diff --git a/.github/workflows/arty-a7-toy.yml b/.github/workflows/arty-a7-toy.yml index 84962fb..d251740 100644 --- a/.github/workflows/arty-a7-toy.yml +++ b/.github/workflows/arty-a7-toy.yml @@ -26,10 +26,11 @@ jobs: working-directory: platforms/arty-a7-toy run: | python3 scripts/verify_target.py + python3 scripts/verify_rob_evidence.py python3 scripts/verify_linux_gemmini_archive.py python3 scripts/verify_linux_gemmini.py --build-record evidence/2026-10-12/linux-gemmini/build/LINUX_GEMMINI_BUILD.json --hardware-result evidence/2026-10-12/linux-gemmini/hardware/RESULT.json python3 -m compileall -q scripts tests host software - bash -n scripts/elaborate.sh scripts/build_test_programs.sh software/build.sh + bash -n scripts/elaborate.sh scripts/elaborate_rob_candidate.sh scripts/build_test_programs.sh software/build.sh - name: Install interface simulator run: sudo apt-get update && sudo apt-get install -y iverilog - name: AXI, UART/SCU and DDR loader interface tests diff --git a/platforms/arty-a7-toy/README.md b/platforms/arty-a7-toy/README.md index 042cfd9..8e72e7b 100644 --- a/platforms/arty-a7-toy/README.md +++ b/platforms/arty-a7-toy/README.md @@ -15,6 +15,14 @@ it boots the original Linux image and passes all five system checks without reloading from the host. See [Flash evidence](evidence/2026-10-12/flash/README.md). Runtime DDR and changes to the initramfs remain volatile. +## 2026-10-12：可选 ROB 存储优化 + +新增 [ROB RAM 候选](ROB_RAM.md)，整板布线后减少 484 LUT、1,657 FF 和 +84 Slice，增加 2 BRAM tile。CPU/Gemmini/Linux RTL 回归周期数保持不变； +后续实物复测已通过完整镜像读回与两轮 Linux/Gemmini 回归，日志追加在 +[PR #9](https://github.com/DangoSys/fpga/pull/9)。默认构建与既有发布版本保留 +原寄存器路径；候选的 Flash 冷启动尚未验证。 + ## 2026-10-12：Linux/Gemmini 实物回归 按标准 rootfs/bbkernel 流程构建的新镜像已完成全部 DDR 读回和实物启动； diff --git a/platforms/arty-a7-toy/ROB_RAM.md b/platforms/arty-a7-toy/ROB_RAM.md new file mode 100644 index 0000000..3c0c7d5 --- /dev/null +++ b/platforms/arty-a7-toy/ROB_RAM.md @@ -0,0 +1,84 @@ +# ROB 操作数存储优化 + +本轮保留 CPU、Sv39、完整 FPU、Gemmini 8×8、23 项 Ball 指令、16-entry ROB、 +bank/缓存容量和板级端口，将 ROB 的两份 64 位操作数移入同步 RAM。 +改动在 Chisel 覆盖层，生成的 RTL 不手工重写计算逻辑。 + +## 实现方式 + +`patches/framework/GlobalROB.scala` 的 `useOperandRam` 默认关闭，保留原发布路径。 +用 `sbt -Dfpga.robOperandRam=true` 显式启用；单元测试直接指定两条路径进行比较。 +新 RAM 为 16×128、1R1W，allocation +写入，选中 issue 指针时读取。既有指针级提供读取周期，背压期间重复读取该指针； +替换指针时，旧响应先进入既有 payload 级，新读取在下一个周期到达。 +控制标志、依赖状态、MSET 提交小字段仍用寄存器。 + +原完整寄存器观察用于 DPI trace/commit，不删调试语义；DPI disabled 的 FPGA +综合会消除仅被调试使用的数据位。禁止同址读写的断言有效，RAM 内容不复位， +有效位和发射状态仍复位。复位后不会把旧 RAM 数据当作新指令执行。 + +`prepare_fpga_memories.py --block-memory robOperands_ext` 显式选择 BRAM；浅层 +其他 RAM 的原映射策略不变。`prepare_rob_candidate.py` 核验全部架构 profile +字段与旧目标相同，并核对既有 memory 几何参数，之后只对新 RAM 指定 BRAM。 + +## 已完成的功能验证 + +- RAM/register 路径逐周期比较通过，共 8,029 周期，含满队列、绕回、背压和两次 + 中途复位；另以接受时保存的完整命令核验 issue 操作数，避免两条路径共同出错漏检。 +- 七类 memory 与实际原 Chisel RTL/独立 scoreboard 比较通过，覆盖全部深度、 + 写 mask、enable、双端口定义内行为及两拍之间输出稳定性。 +- 板级 AXI、SCU、CRC loader 检查通过；原测试二进制不改，四组周期数与基线完全相同： + +| 用例 | 基线周期 | 候选周期 | +|---|---:|---:| +| CPU/Sv39/FPU/AMO/cache/interrupt | 709,434 | 709,434 | +| 原 13 项 Gemmini | 251,063 | 251,063 | +| OS/WS 分块循环 | 684,219 | 684,219 | +| 非对齐/跨页 DMA | 1,914,839 | 1,914,839 | + +完整生成与绑定已通过；候选核心 SHA256 为 +`31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9`。 +Linux RTL 启动、串口命令和五项用户态检查通过，273,506,752 周期与基线相同。 +25 MHz UART 整板实现通过并生成位流；完整报告见 +[本轮记录](evidence/2026-10-12/rob-ram/REPORT.md)。该初始档案保持实现阶段的历史状态。 +后续实物复测已通过完整镜像读回与两轮各 15 个 Linux/Gemmini 程序，新增记录在 +[PR #9](https://github.com/DangoSys/fpga/pull/9)，绑定同一份候选位流摘要。 + +| 布线后资源 | 同条件 UART 基线 | ROB RAM 候选 | 变化 | +|---|---:|---:|---:| +| 物理 LUT | 54,413 | 53,929 | −484 | +| FF | 35,600 | 33,943 | −1,657 | +| 占用 Slice | 15,663 | 15,579 | −84 | +| BRAM tile | 29 | 31 | +2 | +| DSP | 117 | 117 | 0 | + +空闲 Slice 从 187 增至 271，占用仍为 98.29%，不能据此判断足够恢复其他 Ball。 +WNS +1.276 ns、WHS +0.012 ns，无布线错误或 Critical DRC/CDC；普通警告保留。 +DSP 仍包含全部 64 个 PE。这里比较 UART 目标，未混用 Flash 目标的资源报告。 + +## 复现候选 + +在隔离 Linux 工具链目录执行，原基线 SRAM 清单从已验证旧版本的 +`build/serial-bound/MEMORY_MANIFEST.json` 取得；不能传入候选自身的清单。 +构建代理仍遵守 AGENTS 的 MCP 规则，本轮用户已明确授权隔离直接调用作为例外。 + +```bash +bash scripts/elaborate_rob_candidate.sh +python3 tests/check_fpga_memories.py --original build/serial-reference/ToyLinuxChip.sv --bound build/serial-bound +bash scripts/build_test_programs.sh +python3 scripts/run_board_regression.py +VIVADO=/path/to/vivado python3 scripts/start_rob_board_build.py +bash software/build.sh +python3 scripts/check_board_linux.py +python3 scripts/verify_rob_evidence.py +``` + +回归需按原流程准备 `cpu-smoke`、`gemmini-tests`、`loop-stress` 和 `dma-beat64` +测试二进制；本次从旧隔离目录只读复用并在结果里记录摘要。Linux 检查使用同一份 +原标准 payload，执行 `scripts/check_board_linux.py`，结果在 `build/board-linux-final/`。 + +候选 launcher 使用原整板 Tcl、原 25 MHz 约束和原策略，外层一小时 timeout。 +其结果不继承旧实物资格。默认 `elaborate.sh` 仍受旧 `verify_target.py --core` +摘要门限保护；候选走上述独立入口和 `verify_rob_evidence.py --core`。 +后续候选已临时上板并通过上述回归；其 Flash 启动版本仍未生成或验证， +现有发布包不替换。 diff --git a/platforms/arty-a7-toy/SOURCE_LOCK.json b/platforms/arty-a7-toy/SOURCE_LOCK.json index 49248f5..19dbe30 100644 --- a/platforms/arty-a7-toy/SOURCE_LOCK.json +++ b/platforms/arty-a7-toy/SOURCE_LOCK.json @@ -6,7 +6,8 @@ ".gitignore": "5eaf4f0d4cbefc5292732eb17cd984839a8fe4cfc65f39352c187fd73c95947a", ".jvmopts": "a66471d84e6e2ed0c3c40d5ebbc237d268ed9b04f3528ef22e967a2bd4e8aa44", "FLASH_BOOT.md": "471bcd9c9704bd2eedf11880c27c48d0505a56498e62e68ada84d5cd5ed70686", - "README.md": "d1a1326934b5f211f617b0528ca6d85fde5771d8ca32f0c85add7ffcb8310264", + "README.md": "6b1ff7e6d6273aa9f9874735bf6b22b7ba6c15b7df81b8b8bc76e41c9aa61f51", + "ROB_RAM.md": "2160a3dc8130464cf6d54aa03d64eadb13d4fc28c3a64cabfe54c3d5dfed86de", "SOFTWARE_BASELINE.json": "3a5c9f65771e6fd7f8172674baf22263ba7c2d9244993c9162ba526344a7b0aa", "THIRDPARTY.md": "02ed1d3ddd4fc26a8b1580eb4948ff6cf4f548c0434c89f1c6c2220bed3d4a42", "UPSTREAM_MANIFEST.json": "c4a96343e318c452420cf86b34d6008140560eeffa91cd85b4b87b229717c9be", @@ -40,7 +41,7 @@ "boot/flash_boot.c": "98d353e13a32fe3788a78a59da664aeb3b8ea7bc8b1d15951e377122bd8a593e", "boot/flash_start.S": "10a3c3dae05a2b3d99a58778a2815187e3fc34cd4200cfc8ff766602a022894c", "boot/requirements.txt": "f957a1197432942b8e01f3ba222639d0a341a93360a6bad23a99b6a9c3496a5f", - "build.sbt": "e41d7a540c61879ccf1adde9cb1dae2a203b0f619c625a51838c323cce24c966", + "build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", "config/gemmini-8.toml": "7a34b166586b25e2bcb0849764a4f0d969b60493ba2d8d59f4e2176771c07195", "dependencies.json": "932815e2f03b3caf8a1ab4c17baa9bc1962633d1fe8a26168f97d60f0a6844c4", "evidence/2026-10-11/BOARD_REPORT.md": "a349e25ba696c037c54a7a44bcadda163dc43092f6dc5c573968db6b27908366", @@ -243,6 +244,99 @@ "evidence/2026-10-12/linux-gemmini/sources/software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec", "evidence/2026-10-12/linux-gemmini/watchdog/RESULT.json": "efc60f10a891ba2e224ee3130d4e776c00fc04eea5cc2e522690f85ddfb0475e", "evidence/2026-10-12/linux-gemmini/watchdog/check.log": "58de5f54346dfd805737aea528347a5fa9430a7a0962964a08b349ede52b6303", + "evidence/2026-10-12/rob-ram/INPUT_MANIFEST.json": "1185e957c6d0be808e34be4b209e92252c81ebfc75ec048426f830ba6a29ae10", + "evidence/2026-10-12/rob-ram/MANIFEST.json": "7109733e237bdbdbc00e1ab71be472c013d6cc84695b3c206227c56eb5971bd8", + "evidence/2026-10-12/rob-ram/MEMORY_MANIFEST.json": "35a43d93e5bde0cd6b0379dc2755497d660e179a5ed190cec3de259e427226b4", + "evidence/2026-10-12/rob-ram/OPTIN_RESULT.json": "bdb1d489c2d4e7d7fa4757d104bbc155f504f75ab75be26f79005b546f0c8b9b", + "evidence/2026-10-12/rob-ram/REPORT.md": "69e3e3cde262b0ac3b09099d062d9031962a88bfd568f0ec3518eeb265dde034", + "evidence/2026-10-12/rob-ram/RESULT.json": "c415cbbe90ff1ae4bd699c8312453847f025e0ece0bdbdc0722650e972ca8b1d", + "evidence/2026-10-12/rob-ram/ROB_RAM_PREPARED.json": "02297158d70b14e0c1fe9ea51f47b43391d0721bd6f2f0fffeb988c161a24347", + "evidence/2026-10-12/rob-ram/ToyLinuxChip.profile.json": "57e251b00a486f406e5e27f666f4416be730b4e08c8838584e4aac49ebb30f86", + "evidence/2026-10-12/rob-ram/implementation/RUN.json": "905863a76131fcac84f7164b461f03186497c61753565b08209a0872a722bcaa", + "evidence/2026-10-12/rob-ram/implementation/bus-skew.rpt": "a750a81d15159a1d57d0e73e3c78d9d27570fdc11099da2a60225cf744dd5f20", + "evidence/2026-10-12/rob-ram/implementation/cdc.rpt": "135fb071ef679e297772e213428481193b604b70e122ae57df1b397c7a73c17f", + "evidence/2026-10-12/rob-ram/implementation/check-timing.rpt": "a97227785473b88d223f328775f146737b4282ffaf5f51835b0b372205733bd3", + "evidence/2026-10-12/rob-ram/implementation/clocks.rpt": "0e713fd3d6d35c3949547f7a21f3009e6540d3db40c70da83c80689ddeeb6181", + "evidence/2026-10-12/rob-ram/implementation/console.log": "cc9e8209337460ff1cc5fc9bb7db8e07030a9dc63b9853b7fbb11e597b4bab2a", + "evidence/2026-10-12/rob-ram/implementation/drc.rpt": "e0c062aa6e13a01a4feed37ea85bff0a8f6ae05ca266d77967bcf432e2195769", + "evidence/2026-10-12/rob-ram/implementation/io.rpt": "ee1accd10f5e79dd52619cf97f94d34c3d0bfc65c9689e5a6212cc9f0bc89b8e", + "evidence/2026-10-12/rob-ram/implementation/ip-status.rpt": "b6857949e988e7407d0aebf28e68a53e94248a26fc0f5f87fa2395e047a86d97", + "evidence/2026-10-12/rob-ram/implementation/launcher.log": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", + "evidence/2026-10-12/rob-ram/implementation/methodology.rpt": "b1f11140bdc20a7b25a7691b462411020d7528d9dd0dae02ff7e7d5715f9274e", + "evidence/2026-10-12/rob-ram/implementation/opt-utilization.rpt": "e503a8dbd9140caf4e8ece6e2bba6b4547c70e20de86e05e2bd25f0f229b0d83", + "evidence/2026-10-12/rob-ram/implementation/phase.txt": "a4bccf5c13ef5ff8311e59b34d492bc7072a55298723601a6a9c127053aee8fc", + "evidence/2026-10-12/rob-ram/implementation/route-status.rpt": "940f9a8a05963ffdc7ffc304e6f4226be99a07b3f5a83199d5bcd6e289897742", + "evidence/2026-10-12/rob-ram/implementation/routed-hierarchy.rpt": "86bbcd4a653265301c3212a26d6980b20e628d2ffa98f43896874aaea3918187", + "evidence/2026-10-12/rob-ram/implementation/routed-timing.rpt": "3c02fb09120654dba434c5b438117228bf2965953a5fb23f82d162736904bafe", + "evidence/2026-10-12/rob-ram/implementation/routed-utilization.rpt": "c5e97613245378c1cf377f5d464b93354ec980376e6a63c272d379d96db1bf5e", + "evidence/2026-10-12/rob-ram/implementation/synth-hierarchy.rpt": "33723226ef28dd33f17075726ada64f2e92771b5b05686fe150078e7dbb1f0a2", + "evidence/2026-10-12/rob-ram/implementation/synth-timing.rpt": "d6a2cc3a07c5cdd384567081a903c79ba3bccdde3e875c2f189eea9437cd9bd7", + "evidence/2026-10-12/rob-ram/implementation/synth-utilization.rpt": "d26984e3af4d6c3973f9230f72d683064e6df0d6ef0c486a245b94a605f1336a", + "evidence/2026-10-12/rob-ram/implementation/vivado.jou": "3b780c0944a5a818873709d6700298ccdc5126def0d877da58fdb81caeebb04c", + "evidence/2026-10-12/rob-ram/implementation/vivado.log": "ae9f34b1c0a0648e96b25088aa5336c2ecb269d12c5e0d002ed6ede00c23077c", + "evidence/2026-10-12/rob-ram/sources/board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "evidence/2026-10-12/rob-ram/sources/board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "evidence/2026-10-12/rob-ram/sources/board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "evidence/2026-10-12/rob-ram/sources/board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "evidence/2026-10-12/rob-ram/sources/board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "evidence/2026-10-12/rob-ram/sources/board/backup_flash.tcl": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "evidence/2026-10-12/rob-ram/sources/board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "evidence/2026-10-12/rob-ram/sources/board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "evidence/2026-10-12/rob-ram/sources/board/flash_boot.xdc": "bbf9e250ae28dcc4f54d00effd918811f723a7563b4ceacb7b1d03a29151f4ea", + "evidence/2026-10-12/rob-ram/sources/board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "evidence/2026-10-12/rob-ram/sources/board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "evidence/2026-10-12/rob-ram/sources/board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", + "evidence/2026-10-12/rob-ram/sources/board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "evidence/2026-10-12/rob-ram/sources/board/program_flash.tcl": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "evidence/2026-10-12/rob-ram/sources/board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "evidence/2026-10-12/rob-ram/sources/board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "evidence/2026-10-12/rob-ram/sources/board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "evidence/2026-10-12/rob-ram/sources/board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "evidence/2026-10-12/rob-ram/sources/board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "evidence/2026-10-12/rob-ram/sources/board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "evidence/2026-10-12/rob-ram/sources/board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "evidence/2026-10-12/rob-ram/sources/board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "evidence/2026-10-12/rob-ram/sources/board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "evidence/2026-10-12/rob-ram/sources/board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "evidence/2026-10-12/rob-ram/sources/build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", + "evidence/2026-10-12/rob-ram/sources/patches/framework/GlobalROB.scala": "dbfc0583355accfdd6a5287b06a78de07b8408705cec38a77d8544f6f108beb0", + "evidence/2026-10-12/rob-ram/sources/scripts/bind_fpu_rf.py": "3551d10b12139d3ce87615f71c5750c65da385d278111852337c2b74c92ba889", + "evidence/2026-10-12/rob-ram/sources/scripts/check_board_linux.py": "baf23e20a55cc5e3c74d663e9be6fb5f21134a5428445f4e688f97e3b0ed5647", + "evidence/2026-10-12/rob-ram/sources/scripts/check_globalrob.py": "d9476b99ea8f68ea1b22fe62648433314c711fb40162349824f9fe89182517b4", + "evidence/2026-10-12/rob-ram/sources/scripts/prepare_fpga_memories.py": "9d40763492ebbf2bc5aa183e760ec349e31765a0e999af88f476d5e945ab74c4", + "evidence/2026-10-12/rob-ram/sources/scripts/prepare_rob_candidate.py": "321b4569d2638342a7c0002ba1db3eb72229c369397289a11ed49633b1f27823", + "evidence/2026-10-12/rob-ram/sources/scripts/run_board_regression.py": "7302be4d5517eb315eb37b3ff8972bf17e2fe42990ae1fb6702c43c632515bfd", + "evidence/2026-10-12/rob-ram/sources/scripts/start_board_build.py": "04c5a521bcd7014774e6b476e8395bde134de9096bb22e6d6b6f200bf4311c83", + "evidence/2026-10-12/rob-ram/sources/scripts/start_rob_board_build.py": "0c99afafe707a51fba935a59076288a50b7179e01d330f8a1294c81ee1956cf9", + "evidence/2026-10-12/rob-ram/sources/src/main/scala/EmitGlobalRobCheck.scala": "5d366fce3e96278f60c648dc114896246b5c595c8ef783986524e6583c490a05", + "evidence/2026-10-12/rob-ram/sources/tests/tb_globalrob.sv": "8ded6fc969a05ead874fd8771b86dadafe51f7ccec54fafd55a9d48a4e7361a6", + "evidence/2026-10-12/rob-ram/tests/BOARD_REGRESSION.json": "8a2b20c212377c8fbf57cde884f0b66f4fc813ccd0b512ae7e09101d73708a05", + "evidence/2026-10-12/rob-ram/tests/board-unit/RESULT.json": "0936b6beacc5e2e7f9933a47b66d1d7a1406c600dbc276211e6ca231eb0034b6", + "evidence/2026-10-12/rob-ram/tests/cpu/RESULT.json": "9b046bb3db28ae6a5fd427ccf1a2790094be0afb1f772766b814968895b3195d", + "evidence/2026-10-12/rob-ram/tests/cpu/compile.log": "25f8949664f517263b62a194839d11709f27240cbfc2bbb7a57221961acce325", + "evidence/2026-10-12/rob-ram/tests/cpu/simulation.log": "d97f1dfee2d17a4ffca8d4ee86efe040b8ffba08e0080057a43c1bfe082ddc5f", + "evidence/2026-10-12/rob-ram/tests/dma/RESULT.json": "ec2727e85728f341b18775edfadddf00e2fef2b3a29b9797608f1487bef74375", + "evidence/2026-10-12/rob-ram/tests/dma/compile.log": "bfac229450f4bef3f236f4d1b19f9b2e67bc74dfe352e0fccad563ac68a12492", + "evidence/2026-10-12/rob-ram/tests/dma/simulation.log": "dd22077918a0b85716f625e14d2819aff818b93691b54d687322996ab64394f5", + "evidence/2026-10-12/rob-ram/tests/gemmini/RESULT.json": "c4e6e44f8565b0f49b7acaa40f2b804b327aa7a6d0257ce2b8af8e13426a25f7", + "evidence/2026-10-12/rob-ram/tests/gemmini/compile.log": "69bfeb5bcd843542e261bdb6b3fa72af49c8b59021c186cd9f1fb56fa5b3e84f", + "evidence/2026-10-12/rob-ram/tests/gemmini/simulation.log": "03ef554f06f97740822c49ff114ebe8739c8748d09c7f4f08819c6fc88184f36", + "evidence/2026-10-12/rob-ram/tests/globalrob/RESULT.json": "121502749440c24b3d8c51684fa4048aae8eafec2fb746fd47e894fceec31bd1", + "evidence/2026-10-12/rob-ram/tests/globalrob/compile.log": "2dc0c38004c7fff3dfcaae5bd4e11ed5afd580380cf7cc3173b34d81be9f2724", + "evidence/2026-10-12/rob-ram/tests/globalrob/elaboration.log": "ca0a55d7eba76adb6b64af774222976bf5c5c0b81bf43b7592625568813dd5ed", + "evidence/2026-10-12/rob-ram/tests/globalrob/simulation.log": "e9a67784ab366ef90305cfccd16c9b10098b39bcc777c98e6aae62e4ac784a2d", + "evidence/2026-10-12/rob-ram/tests/linux-final/RESULT.json": "5322d8de3f9d8ecf7f09896ff2ce1e7a46d6f73a3279c59cce1bf84f80e3bf54", + "evidence/2026-10-12/rob-ram/tests/linux-final/compile.log": "44814c4eced3b014bf5aefc907cc54007272a0cbdbf1cc889f35d9d3d688055e", + "evidence/2026-10-12/rob-ram/tests/linux-final/simulation.log": "cd018ca60b8dc30d71a2660cf0c95d6d56b99e5d4227b604765b57f6e068b83f", + "evidence/2026-10-12/rob-ram/tests/loop/RESULT.json": "27079c6da7a232dbf2b242c0ca636f7bc8bae3dcbddee7994c844901d43db54e", + "evidence/2026-10-12/rob-ram/tests/loop/compile.log": "d1b8feed50e6b399cad22ae474f6dc1cba6661ecad9dfba39b34c8e5a686c02c", + "evidence/2026-10-12/rob-ram/tests/loop/simulation.log": "a59270b83489f8db4aaaaac305f5b02330deea8eeef2fbe3cb70b9660471a484", + "evidence/2026-10-12/rob-ram/tests/rob-board-regression.log": "bb23554efb3b6ddb80e4b2c9e5eaf357e3d606e14de215149a78060065a6b0e0", + "evidence/2026-10-12/rob-ram/tests/rob-core-binding.log": "8b81fb50e87a24078deb03fe215a59242ba82fffd39420062788d0c735f2793e", + "evidence/2026-10-12/rob-ram/tests/rob-core-elaboration.log": "892792151faee44e8d609c2d69b5877b0ba4e33247b8adbdd63124b97e285766", + "evidence/2026-10-12/rob-ram/tests/rob-memory-regression.log": "20000b4d1b563dde9bceeedb097d5370003a4ffe618ded9ace2e77623caf4071", + "evidence/2026-10-12/rob-ram/tests/rob-optin-candidate.log": "37ef56b723b73f2abbf93cf9158048e1170c070dfb9786a51b276098a012d3a4", + "evidence/2026-10-12/rob-ram/tests/rob-optin-default.log": "a6357910977360b5ac6aeaa3cd3c93506e2cf1da42bb072fdd73cb58a8cd5d84", "evidence/README.md": "058e5d4580d68897450dd08eb114469007f9d931bfcd5423809cd1d12811cde0", "host/check_linux_gemmini.py": "3b23497e7b5b3516af22abb1fc38da48055c60dd786f75f5ada3faa201ca9268", "host/check_watchdog.py": "0d35f150a4cff87d99d6c368e9d1ba62312db9b780210bdb33269881421cc573", @@ -259,6 +353,7 @@ "patches/buckyball/GemminiExCtrlPreloadStates.scala": "ad7543bb8413d7fa21df77b3fcc88a27bae16a452b87333032e88f745e43c6bf", "patches/buckyball/GemminiExCtrlStoreOps.scala": "781a6073d2bf123e4f5c0d77b4188044338fab33534849c8bf96f1eea50fe3c4", "patches/buckyball/LoopMatmulUnroller.scala": "5128a8d92aff95d7823a4583ca34fe948c746158266967ec6f646996fcedaa37", + "patches/framework/GlobalROB.scala": "7998e486ffa0f6e4f1cdb3ee991ed5a7c8d389268da94e4fbbc9a9bd56573c7d", "patches/framework/MemFrontend.scala": "a6bda2ac845452ebed3343360c2c81a02a01ca0f819f16da3b49d32b4fa04a0d", "patches/framework/MemGroupQueryArbiter.scala": "0a7ff5bdcab5a541e419ec237f0db21bd77e47254459d6a7fa18e8f0b8a13b1c", "patches/framework/MemLoader.scala": "88f601e5e9baab940fd64bb067d046e6607ad2b0fcec7747dd58fb175126514a", @@ -288,20 +383,25 @@ "scripts/check_board_linux.py": "baf23e20a55cc5e3c74d663e9be6fb5f21134a5428445f4e688f97e3b0ed5647", "scripts/check_board_uart_boot.py": "f76a2cd9e255f437652c05793b4299c35c920c97e22ac1b1a9d1dce0f779968d", "scripts/check_flash_boot.py": "db6f63febbe4dc0b1800df4a13a307380303c871946e31b5d344ea5e13baaf49", + "scripts/check_globalrob.py": "d9476b99ea8f68ea1b22fe62648433314c711fb40162349824f9fe89182517b4", "scripts/elaborate.sh": "fc23feeac3ddaedb3368b87d2dd5f97025242ac59ecc664b974fa7ce313cd2da", + "scripts/elaborate_rob_candidate.sh": "ce65656a3ae6c9fd49d651b9cef434cf8cf3bcfb393180d210f233741c6ffa0f", "scripts/export_capabilities.py": "d741bddf8ef92fa3116bc5b33f24b9c9403c1b39b98c4c9701a8015cd02de78d", "scripts/make_flash_image.py": "7944308a95cf3c99b42203496a95ebd269a929aff1f6b3bdccb9efa7383bce23", "scripts/prepare_flash_boot.py": "75ff16be3f820dc2e9e167132d0ca4f20e67ca359a95398413e80430eebf2101", - "scripts/prepare_fpga_memories.py": "e9914433d01be3cbc253f237934d674a360dd4b97c2b0799b1e67cab5f5fe294", + "scripts/prepare_fpga_memories.py": "9d40763492ebbf2bc5aa183e760ec349e31765a0e999af88f476d5e945ab74c4", + "scripts/prepare_rob_candidate.py": "321b4569d2638342a7c0002ba1db3eb72229c369397289a11ed49633b1f27823", "scripts/prepare_sources.py": "eb3637a141d4ef30659eb8086d1d59ec159c710ee81d9f8e64fc38b811632799", "scripts/remote_linux_gemmini.py": "2221acd85bc1876d7730f15bb01f0b50629c2a9b9645b4d12cb74e566cf1e686", "scripts/resolve_config.py": "1c4fb7d8533e659c7f8cb9e0ef5eb93f06d29a51d6b3e2449efe648f8f74000d", "scripts/run_board_regression.py": "7302be4d5517eb315eb37b3ff8972bf17e2fe42990ae1fb6702c43c632515bfd", "scripts/start_board_build.py": "04c5a521bcd7014774e6b476e8395bde134de9096bb22e6d6b6f200bf4311c83", + "scripts/start_rob_board_build.py": "0c99afafe707a51fba935a59076288a50b7179e01d330f8a1294c81ee1956cf9", "scripts/verify_flash_evidence.py": "6db7b0dcc7323ba07ec6f17d0a09f04b321f8bdd24582ca49184dd654c1ebd45", "scripts/verify_hardware_evidence.py": "60f3555a6b6ac6a9f567cf1b22caca9755bd4179dcea1f6731a70f8bd26a1202", "scripts/verify_linux_gemmini.py": "1413703dfa42a6be6ac60e0df6bf3eb95ce8b50671a3a803c7421302eace7b2b", "scripts/verify_linux_gemmini_archive.py": "cf8ab6737b2ad3525cf91e528aab64d78261146dec7473596d321812f3bad5e0", + "scripts/verify_rob_evidence.py": "584033d959522151572deb863c8213ef4ffc236e9ea60beb5dee1cb21fac0a1a", "scripts/verify_target.py": "39bdd529e55f2b36bed4ba6b10a4b0a400fcb685f6f3e5886d537e8c549932cd", "software/GEMMINI_LINUX.md": "31d991de14e315a1cf8ca24f5d3715a25a13d8601c8334687730a5b47959a963", "software/MODEL_COMPATIBILITY.md": "1e3a78574d019f4a3e1442b899cc654f2c5a3e41cf55a7650610eed75618a1cf", @@ -313,6 +413,7 @@ "software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec", "software/prepare_platform.py": "f053463897045e1929d65aa9614b7b871c1c6c342f1f15865793883c858f3d61", "src/main/scala/EmitFmaChecks.scala": "1d6eef40cefb36aaf0ce73838f2954cd89d09ad8c97244a2ac346da7137dccfd", + "src/main/scala/EmitGlobalRobCheck.scala": "5d366fce3e96278f60c648dc114896246b5c595c8ef783986524e6583c490a05", "src/main/scala/EmitGroupQueryCheck.scala": "ae3a7bb5a7d951109596bc3e481a9a275e14f04a7cf6ec28084d50f354122ee1", "src/main/scala/EmitPeChecks.scala": "38a88a8a59dcbdf1b4bf3b833679800c5e8505c18782f13719a7e7ec11fd100e", "src/main/scala/EmitRoundShiftChecks.scala": "964a7631e50fe9a7a6024fbcb3c4ae857ea49a6c77435ab1ec269e510a0af7b0", @@ -381,6 +482,7 @@ "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", "tests/tb_fpu_rf.sv": "6d2e61c50907fee0125a0be9acf35ff718fb8615554e6b5f064cfe1e88beaf25", + "tests/tb_globalrob.sv": "8ded6fc969a05ead874fd8771b86dadafe51f7ccec54fafd55a9d48a4e7361a6", "tests/tb_group_query.sv": "3461eda9a029ef0259daff3d5f58f43894e20893dbc489a3e64c8eda83c3f921", "tests/tb_round_shift.sv": "d6cad7539f59f5dcb5c572cfb983828e35665586be79fea55fdb7471f895ae4f", "tests/tb_subrob.sv": "fdaa673650870895e823491e835f351372ec18a73cdd0a188107a956c3d336a4", diff --git a/platforms/arty-a7-toy/build.sbt b/platforms/arty-a7-toy/build.sbt index c29b46e..79eb11f 100644 --- a/platforms/arty-a7-toy/build.sbt +++ b/platforms/arty-a7-toy/build.sbt @@ -57,7 +57,7 @@ lazy val root = project.in(file(".")).dependsOn(inclusive, gemmini).settings(chi val directories = Seq("balldomain", "builtin", "dpi", "frontend", "gpdomain", "memdomain", "top", "system/core/rocket", "system/core/accelerator", "system/tile") val shared = directories.flatMap(d => ((framework / d) ** "*.scala").get) - .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) + .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "GlobalROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) shared ++ ((baseDirectory.value / "patches/framework") ** "*.scala").get ++ ((baseDirectory.value / "patches/buckyball") ** "*.scala").get ++ ((upstream / "arch/src/main/scala/sims/hash") ** "*.scala").get ++ Seq("gemmini", "trace", "mxfp2int", "relu").flatMap { name => val ball = upstream / "examples/balls" / name diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/INPUT_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/INPUT_MANIFEST.json new file mode 100644 index 0000000..f0d60a8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/INPUT_MANIFEST.json @@ -0,0 +1,395 @@ +{ + "source_files": { + ".gitattributes": "8d9ebca04236fcd49c43562b5c6ca1d88ded1ff8c8d437fbdfe3822a5ec22d74", + ".gitignore": "5eaf4f0d4cbefc5292732eb17cd984839a8fe4cfc65f39352c187fd73c95947a", + ".jvmopts": "a66471d84e6e2ed0c3c40d5ebbc237d268ed9b04f3528ef22e967a2bd4e8aa44", + "FLASH_BOOT.md": "471bcd9c9704bd2eedf11880c27c48d0505a56498e62e68ada84d5cd5ed70686", + "README.md": "d1a1326934b5f211f617b0528ca6d85fde5771d8ca32f0c85add7ffcb8310264", + "SOFTWARE_BASELINE.json": "3a5c9f65771e6fd7f8172674baf22263ba7c2d9244993c9162ba526344a7b0aa", + "SOURCE_LOCK.json": "4ce50a70e3fc084865729f132d9d6cd94660f4363d519fd9416e3032b60d04ba", + "THIRDPARTY.md": "02ed1d3ddd4fc26a8b1580eb4948ff6cf4f548c0434c89f1c6c2220bed3d4a42", + "UPSTREAM_MANIFEST.json": "c4a96343e318c452420cf86b34d6008140560eeffa91cd85b4b87b229717c9be", + "VALIDATION.md": "ec3963aee9098723fe7bce0910ac66e7169752e81ae2a687c454154d58f4b610", + "board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/backup_flash.tcl": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/flash_boot.xdc": "bbf9e250ae28dcc4f54d00effd918811f723a7563b4ceacb7b1d03a29151f4ea", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", + "board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "board/program_flash.tcl": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "boot/build.sh": "43c59d0f860add6f71d0c37c34b36ba6ea0bb06360eeb6bdd61770970ad177a9", + "boot/flash.ld": "f5a2010b7a4ae0d8327d75954ac26611c8c1b6230d25217766322c70f98aa7b7", + "boot/flash_boot.c": "98d353e13a32fe3788a78a59da664aeb3b8ea7bc8b1d15951e377122bd8a593e", + "boot/flash_start.S": "10a3c3dae05a2b3d99a58778a2815187e3fc34cd4200cfc8ff766602a022894c", + "boot/requirements.txt": "f957a1197432942b8e01f3ba222639d0a341a93360a6bad23a99b6a9c3496a5f", + "build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", + "config/gemmini-8.toml": "7a34b166586b25e2bcb0849764a4f0d969b60493ba2d8d59f4e2176771c07195", + "dependencies.json": "932815e2f03b3caf8a1ab4c17baa9bc1962633d1fe8a26168f97d60f0a6844c4", + "evidence/2026-10-11/BOARD_REPORT.md": "a349e25ba696c037c54a7a44bcadda163dc43092f6dc5c573968db6b27908366", + "evidence/2026-10-11/BOARD_RESULT.json": "ee1568766df33ee52a9a0a624b017939c499ef507cb074699d15959515297ab3", + "evidence/2026-10-11/GEMMINI_CORRECT_REPORT.md": "f8147d1e0e242e5d6f4bd32f3195ab593c3245874bc67f2e61cd8c48dc07ac2d", + "evidence/2026-10-11/MEMORY_MANIFEST.json": "665d31f358abfe3581f97ff9286842fd8df4459a3e7f1494cd91331fe27d2b1d", + "evidence/2026-10-11/PACKAGE_PREFLIGHT.json": "24efd3aa28c2f3278af6027c00d3ab037ad4a360e34fd3600f21cd65b3c0794d", + "evidence/2026-10-11/ToyLinuxChip.dts": "25066498e83fceec215a45be9b626f43d3ade2a3961fbc16003267bf725adf9e", + "evidence/2026-10-11/ToyLinuxChip.profile.json": "57e251b00a486f406e5e27f666f4416be730b4e08c8838584e4aac49ebb30f86", + "evidence/2026-10-11/implementation/bus-skew.rpt": "62be876436f3b2be677c55676f9e8bc647f5f5bcf54a9feb5fd5826fecfbe21f", + "evidence/2026-10-11/implementation/cdc.rpt": "65637904c8e8d9605579041cb9727c786fc4cdbb62fd98639308535522a3c9bc", + "evidence/2026-10-11/implementation/check-timing.rpt": "2ef7f13f64c7938b5cf2bcb578a4cff373cde8fc07f47c9b5dead08a20436927", + "evidence/2026-10-11/implementation/clocks.rpt": "ae3ab19d48f253e820a0de5eae0d9e2184405931faea012977c815208455f700", + "evidence/2026-10-11/implementation/drc.rpt": "243faa83bbd9d78fffd4bed54fec71ecf74a5a53301f9c4827a27cb207baaa24", + "evidence/2026-10-11/implementation/io.rpt": "c6db8566b56a70ed8ccd6842bde2b30446b3d9d0674a2263982e25dc1c9e1fae", + "evidence/2026-10-11/implementation/methodology.rpt": "46e66742d012e3dd4d33362dc6bf2c361665b736ca5f67b0916aa7e6b8e958f0", + "evidence/2026-10-11/implementation/route-status.rpt": "44b70202e6a6d53f4d4f38fab3e10f0c67bf8e496b4e8dc9466e585914afc0c0", + "evidence/2026-10-11/implementation/routed-hierarchy.rpt": "3ff0c98cba57b4f932aca5a8d90c899bbca9757e928d8c779da3f161a0aad9ae", + "evidence/2026-10-11/implementation/routed-timing.rpt": "34a99a60d8f6b589dcd6a17eacc9f8548772818dee8bb01e16b9e1b5f5c875a5", + "evidence/2026-10-11/implementation/routed-utilization.rpt": "0db8fc7991d4c41becbac7a3345fdb94b52befed6723f7ff2db71ac61b4a5997", + "evidence/2026-10-11/software/RESULT.json": "dd766412f7cd645d60a9400b51082fc2c5302aa6ef64fd4479876693a566e66c", + "evidence/2026-10-11/sources/README.md": "8888006f31c05bb5f8f52a634922017d77084d733ea9c43378037608b50c0fbe", + "evidence/2026-10-11/sources/board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "evidence/2026-10-11/sources/board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "evidence/2026-10-11/sources/board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "evidence/2026-10-11/sources/board/axi_scu.sv": "a3d2808a2bcaa1aa4381e51c9df3ba358d96acdbabd08939e60c073c65550dfc", + "evidence/2026-10-11/sources/board/build_board.tcl": "4fdb448d41a2119eade666fc0b26bd436edd5fda2204a4849e40e00ed4050526", + "evidence/2026-10-11/sources/board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "evidence/2026-10-11/sources/board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "evidence/2026-10-11/sources/board/toy_a7_platform.sv": "db7e7bd98ce81d6c538157e462232d380fe7318a2d0cfeb3afed6773ba127c4c", + "evidence/2026-10-11/sources/board/toy_a7_top.sv": "404cf6ab82b7bc0aeff2d3eeb7855f2e2028784ff4408a6c97eec023464c039f", + "evidence/2026-10-11/sources/board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "evidence/2026-10-11/sources/board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "evidence/2026-10-11/sources/board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "evidence/2026-10-11/sources/board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "evidence/2026-10-11/sources/board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "evidence/2026-10-11/sources/board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "evidence/2026-10-11/sources/board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "evidence/2026-10-11/tests/BOARD_REGRESSION.json": "8a2b20c212377c8fbf57cde884f0b66f4fc813ccd0b512ae7e09101d73708a05", + "evidence/2026-10-11/tests/cdc/RESULT.json": "25b23cc55bfe3904aa23a2aef885b531328419f58f7cc12bdbea127bf64c73e8", + "evidence/2026-10-11/tests/cdc/simulation.log": "ad8102974d99e3d16b21a334d1b875dda5030fb13ad721c0118030f3420e0b24", + "evidence/2026-10-11/tests/cpu/RESULT.json": "9b046bb3db28ae6a5fd427ccf1a2790094be0afb1f772766b814968895b3195d", + "evidence/2026-10-11/tests/cpu/simulation.log": "b8d24f91d2e1edaec5199ee84a99eb713523614419449b49391e19d3e725be2f", + "evidence/2026-10-11/tests/dma/RESULT.json": "ec2727e85728f341b18775edfadddf00e2fef2b3a29b9797608f1487bef74375", + "evidence/2026-10-11/tests/dma/simulation.log": "d9c2251d494cf322013db41114681be326b519a11fd785bcc416e13d94b58e68", + "evidence/2026-10-11/tests/gemmini/RESULT.json": "c4e6e44f8565b0f49b7acaa40f2b804b327aa7a6d0257ce2b8af8e13426a25f7", + "evidence/2026-10-11/tests/gemmini/simulation.log": "4006a795fde1828d030afeaa5c29684e2085c6f8ea5940fbf8be6970b88076af", + "evidence/2026-10-11/tests/linux-final/RESULT.json": "5322d8de3f9d8ecf7f09896ff2ce1e7a46d6f73a3279c59cce1bf84f80e3bf54", + "evidence/2026-10-11/tests/linux-final/simulation.log": "41f1684440002e5e7a9310c7af6bb88e0e467938d5e2d00a5ba932eec26bf2b6", + "evidence/2026-10-11/tests/loop/RESULT.json": "27079c6da7a232dbf2b242c0ca636f7bc8bae3dcbddee7994c844901d43db54e", + "evidence/2026-10-11/tests/loop/simulation.log": "1e2d1dd276bbc626de30bd774dd3e9575f9df753aabb707280fc24c281339f13", + "evidence/2026-10-11/tests/uart-boot/RESULT.json": "46fa4f7f8c510a7d15bb28fd5afbecea196e8e6c80d14f4968f6d1215ef8e62a", + "evidence/2026-10-11/tests/uart-boot/simulation.log": "a3f5e2eeffd05e81ebf75fc9b3db693fa458308c52e27ce6de58710f87746def", + "evidence/2026-10-11/tests/unit/RESULT.json": "6253cd9add8621d2581c70edae034aafd6ce95ecb78adb4c12813f4297947089", + "evidence/2026-10-12/README.md": "8288b95ca8a1986394e0766e384a2aee3915ba08c9d05beb21522b7dc162a8be", + "evidence/2026-10-12/flash/FLASH_RESULT.json": "5a5c8e21587cae91df24d441d583dc921a234f0514bf0d72e7cdd7655145ff92", + "evidence/2026-10-12/flash/MANIFEST.json": "296430d37fa0b67e43abdc492f0cbbeb358c6d88195a75b1fcec8f52d19b0e8d", + "evidence/2026-10-12/flash/README.md": "4aec80e940a31174e19cb41bd8460acdf073bd2e07f6fa8191810e9bc8d17912", + "evidence/2026-10-12/flash/hardware/AUTOMATIC_BOOT_RESULT.json": "feb7d92ca4b20cf61a30457c106ea69a037c3df4f10341442df0f5e38855cc0d", + "evidence/2026-10-12/flash/hardware/RESULT-monitor-interrupted.json": "525848d5cdfe2944c0242dc3c31853a0f37dad085159d91f07d2a751b7284095", + "evidence/2026-10-12/flash/hardware/cold-boot-1.json": "2398886bf5cae63dd21096cd330e4706db21c9fa6f8c9c52adf531e95ee41d44", + "evidence/2026-10-12/flash/hardware/cold-boot-1.log": "e40b11c9ba506c9c3438a8eb3d58f006f6e7033fc0d1374b45a316f607fcf9da", + "evidence/2026-10-12/flash/hardware/cold-observer.py": "7beecce577edcc6ede47f66eff456abd13430a04919cc0ce03ee03abeb539a12", + "evidence/2026-10-12/flash/hardware/command-1.log": "41dce217c172b02d32aeac2a377703b11d845d570f59e6f3afbfd53b65090334", + "evidence/2026-10-12/flash/hardware/linux-console.log": "df9e249f7257e97089a61c8a19ac6ce1b4815777ff4c4ddfcb81a4f7c6ac874c", + "evidence/2026-10-12/flash/hardware/program.jou": "7db8abe5e3d98d3fec16adb503f13fb2df8e29c5dfcd97c65b2173a728ec5a52", + "evidence/2026-10-12/flash/hardware/program.log": "0dd1d38183ef4c82d0c0c7eec8b16fb1913037e070fe0095fb5624b4af610306", + "evidence/2026-10-12/flash/implementation/RUN.json": "1a01b286dbd865efd5b08c961b421e7d306f02f406e984207ae7bd837cf0207f", + "evidence/2026-10-12/flash/implementation/bus-skew.rpt": "c3f1e3d9cf7342e241268e297059bbb509c6d95d2366113d4e66d4fc82b84331", + "evidence/2026-10-12/flash/implementation/cdc.rpt": "9b5106ca202d509feebccd7449e314bc07fe0c115847acaae381466b36ca603f", + "evidence/2026-10-12/flash/implementation/check-timing.rpt": "3a0cba14e9bdddac9bba4c250d4873fedc9c0bb759ad1ea4fd458afe513ed8a1", + "evidence/2026-10-12/flash/implementation/clocks.rpt": "feba2f7f051b86446a3e8f326c6c2e2644263a7fb154c6099a8c7780b429aa58", + "evidence/2026-10-12/flash/implementation/console.log": "67f00b1c7c0689e231bcd9fed90d64bc03e733c589d05eb3aff7693cb2aa2f23", + "evidence/2026-10-12/flash/implementation/drc.rpt": "08383948521337a99b9b738b7ff71ef8130a6ca6dfe99343ca83ac3ea9da7e0f", + "evidence/2026-10-12/flash/implementation/io.rpt": "d7995825975c4ea130d99b826c1385f9b51877876f6329a1ce57d50d8aefc7ad", + "evidence/2026-10-12/flash/implementation/methodology.rpt": "3ca198b32fce12b11e9e535955cc0f7df89116e030c7051f528225633d275ca4", + "evidence/2026-10-12/flash/implementation/route-status.rpt": "aa557d2816783fb10f403474755b1b1b5e55bc3e4a9902f3374c777472c2ab98", + "evidence/2026-10-12/flash/implementation/routed-hierarchy.rpt": "d4f88def7522cca107288d8854c9c3d6d9dbd2e1ebeb4aeeb8cd88ef84d8cc5b", + "evidence/2026-10-12/flash/implementation/routed-timing.rpt": "4d192e3f96a3c58bc5784babc088964200ff66b01115864c4e8963be744cc756", + "evidence/2026-10-12/flash/implementation/routed-utilization.rpt": "bfb20c8e32b428b2231c80579b55f6ef3ca0dcd642c97af54ed6f176919a35f9", + "evidence/2026-10-12/flash/implementation/vivado.jou": "26344333d0976ce3e5b24489f241dd193c1c2fa851c3ae0d7a57dc9c1fe6d2fe", + "evidence/2026-10-12/flash/implementation/vivado.log": "162cd27c49df41ef1c2fa4fed7c443217ba97d9bc9e4a83163ae82eb085f5fcf", + "evidence/2026-10-12/flash/software/FLASH_IMAGE.json": "5abfd2bcabfbc0aa3c900171d26f34b068e886dbf29c95890adfe41c37d74f2a", + "evidence/2026-10-12/flash/software/MANIFEST.json": "dcae443f8c034f4965b3ae1728868c74041e62bdd6b7cc3d0ef1882a05ab769f", + "evidence/2026-10-12/flash/software/toy_flash.log": "6dd18956cf3b17d446cee82610195808545c0deec09472451c287c9ca473a98e", + "evidence/2026-10-12/flash/sources/board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "evidence/2026-10-12/flash/sources/board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "evidence/2026-10-12/flash/sources/board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "evidence/2026-10-12/flash/sources/board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "evidence/2026-10-12/flash/sources/board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "evidence/2026-10-12/flash/sources/board/backup_flash.tcl": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "evidence/2026-10-12/flash/sources/board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "evidence/2026-10-12/flash/sources/board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "evidence/2026-10-12/flash/sources/board/flash_boot.xdc": "f95adc514f09056bad0e67c5ddc2da65352b4c75a8224791c6903dc841820806", + "evidence/2026-10-12/flash/sources/board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "evidence/2026-10-12/flash/sources/board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "evidence/2026-10-12/flash/sources/board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", + "evidence/2026-10-12/flash/sources/board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "evidence/2026-10-12/flash/sources/board/program_flash.tcl": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "evidence/2026-10-12/flash/sources/board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "evidence/2026-10-12/flash/sources/board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "evidence/2026-10-12/flash/sources/board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "evidence/2026-10-12/flash/sources/board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "evidence/2026-10-12/flash/sources/board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "evidence/2026-10-12/flash/sources/board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "evidence/2026-10-12/flash/sources/board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "evidence/2026-10-12/flash/sources/board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "evidence/2026-10-12/flash/sources/board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "evidence/2026-10-12/flash/sources/board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "evidence/2026-10-12/flash/sources/boot/build.sh": "43c59d0f860add6f71d0c37c34b36ba6ea0bb06360eeb6bdd61770970ad177a9", + "evidence/2026-10-12/flash/sources/boot/flash.ld": "f5a2010b7a4ae0d8327d75954ac26611c8c1b6230d25217766322c70f98aa7b7", + "evidence/2026-10-12/flash/sources/boot/flash_boot.c": "98d353e13a32fe3788a78a59da664aeb3b8ea7bc8b1d15951e377122bd8a593e", + "evidence/2026-10-12/flash/sources/boot/flash_start.S": "10a3c3dae05a2b3d99a58778a2815187e3fc34cd4200cfc8ff766602a022894c", + "evidence/2026-10-12/flash/sources/boot/requirements.txt": "f957a1197432942b8e01f3ba222639d0a341a93360a6bad23a99b6a9c3496a5f", + "evidence/2026-10-12/flash/sources/host/flash.py": "47ad35043c9a04e9f6730dd4d53cf84f0d7bb018a03f76754d549f7bebe936dc", + "evidence/2026-10-12/flash/sources/host/observe_flash_boot.py": "cb2e76647d0ba5af3fc1330613d4e75b8b21eca9bd1624355067a752dbf92483", + "evidence/2026-10-12/flash/sources/scripts/check_board_uart_boot.py": "f76a2cd9e255f437652c05793b4299c35c920c97e22ac1b1a9d1dce0f779968d", + "evidence/2026-10-12/flash/sources/scripts/check_flash_boot.py": "db6f63febbe4dc0b1800df4a13a307380303c871946e31b5d344ea5e13baaf49", + "evidence/2026-10-12/flash/sources/scripts/prepare_flash_boot.py": "75ff16be3f820dc2e9e167132d0ca4f20e67ca359a95398413e80430eebf2101", + "evidence/2026-10-12/flash/sources/scripts/start_board_build.py": "04c5a521bcd7014774e6b476e8395bde134de9096bb22e6d6b6f200bf4311c83", + "evidence/2026-10-12/flash/sources/tests/spi_flash_model.sv": "904377bb59c15643203b991d8414493d2f4f593285ecad63dc01628cb41f28fc", + "evidence/2026-10-12/flash/sources/tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", + "evidence/2026-10-12/flash/tests/board-uart-flash-recovery/RESULT.json": "197a08d2631e31f17b27fe9fa6d571c5882c11e51b6d593ad0b130a04b5540c9", + "evidence/2026-10-12/flash/tests/board-uart-flash-recovery/simulation.log": "c4d564bff2521b4f12e790b12a260701dbfc473529f281b7315607c6791d8578", + "evidence/2026-10-12/flash/tests/board-unit/RESULT.json": "0936b6beacc5e2e7f9933a47b66d1d7a1406c600dbc276211e6ca231eb0034b6", + "evidence/2026-10-12/flash/tests/flash-regression/RESULT.json": "0e12af653bc651607b0701a5e562aedffda0e09d06d464398dc3ffa923dc064a", + "evidence/2026-10-12/flash/tests/flash-regression/bad_header.log": "da911477a6999b7a43de837979c6a5a35ecbb287efde66f8b513f9a21b9eb18d", + "evidence/2026-10-12/flash/tests/flash-regression/bad_payload.log": "2b1155d8cad3c3a00d85e676b5bb17e252592054d2e3e0ef8e396012438dd8bf", + "evidence/2026-10-12/flash/tests/flash-regression/valid.log": "beada20d15f8c8476c9849ed4c698bce487bc983bc12991cc0d7371a36a5c054", + "evidence/2026-10-12/hardware/HARDWARE_RESULT.json": "514fe87e3fb0753d416f670b2b8906e98ae6b6ec49b56154e0833e5863f085e7", + "evidence/2026-10-12/hardware/MANIFEST.json": "dc06cd7d47777269119de6306c03d71c8ddf20efb9708ebdfbcd983a02993481", + "evidence/2026-10-12/hardware/PROGRAM_RESULT.json": "f45536ce8d86fa2a735ab85a9008d662c793f31d3eadc430f426abd09b95c612", + "evidence/2026-10-12/hardware/d2xx_load.py": "bf9a8f8c931b71672932f72992cd03d15977d753eebc891800e6aaefa287218f", + "evidence/2026-10-12/hardware/dfx_runtime.txt": "b70e818734e3af5f8b01153d47a37c50449a5f53b008fb4f23849ec0f957b0b9", + "evidence/2026-10-12/hardware/linux-console.log": "aceb1739620d1b1554b809c849320ed0a5f20f9a6822d1a6c3dd33fca1d6a2d3", + "evidence/2026-10-12/hardware/live-console-first.log": "ac97f527e1ec985ba08ae2b1002a2c14ff0a54fbf8078b94ba4dbe421e3ad005", + "evidence/2026-10-12/hardware/live-console.log": "fb2b77f67b02c6e73e0b7bf1e2dbf3557c1d0b98ef0d69ac4c42191107e99bd6", + "evidence/2026-10-12/hardware/live_check-first.py": "a3e37a9671d8f526d706922cec581727dfa7bb80510789b08b785caa0443583e", + "evidence/2026-10-12/hardware/live_check.py": "822eb8fbb846eb0a41a30eadc163a735dc1932dffdded54dd2117f7aaf0c60e8", + "evidence/2026-10-12/hardware/load-and-linux.log": "9633ad82626f7e59ed0b503f0263c5d620c6b6276a262e385ae8785649c1bd8e", + "evidence/2026-10-12/hardware/program.jou": "9796d9c11dd2f362818c6833a96a9801f14fe25c357fb798db61f00df210d99d", + "evidence/2026-10-12/hardware/program.log": "c754d0f5066dbd34b9035fb77ee6e8ef3fe403b03b56b97f5cdd523aba313511", + "evidence/2026-10-12/hardware/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "evidence/2026-10-12/hardware/summarize_hardware.py": "a0f681a64ca0c441fc614bf8c2ccf664e2de86d02d3d2cfe2eb0b99e7f8edefd", + "evidence/2026-10-12/linux-gemmini/MANIFEST.json": "13a488dcc4975e3936b3f4db81768c4c190602b6cda5d931394efe3e252eeea8", + "evidence/2026-10-12/linux-gemmini/README.md": "77ef4fdb7507cf748201bf751109ac30aaa1f8d3af0d3d52bf53bf5da5f07045", + "evidence/2026-10-12/linux-gemmini/REPORT.md": "0b54513128c3e9432964b1082ebcb04af46b41e8034f7ddef35b7876b2e3a7bf", + "evidence/2026-10-12/linux-gemmini/build/BOARD_FIRMWARE_RESULT.json": "a1c458a50c26a7cd05bf17d362771db241d526d909821f7b2ed32a42ecf5a8c0", + "evidence/2026-10-12/linux-gemmini/build/INPUT_MANIFEST.json": "b1bd6eb8c04f88d9ab1080118e6ed4ba4e760ad121ec1d30ed42936bc59226c4", + "evidence/2026-10-12/linux-gemmini/build/LINUX_GEMMINI_BUILD.json": "4d9229135d7f92b711c385628fcd96839ad0e667a6579f87d8f604ce8dd7cda3", + "evidence/2026-10-12/linux-gemmini/build/SESSION.json": "06e0cb8cd341a395a87d514381422da405c3c08c5312c69fd71a72a82b00ceb0", + "evidence/2026-10-12/linux-gemmini/build/build.log": "1c9ba6e82cae3182025567709bd6796910e194ff30a22f6545ec2ca8967037f7", + "evidence/2026-10-12/linux-gemmini/first-pass/LOAD_RESULT.json": "a36ce2b6e39608aa4d1f0df71ae8354b5e446a360623891b3846a77d0388e657", + "evidence/2026-10-12/linux-gemmini/first-pass/PERFORMANCE.json": "fc681a9d01275898476837e413d4edfcd67fbc1c98fcb8be3ac443fabcfb0e0e", + "evidence/2026-10-12/linux-gemmini/first-pass/RESULT.json": "b2422db3c133cab82d69efe300642ca16c546054b091125c1b208f2cbd42e269", + "evidence/2026-10-12/linux-gemmini/first-pass/boot-console.log": "eb98e070415b15b6500d53eaeebc19b32f526cbe34cd3f2b8f9f652187c900c1", + "evidence/2026-10-12/linux-gemmini/first-pass/linux-console.log": "edf9345b7a7757c4149fc993ad203b541047332d49525fe5ed965de7c026a1b1", + "evidence/2026-10-12/linux-gemmini/generated-inputs/CMakeLists.txt": "4ea8d92e23c19d780fff7d6a2c1369ef3363dc1fe87acf1195656ce852684f4f", + "evidence/2026-10-12/linux-gemmini/generated-inputs/PREPARED.json": "890d8a759be94610a16a5ac976f0775e99220a4e4de3e44abd3c3aeeff99819e", + "evidence/2026-10-12/linux-gemmini/generated-inputs/ballISA.h": "8f74e9230c45bc270c99b4b31fde6db6ed61b01c0055c7c62855de11bb571606", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_linux_check.c": "2fa2f6d73d674d89344ffd058f28712380c2de04d64a88b43fe141e30e9df467", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_cisc_atranspose_test.c": "d4b44df5f004b4e1d4ada02c247e5f66a6596dfa80cf70a09c54d7448b572712", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_cisc_basic_test.c": "481733138780de0ef2ce7d867bc375cd22a64990f33b9eabd8a03a45c2e8861c", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_cisc_btranspose_test.c": "efdf1cefe9277fde1dce1d62eb7c3364ddbb27926e99ddce9800f1fb54be1fec", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_cisc_shift_test.c": "9676b4e45945de9cbe005be695ffd8d0f3a406fa0448875a8372cc1d1c20fb4c", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_risc_abtranspose_test.c": "641982f9adc4b898a27d23967807d9f350c3db717b7c276df42281b7c6ba3558", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_risc_atranspose_test.c": "4583e36cbea777a439e65fb4ca58e51574e2f7686217088922128c36fa8d74f9", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_risc_basic_test.c": "cd8102c88b58a2ea289212779bd2bf50f9e35806e9039f4cc5a6abf73eef131f", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_risc_btranspose_test.c": "01ee05bb7a92de708e1bac4041354d9f0363c70a4f5b898af784f47410f63798", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_os_risc_shift_test.c": "aae1a632fd3fabc1ae9fea89daf9dc0693880c718f100c86b946257935a4076d", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_ws_cisc_conv_test.c": "ab75719d036a6b61b4369514c6771ebac94a04e7448f2127b1be60bab2e8f28b", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_ws_risc_basic_test.c": "f5aab861cf0f764e6179e24c70c75d9f3c7e9a0364a4e3aa818784f7f309c03a", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_ws_risc_btranspose_test.c": "fff4938ea7c16864e3e1b91a2d30ef2d3eabeb3ed4a1153964f5d351d6980279", + "evidence/2026-10-12/linux-gemmini/generated-inputs/gemmini_ws_risc_shift_test.c": "a22209c0c02cd5d5b258525dd6266bbe3a7447b410a082e8da19a268478b6307", + "evidence/2026-10-12/linux-gemmini/generated-inputs/params.h": "cc6bbe816a15f9a7bd133fbeb45d039733a22a6a6f94dace16eecea5eef61b24", + "evidence/2026-10-12/linux-gemmini/hardware/LOAD_RESULT.json": "a36ce2b6e39608aa4d1f0df71ae8354b5e446a360623891b3846a77d0388e657", + "evidence/2026-10-12/linux-gemmini/hardware/PERFORMANCE.json": "696de0aa9b3129ae10369afe8d71553922b577170554a1b2d9639048d89d5b20", + "evidence/2026-10-12/linux-gemmini/hardware/POST_RESULT.json": "3d2ad49575d52bdf4fdcee730a69c7d79b6c5add809f9b7007607c2b883246ac", + "evidence/2026-10-12/linux-gemmini/hardware/RESULT.json": "184efe4a22b4d1078788d74167c40ae8fd65210650f01458d752be927a6e1206", + "evidence/2026-10-12/linux-gemmini/hardware/boot-console.log": "eb98e070415b15b6500d53eaeebc19b32f526cbe34cd3f2b8f9f652187c900c1", + "evidence/2026-10-12/linux-gemmini/hardware/linux-console.log": "e5c5442fa53496bc2c72bb725678fa424c0a73f43a511fee1e678ca7b6ca6729", + "evidence/2026-10-12/linux-gemmini/hardware/post-console.log": "3b9b17bdc1c03a90b6fcc3b66ae796c721f41a3fe1a690dc753bc71ea84311ee", + "evidence/2026-10-12/linux-gemmini/hardware/program-console.log": "e4ee8fb155e0bb01fd4eef92a4e64c560a2921815eb60ce70c0cd72293c2f697", + "evidence/2026-10-12/linux-gemmini/hardware/program.jou": "0e45a26886ecdfaf1dec01dc4b9b256f5a40db1239e1d09f5aa7d439bcd36fac", + "evidence/2026-10-12/linux-gemmini/hardware/program.log": "7e71edb015aa3f1e9afd6b62c13364d7e2e760e6c6a48734de84e66eadbdb304", + "evidence/2026-10-12/linux-gemmini/load/RESULT.json": "a36ce2b6e39608aa4d1f0df71ae8354b5e446a360623891b3846a77d0388e657", + "evidence/2026-10-12/linux-gemmini/load/linux-boot.log": "eb98e070415b15b6500d53eaeebc19b32f526cbe34cd3f2b8f9f652187c900c1", + "evidence/2026-10-12/linux-gemmini/load/transfer.log": "25799c30f382384cc2facce1320f1b11c86d555a7a6364fa3384079886aa39a4", + "evidence/2026-10-12/linux-gemmini/sources/board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "evidence/2026-10-12/linux-gemmini/sources/diagnostics/check_watchdog.py": "de3dea9d9bdff5760788918ad7493651903e5bb633804796de1dd6d840b3d71c", + "evidence/2026-10-12/linux-gemmini/sources/diagnostics/post_gemmini_live.py": "bfc88015da57b0601793b6253ed3b0659391916becbe81dd248c3a1c5e0f97b3", + "evidence/2026-10-12/linux-gemmini/sources/host/check_linux_gemmini.py": "5554ebb0902b9cca203d48889f59ef160ad958aaac1dbb8d37c0579a1c3e5b2b", + "evidence/2026-10-12/linux-gemmini/sources/host/ftdi_transport.py": "f3a88c170f40121febde7fd283a50e54ab5af5b79f0651cb15db9af743d57de7", + "evidence/2026-10-12/linux-gemmini/sources/host/load.py": "a62e48b779c9ce1d6f8f6669523e427cf48bd19be3bf50a554dc391b09b3e3b2", + "evidence/2026-10-12/linux-gemmini/sources/program.tcl": "0ff928503cf00798dae132117435e34981a176c586d7aa16e587c47877ba031f", + "evidence/2026-10-12/linux-gemmini/sources/scripts/remote_linux_gemmini.py": "b99f6cea4cdbc5765cb9778ee12a6485a778f558e1871d40473cd532889c3e60", + "evidence/2026-10-12/linux-gemmini/sources/scripts/verify_linux_gemmini.py": "ef336dfa911a71ef9b64618444864dc4f8620d2b53674422ea238fb1b11c2c26", + "evidence/2026-10-12/linux-gemmini/sources/software/build_gemmini_image.py": "949a59cbc4bd494cbe793b392aaccc237637c809667b6bd5dd211e2176e6fcbf", + "evidence/2026-10-12/linux-gemmini/sources/software/gemmini_linux_check.c": "2fa2f6d73d674d89344ffd058f28712380c2de04d64a88b43fe141e30e9df467", + "evidence/2026-10-12/linux-gemmini/sources/software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec", + "evidence/2026-10-12/linux-gemmini/watchdog/RESULT.json": "efc60f10a891ba2e224ee3130d4e776c00fc04eea5cc2e522690f85ddfb0475e", + "evidence/2026-10-12/linux-gemmini/watchdog/check.log": "58de5f54346dfd805737aea528347a5fa9430a7a0962964a08b349ede52b6303", + "evidence/README.md": "058e5d4580d68897450dd08eb114469007f9d931bfcd5423809cd1d12811cde0", + "host/check_linux_gemmini.py": "3b23497e7b5b3516af22abb1fc38da48055c60dd786f75f5ada3faa201ca9268", + "host/check_watchdog.py": "0d35f150a4cff87d99d6c368e9d1ba62312db9b780210bdb33269881421cc573", + "host/flash.py": "47ad35043c9a04e9f6730dd4d53cf84f0d7bb018a03f76754d549f7bebe936dc", + "host/ftdi_transport.py": "f3a88c170f40121febde7fd283a50e54ab5af5b79f0651cb15db9af743d57de7", + "host/load.py": "a62e48b779c9ce1d6f8f6669523e427cf48bd19be3bf50a554dc391b09b3e3b2", + "host/observe_flash_boot.py": "7beecce577edcc6ede47f66eff456abd13430a04919cc0ce03ee03abeb539a12", + "host/requirements-gemmini.txt": "43ab64f971d4d5ffbbc16009743fb980a06a76d381a2c71e54e9d3aab314cb6a", + "patches/buckyball/GemminiBall.scala": "c18ace5c3ae6645c022af809104e4baf35da657a42ab144ce86260327ebab5aa", + "patches/buckyball/GemminiExCtrl.scala": "ac3ecc72fa7deb5d50c0c42496b19de9d596b4ebaebd24496bf3792c87d85eaf", + "patches/buckyball/GemminiExCtrlCmdStates.scala": "6fc95f3f3f22333e5ad5a90d28a40bfa70fa2593b4ea0be05e42fcfb11235f6e", + "patches/buckyball/GemminiExCtrlComputeFeedState.scala": "ae3aa3fc7e2fa78bd71a976a5ae08fb539658c28b013d78248a82cfb5fc041d0", + "patches/buckyball/GemminiExCtrlDefs.scala": "7595c8df0a05902ba19761836287bfc5bca1951d2341834b399842f692906bee", + "patches/buckyball/GemminiExCtrlPreloadStates.scala": "ad7543bb8413d7fa21df77b3fcc88a27bae16a452b87333032e88f745e43c6bf", + "patches/buckyball/GemminiExCtrlStoreOps.scala": "781a6073d2bf123e4f5c0d77b4188044338fab33534849c8bf96f1eea50fe3c4", + "patches/buckyball/LoopMatmulUnroller.scala": "5128a8d92aff95d7823a4583ca34fe948c746158266967ec6f646996fcedaa37", + "patches/framework/GlobalROB.scala": "dbfc0583355accfdd6a5287b06a78de07b8408705cec38a77d8544f6f108beb0", + "patches/framework/MemFrontend.scala": "a6bda2ac845452ebed3343360c2c81a02a01ca0f819f16da3b49d32b4fa04a0d", + "patches/framework/MemGroupQueryArbiter.scala": "0a7ff5bdcab5a541e419ec237f0db21bd77e47254459d6a7fa18e8f0b8a13b1c", + "patches/framework/MemLoader.scala": "88f601e5e9baab940fd64bb067d046e6607ad2b0fcec7747dd58fb175126514a", + "patches/framework/MemMidend.scala": "ca92e7f34040ac4ff43bbe6ab53ff1adf364a10461dbd09d27da880701764313", + "patches/framework/MemStorer.scala": "b5edae8fd7d7104cc051ec0e222168bea2ceef93311919c9f1661896cdf67527", + "patches/framework/PrivateMemBackend.scala": "279dbefd2849d5eab14630820d5d3c435a498dab56cf95c1934737c0627e1850", + "patches/framework/SubROB.scala": "701ba5c8ca96ee33a0c90e55533463baef1f5abb6ec51aa4a1156cef47a1f715", + "patches/gemmini/FpgaArithmetic.scala": "0789a0955d86579226ea53835c5bc5a1f7513c41bf4fa3b3a005f5f683bf9a32", + "patches/gemmini/LICENSE": "c41aaa8016faefb6d266f5cfbbaeefc32b5ae0ff3c67670be2b1b0cf291ef6e0", + "patches/gemmini/Mesh.scala": "44c2f14ab5fbf6ab23b9aa15c09fa7fcc8f94b7c4e54a0a0c171a95165819db8", + "patches/gemmini/PE.scala": "c637e0cfb2a76cd5299eedcbd248085646e8201799027fac06858f5003af32a6", + "patches/gemmini/Tile.scala": "8bee3fc67cbc6702aba72b805c3858e8cbca7cdecbd317a083b77d108a9e6e08", + "patches/rocket/FPU.scala": "df54736218a12a6ec9f48b93c3d4a626e3e56c8600e3ad712905c481c47e29e3", + "patches/rocket/SharedFma.scala": "e2b00a7b6d5c70cc58d7e39605cf169eb901e1d3e15f33dc46d0d981e831bcbb", + "program.ps1": "78405622ac77e9e723fd6437f9649d8ce8c8762274b6cdc6d29ccbbd85c039a3", + "program.tcl": "0ff928503cf00798dae132117435e34981a176c586d7aa16e587c47877ba031f", + "project/build.properties": "a59fccae87ea7dba4034abbbf5333eaaa3dbb2fdcfbf37e98e3752f28c4a3892", + "project/repositories": "063c457354f9a2bd99f0d1c5c51f0fc3d7ffff04894bb4b740538043fb3b61f6", + "rtl/FpuRfLvt.sv": "bbc9ad168c94204a946b3e107115fae7f6042fd6c7f95807d7af367449e28950", + "rtl/FpuRfOriginal.sv": "c2b85443eb5933ae1b39b7a78080998cecd79d289f29b061c34a0526d52b53b1", + "scripts/bind_fpu_rf.py": "3551d10b12139d3ce87615f71c5750c65da385d278111852337c2b74c92ba889", + "scripts/build_board_firmware.py": "1af5afa3b468fa13a0aaba57a977ba26ff2b0857a765ceda0a0b666fec39b344", + "scripts/build_test_programs.sh": "9985425285919e2597cf2a7d664eda4bf6c2771b9ac57a317940dbfbf7a13885", + "scripts/check_board.py": "a443bd1708e0e7435245be748f7d590e209bfddcb4b246e92a1a0c21445d3ab2", + "scripts/check_board_cdc.py": "9d94d740934d47ebf768135d97ea0b46be8ebd89a9cc6f25ea2b08ef1df493c1", + "scripts/check_board_cpu.py": "4e3a3ccbb34556e4e43b83beb220c92a65094ea5a04d4427c8775ac0c2b41d48", + "scripts/check_board_linux.py": "baf23e20a55cc5e3c74d663e9be6fb5f21134a5428445f4e688f97e3b0ed5647", + "scripts/check_board_uart_boot.py": "f76a2cd9e255f437652c05793b4299c35c920c97e22ac1b1a9d1dce0f779968d", + "scripts/check_flash_boot.py": "db6f63febbe4dc0b1800df4a13a307380303c871946e31b5d344ea5e13baaf49", + "scripts/check_globalrob.py": "d9476b99ea8f68ea1b22fe62648433314c711fb40162349824f9fe89182517b4", + "scripts/elaborate.sh": "fc23feeac3ddaedb3368b87d2dd5f97025242ac59ecc664b974fa7ce313cd2da", + "scripts/export_capabilities.py": "d741bddf8ef92fa3116bc5b33f24b9c9403c1b39b98c4c9701a8015cd02de78d", + "scripts/make_flash_image.py": "7944308a95cf3c99b42203496a95ebd269a929aff1f6b3bdccb9efa7383bce23", + "scripts/prepare_flash_boot.py": "75ff16be3f820dc2e9e167132d0ca4f20e67ca359a95398413e80430eebf2101", + "scripts/prepare_fpga_memories.py": "9d40763492ebbf2bc5aa183e760ec349e31765a0e999af88f476d5e945ab74c4", + "scripts/prepare_sources.py": "eb3637a141d4ef30659eb8086d1d59ec159c710ee81d9f8e64fc38b811632799", + "scripts/remote_linux_gemmini.py": "2221acd85bc1876d7730f15bb01f0b50629c2a9b9645b4d12cb74e566cf1e686", + "scripts/resolve_config.py": "1c4fb7d8533e659c7f8cb9e0ef5eb93f06d29a51d6b3e2449efe648f8f74000d", + "scripts/run_board_regression.py": "7302be4d5517eb315eb37b3ff8972bf17e2fe42990ae1fb6702c43c632515bfd", + "scripts/start_board_build.py": "04c5a521bcd7014774e6b476e8395bde134de9096bb22e6d6b6f200bf4311c83", + "scripts/verify_flash_evidence.py": "6db7b0dcc7323ba07ec6f17d0a09f04b321f8bdd24582ca49184dd654c1ebd45", + "scripts/verify_hardware_evidence.py": "60f3555a6b6ac6a9f567cf1b22caca9755bd4179dcea1f6731a70f8bd26a1202", + "scripts/verify_linux_gemmini.py": "1413703dfa42a6be6ac60e0df6bf3eb95ce8b50671a3a803c7421302eace7b2b", + "scripts/verify_linux_gemmini_archive.py": "cf8ab6737b2ad3525cf91e528aab64d78261146dec7473596d321812f3bad5e0", + "scripts/verify_target.py": "39bdd529e55f2b36bed4ba6b10a4b0a400fcb685f6f3e5886d537e8c549932cd", + "software/GEMMINI_LINUX.md": "31d991de14e315a1cf8ca24f5d3715a25a13d8601c8334687730a5b47959a963", + "software/MODEL_COMPATIBILITY.md": "1e3a78574d019f4a3e1442b899cc654f2c5a3e41cf55a7650610eed75618a1cf", + "software/build.sh": "908b5678edf5a710187480974c0c699ca8833faede20d044b7131060c3161292", + "software/build_gemmini_image.py": "949a59cbc4bd494cbe793b392aaccc237637c809667b6bd5dd211e2176e6fcbf", + "software/gemmini_linux_check.c": "2fa2f6d73d674d89344ffd058f28712380c2de04d64a88b43fe141e30e9df467", + "software/linux_system_check.c": "c1cedf2ce6e2583393c9e7f51fe20558c1402b8d81faf2152e8f6eeaf8058315", + "software/prepare_dependencies.py": "5bf2eca25081e014ff0de67ae0aeb41cb4380a2767a08a109a3bf6c19238b308", + "software/prepare_gemmini_linux.py": "358cee302a2a8ee6672cbf4c830776a6047dc33793a272a89f7343729ca0b3ec", + "software/prepare_platform.py": "f053463897045e1929d65aa9614b7b871c1c6c342f1f15865793883c858f3d61", + "src/main/scala/EmitFmaChecks.scala": "1d6eef40cefb36aaf0ce73838f2954cd89d09ad8c97244a2ac346da7137dccfd", + "src/main/scala/EmitGlobalRobCheck.scala": "5d366fce3e96278f60c648dc114896246b5c595c8ef783986524e6583c490a05", + "src/main/scala/EmitGroupQueryCheck.scala": "ae3a7bb5a7d951109596bc3e481a9a275e14f04a7cf6ec28084d50f354122ee1", + "src/main/scala/EmitPeChecks.scala": "38a88a8a59dcbdf1b4bf3b833679800c5e8505c18782f13719a7e7ec11fd100e", + "src/main/scala/EmitRoundShiftChecks.scala": "964a7631e50fe9a7a6024fbcb3c4ae857ea49a6c77435ab1ec269e510a0af7b0", + "src/main/scala/EmitRoutingCheck.scala": "fa40ecc7be03688ec66526742082ec6aba969b2e45f9881dbff4dfb218f4ac84", + "src/main/scala/EmitSubRobCheck.scala": "297d54bfd3fd5901f2ac584e4ae0c34edd18c38be4260e0700bb03bf20d2a6b3", + "src/main/scala/ReferencePE.scala": "6afff2af2a328fc38fa28c8c20c62906a49e55753422b96edf9515241cec7f6c", + "src/main/scala/ToyLinuxChip.scala": "d2c1bc12c9896f240ffb054f6d656076b0c367258fdd0764d58389de51c909e5", + "src/main/scala/ToyLinuxConfig.scala": "6e4afd1fc5705996b7995faa5d94867ae80102f7ecf28a1ab8b0dbc1b4d44c14", + "tests/REFERENCE_MANIFEST.json": "de4c11a8bca5bf8bb0fba0eada731177772756f307abd5523bbe5d60ffe3ff25", + "tests/axi_smoke_memory.sv": "7d0d410549217e73d319b807488812da06d54404a50fce484e1b527ea0e6632d", + "tests/board_loader_template.sv": "34be31c066ec317d5a1053d6e840145eb0af78766707915294a01cb96ec9b766", + "tests/check_cpu_smoke.py": "4e4ddc8df87550ebef7d0faa333833753d78b1409b01b64401de4ae600ecf00c", + "tests/check_dma_beat64.py": "c3f706adcf0bb8683825404b5342d56ac9587941678224106bb9c3d9289a01a2", + "tests/check_fpga_memories.py": "23d30b55b8aa909c6b4cda56a7e40d6c0be9e7d9bbd06f5ef8e8abf33400df76", + "tests/check_fpu_shared.py": "4c4cda836f3763e7cd8858edaea06ee2bf6db66471d246078015839b815ba9c4", + "tests/check_gemmini.py": "b34856c40f30e20efe1ba430555b10d6be4000b77d824751b92aa83af798cb71", + "tests/check_loop_stress.py": "c803fa7003da1895f49fc0ab6c4f1cefe20c9a419820927763fc0c685b9c0b2b", + "tests/check_pe.py": "47d167270b7890c1545bb7e6d325e8dd2d01b2b2821ddfba8064586518cd17d0", + "tests/check_routing.py": "1daeed7b9cc5d64bc4705f29c97eb134fd73c8940c7a6dfe0a90926fc04111c9", + "tests/check_ws_round.py": "56742cb9744b13528dadaf938ed59132f1c82e51d3cafeb34043d1518aea1128", + "tests/check_ws_shift_edges.py": "14655c70b72be241242c9a33495b5ec2a475724b2c88b5e4a65078560654d7e0", + "tests/cpu_smoke.S": "0e65a6c334d849e19668ada71f8a43b01a849523cd126e51c213078f77a5fa9f", + "tests/cpu_smoke.ld": "5c8f545686abe877ec8cfd9b6a2ed6e06c284b800e2c95937bc588a92a53568f", + "tests/dma_beat64.c": "ff3654f024836d346ffbb65a4c431a7e1dbf594b9e00e87443ca1f8583832d4d", + "tests/fma_differential.cpp": "790313bbd9110230d78d11d4fd81dcb1c1b40aa2ab703faccc2788a414482168", + "tests/gemmini_runtime.c": "1cf5e2ab3ca95a1941ba1e6db73fa81d2d21a7d7dd33dd0871fde6509661554f", + "tests/gemmini_start.S": "f583cf6a4822511546b8eef0221ccca6b91e92025d663a247a8548d4b6230c32", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/00_fence.c": "465a066c9f4b4dc7f75a8981983ea98ea29ca9838afc179f385dbfa569e45fb8", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/01_barrier.c": "5e3e8ac07f8a18eb771696e668e64754ce0dc5603a997dade467b26d8298b139", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/16_mvout.c": "d2dddcf237327aa65828ebf713466727544d08e41f93f0471fc3813169136e41", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/32_mset.c": "84c0ddded8d13f38a27613b019255a83638da85f31fddb36f5934b108c37499e", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/33_mvin.c": "713fdc01623938acefe64899e1b4a1f1c712bbb1fc48241d5a4392ff6e44e5fe", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/34_mvin_2d.c": "c79c07850fec290219221eebd6f5689ec0ad6ccd9c9ee29122ebb10a42d9ada7", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/35_mvin_mmio.c": "3729c4e3e5997594d8c8498eb90243327a508a6b1ddcf8484c69706d5a105f10", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/bb_func7.h": "f331dee3ce71c92b0934e80bb43b389dd041a39906ae149e848f1a66b057740c", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.c": "939f5e399bfc8d7b365624f1f9b70b30d6d3211908a06230bb2f268dba9b7773", + "tests/reference/bb-tests/workloads/lib/bbhw/isa/isa.h": "f23d3ee4440cb928645a4e3f1402ec94a3074b38f8f3f52836ab30486a9f6895", + "tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.c": "1ff9240196f37dbe2bc5af79d54508e718b5986ad69567ed74491133f19d5996", + "tests/reference/bb-tests/workloads/lib/bbhw/mem/mem.h": "57021a3076bb25a2a597c6f1f6ed147ab92acc7fca4768da87f96c2a22edb3ad", + "tests/reference/bb-tests/workloads/lib/buckyball.c": "c4c4b9fb107b89407c0654dab809885af7b855e985d7a6d2b80ea2d3d4394673", + "tests/reference/bb-tests/workloads/lib/buckyball.h": "c832025bdcbd13960537c317145623fe99eb15d333ad4645e3cd2aee0c493c50", + "tests/reference/examples/balls/gemmini/workloads/ctests/CMakeLists.txt": "724fd8f7733f25b39d46c142f777c588a603124a3f6484a04267a81242d0d11b", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_atranspose_test.c": "4a275b5e4a227d1a98270df7743428dbc423fe8a01f1daed621a59c9734e6246", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_basic_test.c": "c0050f3b79e787b35662daceb065e0d1f70f77136ac8f3d5413ad470423facc4", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_btranspose_test.c": "3027b5dd089b56ace3884f37d604035156a40f3054b21ae8fd8c3c861a98a4d2", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_cisc_shift_test.c": "b7b38aa6ea09431a6a47fa4d7959f7db40fc4b9fcd9551cbf3f52f4bdecd33e0", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_abtranspose_test.c": "a7f5f12fa7972b66f42a80d1d9311dea6fa5b1a659735c6100b32fae9d33484e", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_atranspose_test.c": "28ed257342db8009a4b38a022da5a532e477a10e6c8dcfdff1dd05070dfaedbf", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_basic_test.c": "7aa2d5a79425697cff9731fd3ce122572c72e844fab636a32e20f44cbd485f07", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_btranspose_test.c": "eb3c6f237d1de012bb48e61d516d1f1d91af28217a29e30da084eeb54e7612c2", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_os_risc_shift_test.c": "9900168f5dcbecba4768e28ed390fef9ec80e592147942f3c21af6b964d3a51e", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_cisc_conv_test.c": "2c277ac5740e7cc28198ba3b213fb29bbb1af4c7cfe114c23f30240955b026f7", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_basic_test.c": "c34824e7d4fefbe98d1f8d606bdb14c042917e1603ebdfe4d98a7f8a31147158", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_btranspose_test.c": "3869bc9ce52591118fcfb6fe1ceab4f3a8a0fe496b12dbd2b84f20ac3fde0fbc", + "tests/reference/examples/balls/gemmini/workloads/ctests/gemmini_ws_risc_shift_test.c": "ba8cd9b3148f707c7a451dc016fff5d0bb6df3b7f05accd6a22c3202ea7bd663", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini.h": "28d76de0a7cea15ad56857dc0bf96e66931a004d43531d57415fef9180060794", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_accumulated.h": "884721bb02de7c8e5ad5df6ce64a55eb1877de69ce1b5b82ddeed32615f59e21", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_compute_preloaded.h": "bbab5fa3af8537b10dd9102008e4fac64553a6f265837aea7fa7ffa07d941fa3", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_config.h": "c02b851181bbba2e3c562714dade47ef9fd37d94671827df9fca2da99b429265", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_flush.h": "9e57eb61e455a3296e3177c2f56a50ee4b85467e17db925ec959e83e9d469822", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_conv_ws.h": "3111bf7ece22ff56a2a248c802dd5dc0cc5a7cb8323a427b916c2de98b306fe6", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_loop_ws.h": "19530b9162e59cce3deb707312c2cfe4ec885fa73b54cc79bf3e6f52d45a73e0", + "tests/reference/examples/balls/gemmini/workloads/isa/gemmini_preload.h": "a5ac4c839a9ec1c33e8a34a1ebc282c6470196b8c19d91a429df3afa24f4b85e", + "tests/serial_loop_stress.c": "7058ae7627cee616c69e42ecf905d6b1a57d23ea2aa66a20a8cfe6ee41166dc7", + "tests/spi_flash_model.sv": "904377bb59c15643203b991d8414493d2f4f593285ecad63dc01628cb41f28fc", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97", + "tests/tb_fpu_rf.sv": "6d2e61c50907fee0125a0be9acf35ff718fb8615554e6b5f064cfe1e88beaf25", + "tests/tb_globalrob.sv": "8ded6fc969a05ead874fd8771b86dadafe51f7ccec54fafd55a9d48a4e7361a6", + "tests/tb_group_query.sv": "3461eda9a029ef0259daff3d5f58f43894e20893dbc489a3e64c8eda83c3f921", + "tests/tb_round_shift.sv": "d6cad7539f59f5dcb5c572cfb983828e35665586be79fea55fdb7471f895ae4f", + "tests/tb_subrob.sv": "fdaa673650870895e823491e835f351372ec18a73cdd0a188107a956c3d336a4", + "tests/ws_round_edges.c": "4ba46cd06447f1c5d8fdbebf16cc3ef4780c1b0d0b74f4d8d2dc7598410d3d10", + "tests/ws_shift_edges.c": "9a3fa9f60a25e5f1d6f5922bbe1ec97c77ce98b573a38830b8d36542e1a7fd8f", + "scripts/prepare_rob_candidate.py": "321b4569d2638342a7c0002ba1db3eb72229c369397289a11ed49633b1f27823", + "scripts/start_rob_board_build.py": "0c99afafe707a51fba935a59076288a50b7179e01d330f8a1294c81ee1956cf9" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/MANIFEST.json new file mode 100644 index 0000000..7fad007 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/MANIFEST.json @@ -0,0 +1,95 @@ +{ + "files": { + "implementation/bus-skew.rpt": "a750a81d15159a1d57d0e73e3c78d9d27570fdc11099da2a60225cf744dd5f20", + "implementation/cdc.rpt": "135fb071ef679e297772e213428481193b604b70e122ae57df1b397c7a73c17f", + "implementation/check-timing.rpt": "a97227785473b88d223f328775f146737b4282ffaf5f51835b0b372205733bd3", + "implementation/clocks.rpt": "0e713fd3d6d35c3949547f7a21f3009e6540d3db40c70da83c80689ddeeb6181", + "implementation/console.log": "cc9e8209337460ff1cc5fc9bb7db8e07030a9dc63b9853b7fbb11e597b4bab2a", + "implementation/drc.rpt": "e0c062aa6e13a01a4feed37ea85bff0a8f6ae05ca266d77967bcf432e2195769", + "implementation/io.rpt": "ee1accd10f5e79dd52619cf97f94d34c3d0bfc65c9689e5a6212cc9f0bc89b8e", + "implementation/ip-status.rpt": "b6857949e988e7407d0aebf28e68a53e94248a26fc0f5f87fa2395e047a86d97", + "implementation/launcher.log": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", + "implementation/methodology.rpt": "b1f11140bdc20a7b25a7691b462411020d7528d9dd0dae02ff7e7d5715f9274e", + "implementation/opt-utilization.rpt": "e503a8dbd9140caf4e8ece6e2bba6b4547c70e20de86e05e2bd25f0f229b0d83", + "implementation/phase.txt": "a4bccf5c13ef5ff8311e59b34d492bc7072a55298723601a6a9c127053aee8fc", + "implementation/route-status.rpt": "940f9a8a05963ffdc7ffc304e6f4226be99a07b3f5a83199d5bcd6e289897742", + "implementation/routed-hierarchy.rpt": "86bbcd4a653265301c3212a26d6980b20e628d2ffa98f43896874aaea3918187", + "implementation/routed-timing.rpt": "3c02fb09120654dba434c5b438117228bf2965953a5fb23f82d162736904bafe", + "implementation/routed-utilization.rpt": "c5e97613245378c1cf377f5d464b93354ec980376e6a63c272d379d96db1bf5e", + "implementation/RUN.json": "905863a76131fcac84f7164b461f03186497c61753565b08209a0872a722bcaa", + "implementation/synth-hierarchy.rpt": "33723226ef28dd33f17075726ada64f2e92771b5b05686fe150078e7dbb1f0a2", + "implementation/synth-timing.rpt": "d6a2cc3a07c5cdd384567081a903c79ba3bccdde3e875c2f189eea9437cd9bd7", + "implementation/synth-utilization.rpt": "d26984e3af4d6c3973f9230f72d683064e6df0d6ef0c486a245b94a605f1336a", + "implementation/vivado.jou": "3b780c0944a5a818873709d6700298ccdc5126def0d877da58fdb81caeebb04c", + "implementation/vivado.log": "ae9f34b1c0a0648e96b25088aa5336c2ecb269d12c5e0d002ed6ede00c23077c", + "INPUT_MANIFEST.json": "1185e957c6d0be808e34be4b209e92252c81ebfc75ec048426f830ba6a29ae10", + "MEMORY_MANIFEST.json": "35a43d93e5bde0cd6b0379dc2755497d660e179a5ed190cec3de259e427226b4", + "OPTIN_RESULT.json": "bdb1d489c2d4e7d7fa4757d104bbc155f504f75ab75be26f79005b546f0c8b9b", + "REPORT.md": "69e3e3cde262b0ac3b09099d062d9031962a88bfd568f0ec3518eeb265dde034", + "RESULT.json": "c415cbbe90ff1ae4bd699c8312453847f025e0ece0bdbdc0722650e972ca8b1d", + "ROB_RAM_PREPARED.json": "02297158d70b14e0c1fe9ea51f47b43391d0721bd6f2f0fffeb988c161a24347", + "sources/board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "sources/board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "sources/board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "sources/board/backup_flash.tcl": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "sources/board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "sources/board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "sources/board/flash_boot.xdc": "bbf9e250ae28dcc4f54d00effd918811f723a7563b4ceacb7b1d03a29151f4ea", + "sources/board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "sources/board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "sources/board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", + "sources/board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "sources/board/program_flash.tcl": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "sources/board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "sources/board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "sources/board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "sources/board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "sources/board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "sources/board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "sources/board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "sources/board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "sources/board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "sources/board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "sources/board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "sources/build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", + "sources/patches/framework/GlobalROB.scala": "dbfc0583355accfdd6a5287b06a78de07b8408705cec38a77d8544f6f108beb0", + "sources/scripts/bind_fpu_rf.py": "3551d10b12139d3ce87615f71c5750c65da385d278111852337c2b74c92ba889", + "sources/scripts/check_board_linux.py": "baf23e20a55cc5e3c74d663e9be6fb5f21134a5428445f4e688f97e3b0ed5647", + "sources/scripts/check_globalrob.py": "d9476b99ea8f68ea1b22fe62648433314c711fb40162349824f9fe89182517b4", + "sources/scripts/prepare_fpga_memories.py": "9d40763492ebbf2bc5aa183e760ec349e31765a0e999af88f476d5e945ab74c4", + "sources/scripts/prepare_rob_candidate.py": "321b4569d2638342a7c0002ba1db3eb72229c369397289a11ed49633b1f27823", + "sources/scripts/run_board_regression.py": "7302be4d5517eb315eb37b3ff8972bf17e2fe42990ae1fb6702c43c632515bfd", + "sources/scripts/start_board_build.py": "04c5a521bcd7014774e6b476e8395bde134de9096bb22e6d6b6f200bf4311c83", + "sources/scripts/start_rob_board_build.py": "0c99afafe707a51fba935a59076288a50b7179e01d330f8a1294c81ee1956cf9", + "sources/src/main/scala/EmitGlobalRobCheck.scala": "5d366fce3e96278f60c648dc114896246b5c595c8ef783986524e6583c490a05", + "sources/tests/tb_globalrob.sv": "8ded6fc969a05ead874fd8771b86dadafe51f7ccec54fafd55a9d48a4e7361a6", + "tests/board-unit/RESULT.json": "0936b6beacc5e2e7f9933a47b66d1d7a1406c600dbc276211e6ca231eb0034b6", + "tests/BOARD_REGRESSION.json": "8a2b20c212377c8fbf57cde884f0b66f4fc813ccd0b512ae7e09101d73708a05", + "tests/cpu/compile.log": "25f8949664f517263b62a194839d11709f27240cbfc2bbb7a57221961acce325", + "tests/cpu/RESULT.json": "9b046bb3db28ae6a5fd427ccf1a2790094be0afb1f772766b814968895b3195d", + "tests/cpu/simulation.log": "d97f1dfee2d17a4ffca8d4ee86efe040b8ffba08e0080057a43c1bfe082ddc5f", + "tests/dma/compile.log": "bfac229450f4bef3f236f4d1b19f9b2e67bc74dfe352e0fccad563ac68a12492", + "tests/dma/RESULT.json": "ec2727e85728f341b18775edfadddf00e2fef2b3a29b9797608f1487bef74375", + "tests/dma/simulation.log": "dd22077918a0b85716f625e14d2819aff818b93691b54d687322996ab64394f5", + "tests/gemmini/compile.log": "69bfeb5bcd843542e261bdb6b3fa72af49c8b59021c186cd9f1fb56fa5b3e84f", + "tests/gemmini/RESULT.json": "c4e6e44f8565b0f49b7acaa40f2b804b327aa7a6d0257ce2b8af8e13426a25f7", + "tests/gemmini/simulation.log": "03ef554f06f97740822c49ff114ebe8739c8748d09c7f4f08819c6fc88184f36", + "tests/globalrob/compile.log": "2dc0c38004c7fff3dfcaae5bd4e11ed5afd580380cf7cc3173b34d81be9f2724", + "tests/globalrob/elaboration.log": "ca0a55d7eba76adb6b64af774222976bf5c5c0b81bf43b7592625568813dd5ed", + "tests/globalrob/RESULT.json": "121502749440c24b3d8c51684fa4048aae8eafec2fb746fd47e894fceec31bd1", + "tests/globalrob/simulation.log": "e9a67784ab366ef90305cfccd16c9b10098b39bcc777c98e6aae62e4ac784a2d", + "tests/linux-final/compile.log": "44814c4eced3b014bf5aefc907cc54007272a0cbdbf1cc889f35d9d3d688055e", + "tests/linux-final/RESULT.json": "5322d8de3f9d8ecf7f09896ff2ce1e7a46d6f73a3279c59cce1bf84f80e3bf54", + "tests/linux-final/simulation.log": "cd018ca60b8dc30d71a2660cf0c95d6d56b99e5d4227b604765b57f6e068b83f", + "tests/loop/compile.log": "d1b8feed50e6b399cad22ae474f6dc1cba6661ecad9dfba39b34c8e5a686c02c", + "tests/loop/RESULT.json": "27079c6da7a232dbf2b242c0ca636f7bc8bae3dcbddee7994c844901d43db54e", + "tests/loop/simulation.log": "a59270b83489f8db4aaaaac305f5b02330deea8eeef2fbe3cb70b9660471a484", + "tests/rob-board-regression.log": "bb23554efb3b6ddb80e4b2c9e5eaf357e3d606e14de215149a78060065a6b0e0", + "tests/rob-core-binding.log": "8b81fb50e87a24078deb03fe215a59242ba82fffd39420062788d0c735f2793e", + "tests/rob-core-elaboration.log": "892792151faee44e8d609c2d69b5877b0ba4e33247b8adbdd63124b97e285766", + "tests/rob-memory-regression.log": "20000b4d1b563dde9bceeedb097d5370003a4ffe618ded9ace2e77623caf4071", + "tests/rob-optin-candidate.log": "37ef56b723b73f2abbf93cf9158048e1170c070dfb9786a51b276098a012d3a4", + "tests/rob-optin-default.log": "a6357910977360b5ac6aeaa3cd3c93506e2cf1da42bb072fdd73cb58a8cd5d84", + "ToyLinuxChip.profile.json": "57e251b00a486f406e5e27f666f4416be730b4e08c8838584e4aac49ebb30f86" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/MEMORY_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/MEMORY_MANIFEST.json new file mode 100644 index 0000000..649b3e8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/MEMORY_MANIFEST.json @@ -0,0 +1,140 @@ +{ + "emitted_sha256": "dc7d0cd8ab3d819b1a72b54d624a8462f21c02708983bc7d45457c8d382a228f", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "read_latency": 1, + "write_latency": 1, + "undefined_output_policy": "hold on disabled/write cycle", + "dual_port_collision_policy": "read/write same address is undefined", + "memories": [ + { + "module_name": "tag_array_ext", + "depth": 32, + "width": 92, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 23, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.meta.tag_array.tag_array_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "array_0_0_ext", + "depth": 128, + "width": 128, + "masked": true, + "read": 1, + "write": 1, + "readwrite": 0, + "mask_granularity": 64, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_2_1.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_2_0.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_0_1.array_0_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.dcache.data.array_0_0.array_0_0_ext" + ], + "ram_style": "block" + }, + { + "module_name": "bbtile_icache_tag_array_ext", + "depth": 64, + "width": 42, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 21, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_tag_array.bbtile_icache_tag_array_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "bbtile_icache_data_arrays_0_ext", + "depth": 256, + "width": 64, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 32, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_3.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_2.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_1.bbtile_icache_data_arrays_0_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.frontend.icache.bbtile_icache_data_arrays_0.bbtile_icache_data_arrays_0_ext" + ], + "ram_style": "block" + }, + { + "module_name": "robOperands_ext", + "depth": 16, + "width": 128, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.rob.robOperands.robOperands_ext" + ], + "ram_style": "block" + }, + { + "module_name": "sram_ext", + "depth": 8, + "width": 1269, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.subRob.sram.sram_ext" + ], + "ram_style": "distributed" + }, + { + "module_name": "mem_ext", + "depth": 1024, + "width": 64, + "masked": true, + "read": 0, + "write": 0, + "readwrite": 1, + "mask_granularity": 8, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_7.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_6.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_5.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_4.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_3.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_2.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_1.mem.mem_ext", + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.memDomain.backend.privateBackend.banks_0.mem.mem_ext" + ], + "ram_style": "block" + } + ], + "baseline_core_rtl_sha256": "03155e51ef07fec698c4c75f459478d065ed41fb324f00109d18a7426f330c05", + "additional_memory_adapters": [ + { + "module": "regfile_32x65", + "implementation": "two single-write LUTRAM banks and LVT", + "read_ports": 3, + "write_ports": 2, + "read_latency": 0, + "same_address_write_priority": "W1", + "added_cycles": 0, + "adapter_sha256": "bbc9ad168c94204a946b3e107115fae7f6042fd6c7f95807d7af367449e28950" + } + ] +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/OPTIN_RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/OPTIN_RESULT.json new file mode 100644 index 0000000..7a58cff --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/OPTIN_RESULT.json @@ -0,0 +1,14 @@ +{ + "rob-default-raw": { + "emitted_sha256": "05d53ac2a64ae89cfdb2861b3652b0e5b9a5bea401757c29a35f9a0654a3a2eb", + "core_rtl_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "memory_rtl_sha256": "8307d252185ba71a4516d1932d235a5a188816f84a5ed237bb5f3c1281d4b580" + }, + "rob-optin-raw": { + "emitted_sha256": "9cf090b2ecdf1f59115c5f639151ef9c0037cf2531a619d3dab349f937ec5097", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" + }, + "result": "PASS_DEFAULT_AND_CANDIDATE_BYTE_IDENTITY", + "source_switch": "sbt -Dfpga.robOperandRam=true" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/REPORT.md b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/REPORT.md new file mode 100644 index 0000000..1d7531c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/REPORT.md @@ -0,0 +1,73 @@ +# ROB 操作数 RAM 优化报告 + +本轮通过了 RTL 回归、Linux 启动与完整 FPGA 布线，尚未烧录实板。 +不减少架构功能或容量，不替换已有 UART/Flash 发布包。 + +## 改动与范围 + +从固定上游 `GlobalROB.scala` 增加可选路径：两份 64 位操作数在 allocation +写入 16×128、1R1W 同步 RAM，利用原 issue pointer 级隐藏读延迟。 +控制、依赖、提交顺序与 trace 保留；原指针、背压和有效位控制 RAM 使用。 +显式 BRAM 绑定消除了大量操作数 FF，代价是两块 RAMB36。 + +保留当前 FPGA profile 的 CPU、Sv39、FP16/32/64、Gemmini 8×8、23 项 Ball +指令、16-entry ROB、bank/缓存容量及板级接口。它不会恢复此前已裁剪的独立 Ball。 +这项内部存储优化不改变软件 ABI，也不代表整模型编译链已适配。 + +## 同条件面积与时序 + +器件 `xc7a100tcsg324-1`，Vivado 2024.1，UART 目标、25 MHz CPU； +沿用原 `board/build_board.tcl`、XDC 和综合/布局策略。基线为 +`evidence/2026-10-11/BOARD_RESULT.json`，没有用 Flash 目标作比较。 + +| 布线后测量 | 原寄存器 | 同步 RAM | 变化 | +|---|---:|---:|---:| +| 物理 LUT（已计入 LUT combining） | 54,413 | 53,929 | −484 | +| FF | 35,600 | 33,943 | −1,657 | +| 占用 Slice / 15,850 | 15,663 | 15,579 | −84 | +| 空闲 Slice | 187 | 271 | +84 | +| BRAM tile / 135 | 29 | 31 | +2 | +| DSP / 240 | 117 | 117 | 0 | +| WNS / WHS（ns） | +1.276 / +0.013 | +1.276 / +0.012 | 均通过 | + +候选 TNS、THS 为 0，全部可布线网络完成、布线错误为 0，位流已生成。 +运行 1,396 秒，在 3,600 秒期限内完成。DRC 无 Error/Critical，仍有 360 项 +普通警告（主要为 DSP 输入/输出流水建议）；CDC 保留 3 项时钟转换 IP 的 +CDC-15 Warning，无 Critical。未降低 DRC 严重级别。 + +全部 64 个 PE 仍各使用一个 DSP。综合阶段减少 429 LUT、1,655 FF；最终以 +布线后资源为准。Slice 占用仍为 98.29%，这点余量不能证明能加入另一套算子硬件。 + +RAM 子层级被 Vivado 归入部分 `bankCols_*` 配置控制，不能把该层级下的约 +1,721 LUT 全部解释成 RAM 本体开销。并行提交/配置更新网络仍是后续候选，未在 +本轮修改；未测量的优化不计入上述收益。 + +## 功能与性能核验 + +- ROB RAM 与原寄存器路径逐周期对照通过，8,029 周期，三个随机种子与两次 + 中途复位；接受时保存完整命令作独立对照。断言覆盖满队列、背压及排空。 +- 七类 memory 通过原 RTL/独立 scoreboard 对照，包括新增 RAM；AXI、SCU、 + UART/CRC loader 接口检查通过。 +- 不改测试二进制，CPU/Sv39/FPU/AMO/cache/IRQ、原 13 项 Gemmini、OS/WS + 分块循环、非对齐/跨页 DMA 分别为 709,434、251,063、684,219、1,914,839 + 周期，与原基线完全相同。这是已测用例结论，不是所有负载性能的证明。 +- 同一标准 payload 启动 OpenSBI/Linux，通过写时复制、页面保护、浮点进程 + 上下文、定时器与总检查；273,506,752 周期与基线相同。页面保护用例故意 + 触发子进程 SIGSEGV，之后 `PASS VM_PAGE_PROTECTION` 为预期成功行为。 +- Linux 检查使用 AXI 存储模型，串口 RX 输入真实波形；未模拟物理 DDR PHY。 + +## 复现与文件 + +从平台目录按 [ROB_RAM.md](../../../ROB_RAM.md) 执行。默认构建保持旧路径， +候选需显式 `sbt -Dfpga.robOperandRam=true`。后续两种配置均重新生成，默认 +核心/存储器与旧发布摘要一致，候选与本次已测字节一致，见 `OPTIN_RESULT.json`。 + +`sources/` 保存本次实际执行的覆盖层、测试入口和板级 Tcl/XDC；其中构造默认 +为 true 是首次实验快照，当前集成改为显式开启，生成字节一致性已单独核验。 +`INPUT_MANIFEST.json` 记录隔离目录初始输入，`MANIFEST.json` 核验本档案。 +`tests/` 保存通过的回归原文，`implementation/` 保存完整资源、时序、DRC/CDC +和 Vivado 日志。无关网络/启动命令错误不作为芯片测试失败写入档案。 + +生成核心、存储器、位流摘要记录在 `RESULT.json`。大体积 RTL、DCP、位流保留 +在构建目录，未当作已验收发布件提交。当前只有 UART 候选；Flash 版本和实板 +验收仍需独立执行。原发布资格与本轮记录分开保留。 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/RESULT.json new file mode 100644 index 0000000..be1eac0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/RESULT.json @@ -0,0 +1,51 @@ +{ + "result": "PASS_ROB_RAM_RTL_AND_BOARD_IMPLEMENTATION", + "part": "xc7a100tcsg324-1", + "mode": "UART", + "core_clock_hz": 25000000, + "baseline_record": "evidence/2026-10-11/BOARD_RESULT.json", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "bitstream_sha256": "dec8dcaea14b56db49ef8166d1605034695658f55f02dce73d4455fbc078ee5c", + "routed_resources": { + "LUT": 53929, + "FF": 33943, + "Slice": 15579, + "BRAM_tiles": 31, + "DSP": 117 + }, + "resource_delta": { + "LUT": -484, + "FF": -1657, + "Slice": -84, + "BRAM_tiles": 2, + "DSP": 0 + }, + "free_slices": 271, + "gemmini_mesh_dsp": 64, + "timing": { + "wns_ns": 1.276, + "whs_ns": 0.012, + "tns_ns": 0, + "ths_ns": 0, + "wpws_ns": 0.187 + }, + "route_errors": 0, + "architectural_profile_unchanged": true, + "regression_cycles_unchanged": true, + "linux_rtl_cycles": 273506752, + "physical_board_tested": false, + "flash_boot_tested": false, + "replaces_published_artifacts": false, + "integration_sources": { + "build.sbt": "c4581ef9345fb3d3bd326c95b6f46a0ae8538ed6c0cc22ac675bd0c9a10fd407", + "patches/framework/GlobalROB.scala": "7998e486ffa0f6e4f1cdb3ee991ed5a7c8d389268da94e4fbbc9a9bd56573c7d", + "scripts/check_globalrob.py": "d9476b99ea8f68ea1b22fe62648433314c711fb40162349824f9fe89182517b4", + "scripts/prepare_fpga_memories.py": "9d40763492ebbf2bc5aa183e760ec349e31765a0e999af88f476d5e945ab74c4", + "scripts/prepare_rob_candidate.py": "321b4569d2638342a7c0002ba1db3eb72229c369397289a11ed49633b1f27823", + "scripts/start_rob_board_build.py": "0c99afafe707a51fba935a59076288a50b7179e01d330f8a1294c81ee1956cf9", + "scripts/elaborate_rob_candidate.sh": "ce65656a3ae6c9fd49d651b9cef434cf8cf3bcfb393180d210f233741c6ffa0f", + "src/main/scala/EmitGlobalRobCheck.scala": "5d366fce3e96278f60c648dc114896246b5c595c8ef783986524e6583c490a05", + "tests/tb_globalrob.sv": "8ded6fc969a05ead874fd8771b86dadafe51f7ccec54fafd55a9d48a4e7361a6" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ROB_RAM_PREPARED.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ROB_RAM_PREPARED.json new file mode 100644 index 0000000..a49e085 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ROB_RAM_PREPARED.json @@ -0,0 +1,21 @@ +{ + "result": "PREPARED_NOT_VALIDATED", + "architectural_profile_unchanged": true, + "existing_memory_geometry_unchanged": true, + "rob_operand_memory": { + "module_name": "robOperands_ext", + "depth": 16, + "width": 128, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.rob.robOperands.robOperands_ext" + ] + }, + "rob_operand_ram_style": "block", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ToyLinuxChip.profile.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ToyLinuxChip.profile.json new file mode 100644 index 0000000..8207768 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/ToyLinuxChip.profile.json @@ -0,0 +1,73 @@ +{ + "serial_fpga": true, + "gemmini_only_balls": true, + "ball_count": 1, + "ball_names": [ + "GemminiBall" + ], + "ball_ids": [ + 0 + ], + "ball_funct7": [ + 2, + 3, + 53, + 66, + 67, + 80, + 81, + 82, + 83, + 84, + 85, + 86, + 87, + 96, + 97, + 98, + 99, + 100, + 101, + 102, + 103, + 104, + 105 + ], + "ball_read_ports": 2, + "ball_write_ports": 4, + "accelerator_mmio_scale_pool": false, + "compact_caches": true, + "btb_enabled": false, + "icache_bytes": 8192, + "icache_ways": 2, + "dcache_bytes": 8192, + "dcache_mshrs": 1, + "l2_ways": 0, + "coherence_manager": "broadcast", + "rob_entries": 16, + "sub_rob_depth": 8, + "dma_n_xacts": 2, + "dma_max_in_flight": 4, + "tma_read_channels": 1, + "tma_write_channels": 1, + "cpu_mul_unroll": 8, + "gemmini_rows": 8, + "gemmini_columns": 8, + "virtual_bank_count": 16, + "trimmed_optional_peripherals": true, + "scratchpad_bytes": 0, + "cpu_use_debug": false, + "cpu_breakpoints": 0, + "extra_hpm_counters": 0, + "basic_counters": true, + "use_vm": true, + "fpu_shared_fma": true, + "fpu_sfma_latency": 6, + "fpu_dfma_latency": 6, + "fpu_min_flen": 16, + "fpu_flen": 64, + "bank_count": 8, + "bank_rows": 1024, + "bank_width": 64, + "bank_channels": 7 +} \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/RUN.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/RUN.json new file mode 100644 index 0000000..aafc26b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/RUN.json @@ -0,0 +1,71 @@ +{ + "status": "COMPLETED", + "optimization": "ROB_OPERAND_BRAM", + "timeout_seconds": 3600, + "termination_grace_seconds": 15, + "part": "xc7a100tcsg324-1", + "core_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054", + "board_sources": { + "board/make_flash_image.tcl": "69a70d18a519f8fa156981e9ab024dce5c7bc91733c5b6cf3b9045658415334b", + "board/SOURCE_MANIFEST.json": "03d99f1f43bbf68d92df61db52bdee0019723e2e194ee5f9c12a5ac6d4c5a105", + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/README.md": "5a7f01460107df0c5c40d2a2b18c68648ca2d7b20c914c788b880ec1b9f6f95b", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/program_arty.tcl": "fbb62bafb6df602b0f5f638fb05ae4ecc90494ac162b9a5f5ac314200f7a241c", + "board/arty_a7.xdc": "f13869ba386038557084adabafeb5255943d0b67f1db4b88fd907e4f095d016f", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/backup_flash.tcl": "63d84e9055f00bd7ed97485912b0c8db83bee19b6950ba4c12fc3f9a639c3ea3", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/program_flash.tcl": "a2cfa55d7f61f5cecd74e68e2bbede9c535399291eea274e76fe416bdc8d3626", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/build_board.tcl": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/flash_boot.xdc": "bbf9e250ae28dcc4f54d00effd918811f723a7563b4ceacb7b1d03a29151f4ea", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "board/vendor/License.txt": "28a42137bb9c77a6aa931c5ca670134620f448051dbd708a05921280a7b277ba", + "board/vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "board/vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce", + "board/vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "board/vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "board/vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85" + }, + "execution_script": "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl", + "execution_script_sha256": "04f25ca8f6da06b37aec7156ec47def13da0bac88294466b08fb838bc462ba8d", + "core_clock_hz": 25000000, + "uart_baud": 1000000, + "architectural_profile_unchanged": true, + "flash_boot": false, + "physical_boot_tested": false, + "inherits_baseline_hardware_qualification": false, + "started_at": "2026-10-12T20:13:52.282668+08:00", + "deadline": "2026-10-12T21:13:52.282668+08:00", + "command": [ + "timeout", + "--signal=TERM", + "--kill-after=15s", + "3600s", + "/home/yys/bin/vivado", + "-mode", + "batch", + "-source", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl", + "-log", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log", + "-journal", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou", + "-tclargs", + "/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352" + ], + "worker_pid": 19876, + "timeout_process_pid": 19881, + "exit_code": 0, + "elapsed_seconds": 1396.3394632509999, + "finished_at": "2026-10-12T20:37:08.622201+08:00", + "core_unchanged": false, + "bitstream_generated": true, + "candidate_core_unchanged": true, + "candidate_memory_unchanged": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/bus-skew.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/bus-skew.rpt new file mode 100644 index 0000000..cfa9204 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/bus-skew.rpt @@ -0,0 +1,1380 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:27 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_bus_skew -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +Table of Contents +----------------- +1. Bus Skew Report Summary +2. Bus Skew Report Per Constraint + +1. Bus Skew Report Summary +-------------------------- + +Id Position From To Corner Requirement(ns) Actual(ns) Slack(ns) +-- -------- ------------------------------ ------------------------------ ------ --------------- ---------- --------- +1 31 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.873 11.127 +2 33 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.653 11.347 +3 35 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.929 11.071 +4 37 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.779 11.221 +5 39 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.489 11.511 +6 41 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.698 11.302 +7 43 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 1.078 10.922 +8 45 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.985 11.015 +9 47 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.763 11.237 +10 49 [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] + [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] + Slow 12.000 0.781 11.219 + + +2. Bus Skew Report Per Constraint +--------------------------------- + +Id: 1 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.873 11.127 + + +Slack (MET) : 11.127ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.562ns + Reference Relative Delay: -1.878ns + Relative CRPR: 0.444ns + Actual Bus Skew: 0.873ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X53Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 -0.508 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.747 0.239 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X49Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.498 0.671 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X49Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.066 + SLICE_X49Y78 FDRE (Setup_fdre_C_D) -0.265 0.801 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 0.239 + clock arrival 0.801 + ------------------------------------------------------------------- + relative delay -0.562 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.489 -1.531 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X55Y76 FDRE (Prop_fdre_C_Q) 0.367 -1.164 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.489 -0.675 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.606 1.428 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.033 + SLICE_X57Y76 FDRE (Hold_fdre_C_D) 0.170 1.203 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.675 + clock arrival 1.203 + ------------------------------------------------------------------- + relative delay -1.878 + + + +Id: 2 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.653 11.347 + + +Slack (MET) : 11.347ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.897ns + Reference Relative Delay: -2.108ns + Relative CRPR: 0.558ns + Actual Bus Skew: 0.653ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.633 -0.907 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.456 -0.451 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.535 0.085 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.509 0.682 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 1.077 + SLICE_X69Y94 FDRE (Setup_fdre_C_D) -0.095 0.982 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 0.085 + clock arrival 0.982 + ------------------------------------------------------------------- + relative delay -0.897 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.367 -1.141 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.260 -0.882 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.630 1.452 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.057 + SLICE_X68Y92 FDRE (Hold_fdre_C_D) 0.169 1.226 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.882 + clock arrival 1.226 + ------------------------------------------------------------------- + relative delay -2.108 + + + +Id: 3 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.929 11.071 + + +Slack (MET) : 11.071ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.868ns + Reference Relative Delay: 2.440ns + Relative CRPR: 0.499ns + Actual Bus Skew: 0.929ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.630 1.452 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X67Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y92 FDRE (Prop_fdre_C_Q) 0.456 1.908 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.752 2.660 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X64Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X64Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.113 + SLICE_X64Y93 FDRE (Setup_fdre_C_D) -0.095 -1.208 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.660 + clock arrival -1.208 + ------------------------------------------------------------------- + relative delay 3.868 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.508 0.681 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X68Y92 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y92 FDRE (Prop_fdre_C_Q) 0.367 1.048 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.260 1.307 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.633 -0.907 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 -1.302 + SLICE_X68Y94 FDRE (Hold_fdre_C_D) 0.169 -1.133 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 1.307 + clock arrival -1.133 + ------------------------------------------------------------------- + relative delay 2.440 + + + +Id: 4 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.779 11.221 + + +Slack (MET) : 11.221ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.747ns + Reference Relative Delay: -2.080ns + Relative CRPR: 0.554ns + Actual Bus Skew: 0.779ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.714 -0.826 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y109 FDRE (Prop_fdre_C_Q) 0.419 -0.407 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.607 0.199 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X88Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.597 0.769 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X88Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism 0.395 1.164 + SLICE_X88Y109 FDRE (Setup_fdre_C_D) -0.218 0.946 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 0.199 + clock arrival 0.946 + ------------------------------------------------------------------- + relative delay -0.747 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.594 -1.427 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X87Y109 FDRE (Prop_fdre_C_Q) 0.367 -1.060 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.293 -0.767 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X86Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.716 1.538 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X86Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 1.143 + SLICE_X86Y109 FDRE (Hold_fdre_C_D) 0.170 1.313 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival -0.767 + clock arrival 1.313 + ------------------------------------------------------------------- + relative delay -2.080 + + + +Id: 5 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 0.489 11.511 + + +Slack (MET) : 11.511ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.567ns + Reference Relative Delay: 2.548ns + Relative CRPR: 0.529ns + Actual Bus Skew: 0.489ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.717 1.539 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X89Y108 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y108 FDRE (Prop_fdre_C_Q) 0.456 1.995 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.445 2.440 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.594 -1.427 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X87Y109 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.032 + SLICE_X87Y109 FDRE (Setup_fdre_C_D) -0.095 -1.127 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.440 + clock arrival -1.127 + ------------------------------------------------------------------- + relative delay 3.567 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X89Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X89Y114 FDRE (Prop_fdre_C_Q) 0.367 1.133 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.360 1.493 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X87Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.711 -0.829 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X87Y114 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 -1.224 + SLICE_X87Y114 FDRE (Hold_fdre_C_D) 0.169 -1.055 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival 1.493 + clock arrival -1.055 + ------------------------------------------------------------------- + relative delay 2.548 + + + +Id: 6 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.698 11.302 + + +Slack (MET) : 11.302ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.743ns + Reference Relative Delay: 2.489ns + Relative CRPR: 0.556ns + Actual Bus Skew: 0.698ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.715 1.537 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X76Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y94 FDRE (Prop_fdre_C_Q) 0.478 2.015 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.432 2.448 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.597 -1.423 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.028 + SLICE_X75Y94 FDRE (Setup_fdre_C_D) -0.267 -1.295 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.448 + clock arrival -1.295 + ------------------------------------------------------------------- + relative delay 3.743 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.767 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X76Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y94 FDRE (Prop_fdre_C_Q) 0.418 1.185 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.255 1.440 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X77Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.717 -0.823 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X77Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.218 + SLICE_X77Y93 FDRE (Hold_fdre_C_D) 0.169 -1.049 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.440 + clock arrival -1.049 + ------------------------------------------------------------------- + relative delay 2.489 + + + +Id: 7 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Slow 1.078 10.922 + + +Slack (MET) : 10.922ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.584ns + Reference Relative Delay: -2.177ns + Relative CRPR: 0.515ns + Actual Bus Skew: 1.078ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.717 -0.823 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X76Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X76Y93 FDRE (Prop_fdre_C_Q) 0.518 -0.305 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.813 0.509 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X73Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.592 0.765 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X73Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism 0.395 1.160 + SLICE_X73Y93 FDRE (Setup_fdre_C_D) -0.067 1.093 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 0.509 + clock arrival 1.093 + ------------------------------------------------------------------- + relative delay -0.584 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.597 -1.423 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X75Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y94 FDRE (Prop_fdre_C_Q) 0.367 -1.056 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.254 -0.802 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X74Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.715 1.537 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X74Y93 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C + clock pessimism -0.395 1.142 + SLICE_X74Y93 FDRE (Hold_fdre_C_D) 0.233 1.375 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + ------------------------------------------------------------------- + data arrival -0.802 + clock arrival 1.375 + ------------------------------------------------------------------- + relative delay -2.177 + + + +Id: 8 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +core_raw clk_pll_i memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 0.985 11.015 + + +Slack (MET) : 11.015ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: -0.551ns + Reference Relative Delay: -2.003ns + Relative CRPR: 0.468ns + Actual Bus Skew: 0.985ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X53Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 -0.508 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.746 0.238 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.499 0.672 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 1.067 + SLICE_X48Y80 FDRE (Setup_fdre_C_D) -0.278 0.789 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 0.238 + clock arrival 0.789 + ------------------------------------------------------------------- + relative delay -0.551 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.493 -1.527 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X53Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.367 -1.160 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.366 -0.794 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.612 1.434 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 1.039 + SLICE_X57Y80 FDRE (Hold_fdre_C_D) 0.170 1.209 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival -0.794 + clock arrival 1.209 + ------------------------------------------------------------------- + relative delay -2.003 + + + +Id: 9 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Slow 0.763 11.237 + + +Slack (MET) : 11.237ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.721ns + Reference Relative Delay: 2.442ns + Relative CRPR: 0.516ns + Actual Bus Skew: 0.763ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.612 1.434 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y80 FDRE (Prop_fdre_C_Q) 0.456 1.890 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.606 2.496 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.495 -1.525 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism 0.395 -1.130 + SLICE_X57Y81 FDRE (Setup_fdre_C_D) -0.095 -1.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 2.496 + clock arrival -1.225 + ------------------------------------------------------------------- + relative delay 3.721 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.660 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y76 FDRE (Prop_fdre_C_Q) 0.367 1.027 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.257 1.284 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.607 -0.933 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X55Y76 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C + clock pessimism -0.395 -1.328 + SLICE_X55Y76 FDRE (Hold_fdre_C_D) 0.169 -1.159 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + ------------------------------------------------------------------- + data arrival 1.284 + clock arrival -1.159 + ------------------------------------------------------------------- + relative delay 2.442 + + + +Id: 10 +set_bus_skew -from [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]}]] -to [get_cells [list {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]} {memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]}]] 12.000 +Requirement: 12.000ns +Endpoints: 4 + +From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns) +-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- --------- +clk_pll_i core_raw memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Slow 0.781 11.219 + + +Slack (MET) : 11.219ns (requirement - actual skew) + Endpoint Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Endpoint Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Reference Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i) + Reference Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw) + Path Type: Bus Skew (Max at Slow Process Corner) + Requirement: 12.000ns + Endpoint Relative Delay: 3.898ns + Reference Relative Delay: 2.579ns + Relative CRPR: 0.539ns + Actual Bus Skew: 0.781ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR) + +Endpoint path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X59Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.419 1.855 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.646 2.501 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.498 -1.522 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + clock pessimism 0.395 -1.127 + SLICE_X59Y79 FDRE (Setup_fdre_C_D) -0.270 -1.397 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + data arrival 2.501 + clock arrival -1.397 + ------------------------------------------------------------------- + relative delay 3.898 + +Reference path: + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.494 0.667 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X59Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.367 1.034 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.391 1.425 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X55Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.611 -0.929 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X55Y78 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C + clock pessimism -0.395 -1.324 + SLICE_X55Y78 FDRE (Hold_fdre_C_D) 0.170 -1.154 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + data arrival 1.425 + clock arrival -1.154 + ------------------------------------------------------------------- + relative delay 2.579 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/cdc.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/cdc.rpt new file mode 100644 index 0000000..0772732 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/cdc.rpt @@ -0,0 +1,93 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:23 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_cdc -details -return_string +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +CDC Report + +ID Severity Count Description +------ -------- ----- ------------------------------------------------------- +CDC-3 Info 17 1-bit synchronized with ASYNC_REG property +CDC-9 Info 10 Asynchronous reset synchronized with ASYNC_REG property +CDC-15 Warning 3 Clock enable controlled CDC structure detected + +Source Clock: core_raw +Destination Clock: clk_pll_i +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ------ -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 2 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 3 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 4 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 5 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 6 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_60_60/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[60]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 9 CDC-15 Warning Clock enable controlled CDC structure detected 0 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_144_144/DP/CLK memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[144]/D + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 12 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 13 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path reset_count_reg[9]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + +Source Clock: mem_refclk +Destination Clock: clk_pll_i +CDC Type: User Ignored + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 3 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + +Source Clock: clk_pll_i +Destination Clock: core_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------------------- ----- ---------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C calib_sync_reg[0]/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 3 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 4 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 5 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + 6 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 7 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 8 CDC-3 Info 1-bit synchronized with ASYNC_REG property 6 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_rd_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr/syncstages_ff_reg[0]/D + 9 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + 10 CDC-9 Info Asynchronous reset synchronized with ASYNC_REG property 2 False Path ui_reset_pipe_reg[2]/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + 11 CDC-3 Info 1-bit synchronized with ASYNC_REG property 7 False Path memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd/syncstages_ff_reg[0]/D + +Source Clock: input port clock +Destination Clock: core_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------------------- + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_meta_reg/D + 2 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path uart_txd_in platform/receiver/rx_meta_reg/D + +Source Clock: clk_pll_i +Destination Clock: ref_raw +CDC Type: Safely Timed + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ----------------------- ------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 Max Delay Datapath Only ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + +Source Clock: input port clock +Destination Clock: ref_raw +CDC Type: No Common Primary Clock + +Row ID Severity Description Depth Exception Source (From) Destination (To) +--- ----- -------- ------------------------------------------ ----- ---------- ------------- ------------------ + 1 CDC-3 Info 1-bit synchronized with ASYNC_REG property 2 False Path btn0 btn_ref_meta_reg/D + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/check-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/check-timing.rpt new file mode 100644 index 0000000..a2f2d10 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/check-timing.rpt @@ -0,0 +1,108 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:40 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : check_timing -verbose -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/check-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +---------------------------------------------------------------------------------------------------------------------------------------------------------- + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/clocks.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/clocks.rpt new file mode 100644 index 0000000..b5f4351 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/clocks.rpt @@ -0,0 +1,203 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:39 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_clocks -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/clocks.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Report + + +Attributes + P: Propagated + G: Generated + A: Auto-derived + R: Renamed + V: Virtual + I: Inverted + S: Pin phase-shifted with Latency mode + +Clock Period(ns) Waveform(ns) Attributes Sources +board_clk 10.000 {0.000 5.000} P {CLK100MHZ} +clk_pll_i 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} +core_raw 40.000 {0.000 20.000} P,G,A {clock_mmcm/CLKOUT0} +fb 10.000 {0.000 5.000} P,G,A {clock_mmcm/CLKFBOUT} +freq_refclk 1.500 {0.000 0.750} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} +iserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} +iserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} +mem_refclk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} +oserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} +oserdes_clk_1 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} +oserdes_clk_2 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} +oserdes_clk_3 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} +oserdes_clkdiv 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} +oserdes_clkdiv_1 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} +oserdes_clkdiv_2 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} +oserdes_clkdiv_3 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} +pll_clk3_out 12.000 {0.000 6.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} +pll_clkfbout 6.000 {0.000 3.000} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} +ref_raw 5.000 {0.000 2.500} P,G,A {clock_mmcm/CLKOUT2} +sync_pulse 48.000 {1.312 4.312} P,G,A {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} +sys_raw 6.000 {0.000 3.000} P,G,A {clock_mmcm/CLKOUT1} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} +u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 3.000 {0.000 1.500} P,G,A {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + +==================================================== +Generated Clocks +==================================================== + +Generated Clock : clk_pll_i +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Master Clock : pll_clk3_out +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT} + +Generated Clock : core_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 15.000 30.000} +Generated Sources : {clock_mmcm/CLKOUT0} + +Generated Clock : fb +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 1 +Generated Sources : {clock_mmcm/CLKFBOUT} + +Generated Clock : freq_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0} + +Generated Clock : iserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : iserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK +Master Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV} + +Generated Clock : mem_refclk +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1} + +Generated Clock : oserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK} + +Generated Clock : oserdes_clk_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK} + +Generated Clock : oserdes_clk_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK} + +Generated Clock : oserdes_clk_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/MEMREFCLK +Master Clock : mem_refclk +Divide By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK} + +Generated Clock : oserdes_clkdiv +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK +Master Clock : oserdes_clk +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_1 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK +Master Clock : oserdes_clk_1 +Divide By : 4 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_2 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK +Master Clock : oserdes_clk_2 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV} + +Generated Clock : oserdes_clkdiv_3 +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK +Master Clock : oserdes_clk_3 +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV} + +Generated Clock : pll_clk3_out +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 3.000 6.000} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3} + +Generated Clock : pll_clkfbout +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Multiply By : 1 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT} + +Generated Clock : ref_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Multiply By : 2 +Generated Sources : {clock_mmcm/CLKOUT2} + +Generated Clock : sync_pulse +Master Source : ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Master Clock : sys_raw +Edges : {1 2 3} +Edge Shifts(ns) : {1.312 1.313 43.312} +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2} + +Generated Clock : sys_raw +Master Source : clock_mmcm/CLKIN1 +Master Clock : board_clk +Edges : {1 2 3} +Edge Shifts(ns) : {0.000 -2.000 -4.000} +Generated Sources : {clock_mmcm/CLKOUT1} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK} + +Generated Clock : u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Master Source : ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/FREQREFCLK +Master Clock : freq_refclk +Divide By : 2 +Generated Sources : {ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK} + + + +==================================================== +User Uncertainty +==================================================== + + + +==================================================== +User Jitter +==================================================== + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/console.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/console.log new file mode 100644 index 0000000..87f2d59 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/console.log @@ -0,0 +1,5789 @@ + +****** Vivado v2024.1 (64-bit) + **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 + **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 + **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 + **** Start of session at: Mon Oct 12 20:13:53 2026 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl +# set root [file dirname [file dirname [file normalize [info script]]]] +# cd $root +# if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +# set flash 0 +# if {[llength $argv]==2} { +# if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} +# set flash 1 +# } +# set out [file normalize [lindex $argv 0]] +# file mkdir $out +# file mkdir $out/ip +# proc phase {name} { +# global out +# set f [open $out/phase.txt w];puts $f $name;close $f +# puts "BOARD_PHASE $name" +# } +# set_param general.maxThreads 8 +# phase CREATE_IP +BOARD_PHASE CREATE_IP +# create_project -in_memory -part xc7a100tcsg324-1 +# set_property target_language Verilog [current_project] +# create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +# set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +INFO: [IP_Flow 19-3484] Absolute path of file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/vendor/mig.prj' provided. It will be converted relative to IP Instance files '../../../../board/vendor/mig.prj' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. +# create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +# set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +# generate_target all [get_ips] +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'toy_axi_cdc'... +WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc' +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'toy_axi_cdc'... +generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2222.848 ; gain = 275.328 ; free physical = 491940 ; free virtual = 628327 +# report_ip_status -file $out/ip-status.rpt +# phase SYNTH_IP +BOARD_PHASE SYNTH_IP +# synth_ip [get_ips] +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top arty_ddr3 -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 20494 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2658.477 ; gain = 417.715 ; free physical = 491599 ; free virtual = 627992 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:253] +INFO: [Synth 8-11241] undeclared symbol 'dbg_sel_po_incdec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1223] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_inc', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1227] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_stg23_sel', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1228] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_dec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1229] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3.v:70] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3_mig' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:75] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] + Parameter TCQ bound to: 100 - type: integer + Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string + Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer + Parameter tTEMPSAMPLE bound to: 10000000 - type: integer +INFO: [Synth 8-6157] synthesizing module 'XADC' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] + Parameter INIT_40 bound to: 16'b0001000000000000 + Parameter INIT_41 bound to: 16'b0010111111111111 + Parameter INIT_42 bound to: 16'b0000100000000000 + Parameter INIT_48 bound to: 16'b0000000100000001 + Parameter INIT_49 bound to: 16'b0000000000000000 + Parameter INIT_4A bound to: 16'b0000000100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101011111100100 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1100101000110011 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101001011000110 + Parameter INIT_56 bound to: 16'b1001010101010101 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] + Parameter TCQ bound to: 100 - type: integer + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter REFCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYS_RST_PORT bound to: FALSE - type: string + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: FALSE - type: string +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter DIFF_TERM_SYSCLK bound to: TRUE - type: string +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] + Parameter TCQ bound to: 100 - type: integer + Parameter CLKIN_PERIOD bound to: 6000 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter MMCM_VCO bound to: 666 - type: integer + Parameter MMCM_MULT_F bound to: 8 - type: integer + Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter MEM_TYPE bound to: DDR3 - type: string +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] + Parameter BANDWIDTH bound to: HIGH - type: string + Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 12.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 16.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: BUF_IN - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.000000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 6.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double + Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter COMPENSATION bound to: INTERNAL - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] +INFO: [Synth 8-6157] synthesizing module 'BUFH' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:71] + Parameter TCQ bound to: 100 - type: integer + Parameter DDR3_VDD_OP_VOLT bound to: 135 - type: string + Parameter PAYLOAD_WIDTH bound to: 16 - type: integer + Parameter ADDR_CMD_MODE bound to: 1T - type: string + Parameter AL bound to: 0 - type: string + Parameter BANK_WIDTH bound to: 3 - type: integer + Parameter BM_CNT_WIDTH bound to: 2 - type: integer + Parameter BURST_MODE bound to: 8 - type: string + Parameter BURST_TYPE bound to: SEQ - type: string + Parameter CA_MIRROR bound to: OFF - type: string + Parameter CK_WIDTH bound to: 1 - type: integer + Parameter CL bound to: 5 - type: integer + Parameter COL_WIDTH bound to: 10 - type: integer + Parameter CMD_PIPE_PLUS1 bound to: ON - type: string + Parameter CS_WIDTH bound to: 1 - type: integer + Parameter CKE_WIDTH bound to: 1 - type: integer + Parameter CWL bound to: 5 - type: integer + Parameter DATA_WIDTH bound to: 16 - type: integer + Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer + Parameter DM_WIDTH bound to: 2 - type: integer + Parameter DQ_CNT_WIDTH bound to: 4 - type: integer + Parameter DQ_WIDTH bound to: 16 - type: integer + Parameter DQS_CNT_WIDTH bound to: 1 - type: integer + Parameter DQS_WIDTH bound to: 2 - type: integer + Parameter DRAM_TYPE bound to: DDR3 - type: string + Parameter DRAM_WIDTH bound to: 8 - type: integer + Parameter ECC bound to: OFF - type: string + Parameter ECC_WIDTH bound to: 0 - type: integer + Parameter ECC_TEST bound to: OFF - type: string + Parameter MC_ERR_ADDR_WIDTH bound to: 28 - type: integer + Parameter MASTER_PHY_CTL bound to: 0 - type: integer + Parameter nAL bound to: 0 - type: integer + Parameter nBANK_MACHS bound to: 4 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter nCS_PER_RANK bound to: 1 - type: integer + Parameter ORDERING bound to: NORM - type: string + Parameter IBUF_LPWR_MODE bound to: OFF - type: string + Parameter BANK_TYPE bound to: HR_IO - type: string + Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string + Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter OUTPUT_DRV bound to: LOW - type: string + Parameter REG_CTRL bound to: OFF - type: string + Parameter RTT_NOM bound to: 40 - type: string + Parameter RTT_WR bound to: OFF - type: string + Parameter STARVE_LIMIT bound to: 2 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter tCKE bound to: 5625 - type: integer + Parameter tFAW bound to: 45000 - type: integer + Parameter tPRDI bound to: 1000000 - type: integer + Parameter tRAS bound to: 36000 - type: integer + Parameter tRCD bound to: 13500 - type: integer + Parameter tREFI bound to: 7800000 - type: integer + Parameter tRFC bound to: 160000 - type: integer + Parameter tRP bound to: 13500 - type: integer + Parameter tRRD bound to: 7500 - type: integer + Parameter tRTP bound to: 7500 - type: integer + Parameter tWTR bound to: 7500 - type: integer + Parameter tZQI bound to: 128000000 - type: integer + Parameter tZQCS bound to: 64 - type: integer + Parameter USER_REFRESH bound to: OFF - type: string + Parameter TEMP_MON_EN bound to: ON - type: string + Parameter WRLVL bound to: ON - type: string + Parameter DEBUG_PORT bound to: OFF - type: string + Parameter CAL_WIDTH bound to: HALF - type: string + Parameter RANK_WIDTH bound to: 1 - type: integer + Parameter RANKS bound to: 1 - type: integer + Parameter ODT_WIDTH bound to: 1 - type: integer + Parameter ROW_WIDTH bound to: 14 - type: integer + Parameter ADDR_WIDTH bound to: 28 - type: integer + Parameter APP_MASK_WIDTH bound to: 16 - type: integer + Parameter APP_DATA_WIDTH bound to: 128 - type: integer + Parameter BYTE_LANES_B0 bound to: 4'b1111 + Parameter BYTE_LANES_B1 bound to: 4'b0000 + Parameter BYTE_LANES_B2 bound to: 4'b0000 + Parameter BYTE_LANES_B3 bound to: 4'b0000 + Parameter BYTE_LANES_B4 bound to: 4'b0000 + Parameter DATA_CTL_B0 bound to: 4'b1100 + Parameter DATA_CTL_B1 bound to: 4'b0000 + Parameter DATA_CTL_B2 bound to: 4'b0000 + Parameter DATA_CTL_B3 bound to: 4'b0000 + Parameter DATA_CTL_B4 bound to: 4'b0000 + Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110111111111111101111111111 + Parameter PHY_1_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter ADDR_MAP bound to: 192'b000000000000000000000000000000000000000000000010000000000100000000001001000000000111000000000001000000000101000000000110000000000011000000010000000000010010000000010100000000010001000000011010 + Parameter BANK_MAP bound to: 36'b000000011011000000010111000000010011 + Parameter CAS_MAP bound to: 12'b000000010101 + Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 + Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 + Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 + Parameter CKE_ODT_AUX bound to: FALSE - type: string + Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011 + Parameter PARITY_MAP bound to: 12'b000000000000 + Parameter RAS_MAP bound to: 12'b000000010110 + Parameter WE_MAP bound to: 12'b000000011000 + Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011 + Parameter DATA0_MAP bound to: 96'b000000110100000000110010000000111000000000110101000000110001000000110111000000110110000000110011 + Parameter DATA1_MAP bound to: 96'b000000100011000000100110000000100010000000101000000000100101000000100111000000100001000000100100 + Parameter DATA2_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA3_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001000000111001 + Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter SLOT_0_CONFIG bound to: 8'b00000001 + Parameter SLOT_1_CONFIG bound to: 8'b00000000 + Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string + Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 + Parameter CALIB_COL_ADD bound to: 12'b000000000000 + Parameter CALIB_BA_ADD bound to: 3'b000 + Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string + Parameter REFCLK_FREQ bound to: 200.000000 - type: double + Parameter USE_CS_PORT bound to: 1 - type: integer + Parameter USE_DM_PORT bound to: 1 - type: integer + Parameter USE_ODT_PORT bound to: 1 - type: integer + Parameter IDELAY_ADJ bound to: OFF - type: string + Parameter FINE_PER_BIT bound to: OFF - type: string + Parameter CENTER_COMP_MODE bound to: OFF - type: string + Parameter PI_VAL_ADJ bound to: OFF - type: string + Parameter SKIP_CALIB bound to: FALSE - type: string + Parameter TAPSPERKCLK bound to: 112 - type: integer + Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 28 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 128 - type: integer + Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer + Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string + Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer + Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer + Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer + Parameter FPGA_VOLT_TYPE bound to: N - type: string +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'OBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6157] synthesizing module 'IOBUF_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6155] done synthesizing module 'IOBUF_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6157] synthesizing module 'ODDR' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] +INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] +WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] +WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_init' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_calib_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mem_intfc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_wr_data' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_wr_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_rd_data' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wr_cmd_fsm' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_w_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_b_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v:83] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] +WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140] +WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141] +WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142] +WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143] +WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144] +WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181] +WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153] +WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681] +WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390] +WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-6014] Unused sequential element fine_delay_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:185] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737] +WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738] +WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739] +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791] +WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792] +WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628] +WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_max_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1116] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_index_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1146] +WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:690] +WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal_hr does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:131] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941] +WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697] +WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610] +WARNING: [Synth 8-6014] Unused sequential element sample_cnt_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:156] +WARNING: [Synth 8-6014] Unused sequential element reseed_prbs_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:157] +WARNING: [Synth 8-6014] Unused sequential element lfsr_q_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:174] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_cs1_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4271] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_odt_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4273] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1421] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_rank_cntr_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1539] +WARNING: [Synth 8-6014] Unused sequential element cnt_pwron_cke_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1781] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1814] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1815] +WARNING: [Synth 8-6014] Unused sequential element rnk_ref_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1941] +WARNING: [Synth 8-6014] Unused sequential element read_calib_int_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2720] +WARNING: [Synth 8-6014] Unused sequential element read_calib_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2727] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2778] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_all_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2783] +WARNING: [Synth 8-6014] Unused sequential element complex_row0_rd_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3339] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_wr_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3632] +WARNING: [Synth 8-6014] Unused sequential element extend_cal_pat_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3638] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_data_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3714] +WARNING: [Synth 8-6014] Unused sequential element victim_byte_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:818] +WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element prech_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1303] +WARNING: [Synth 8-6014] Unused sequential element calib_cmd_wren_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4229] +WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:534] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:535] +WARNING: [Synth 8-6014] Unused sequential element pat1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1124] +WARNING: [Synth 8-6014] Unused sequential element early1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1125] +WARNING: [Synth 8-6014] Unused sequential element rd_mux_sel_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:438] +WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155] +WARNING: [Synth 8-6014] Unused sequential element calib_complete_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:182] +WARNING: [Synth 8-6014] Unused sequential element sample_en_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:188] +WARNING: [Synth 8-6014] Unused sequential element device_temp_capture_102_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:290] +WARNING: [Synth 8-6014] Unused sequential element tempmon_sel_pi_incdec_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:883] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:898] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:899] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:900] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:901] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:902] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:903] +WARNING: [Synth 8-6014] Unused sequential element skip_calib_tap_off.skip_cal_tempmon_samp_en_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:2262] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_mux_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:834] +WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673] +WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662] +WARNING: [Synth 8-3848] Net dbg_poc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:335] +WARNING: [Synth 8-3848] Net fine_delay_incdec_pb in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:341] +WARNING: [Synth 8-3848] Net fine_delay_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:342] +WARNING: [Synth 8-3848] Net lim_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:620] +WARNING: [Synth 8-3848] Net lim2init_write_request in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:619] +WARNING: [Synth 8-3848] Net complex_ocal_num_samples_done_r in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:533] +WARNING: [Synth 8-3848] Net complex_ocal_rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:534] +WARNING: [Synth 8-3848] Net complex_victim_inc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:592] +WARNING: [Synth 8-3848] Net rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:588] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_start in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:597] +WARNING: [Synth 8-3848] Net oclk_center_write_resume in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:615] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:616] +WARNING: [Synth 8-6014] Unused sequential element app_wdf_rdy_r_copy4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:268] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:191] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:220] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:221] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:239] +WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96] +WARNING: [Synth 8-6014] Unused sequential element rd_last_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:216] +WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555] +WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:754] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:756] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:758] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:760] +WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:763] +WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:766] +WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:768] +WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:771] +WARNING: [Synth 8-3848] Net device_temp_i in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:784] +WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[7] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[6] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[5] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[4] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[3] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[2] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[1] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[0] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port wr_data_addr[4] in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port accept in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[11] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[10] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[9] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[8] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[7] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[6] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[5] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[4] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[3] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[2] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[1] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[0] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[99] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[98] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[97] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[96] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[95] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[94] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[93] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[16] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[15] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[14] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[12] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[11] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[10] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491527 ; free virtual = 627929 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491535 ; free virtual = 627937 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491535 ; free virtual = 627937 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2909.984 ; gain = 0.000 ; free physical = 491540 ; free virtual = 627942 +INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:346] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:353] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/arty_ddr3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/arty_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.828 ; gain = 0.000 ; free physical = 491553 ; free virtual = 627970 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 70 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 51 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3019.828 ; gain = 0.000 ; free physical = 491557 ; free virtual = 627975 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3019.828 ; gain = 779.066 ; free physical = 491702 ; free virtual = 628120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491702 ; free virtual = 628120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 28). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491707 ; free virtual = 628125 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + INIT_IDLE | 0001 | 000 + REQUEST_READ_TEMP | 1000 | 001 + WAIT_FOR_READ | 0100 | 010 + READ | 0010 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + WL_IDLE | 01110 | 00000 + WL_INIT | 10010 | 00001 + WL_INIT_FINE_INC | 01100 | 00010 + WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 + WL_INIT_FINE_INC_WAIT | 01001 | 00100 + WL_INIT_FINE_DEC | 11001 | 00101 + WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 + WL_INIT_FINE_DEC_WAIT | 11000 | 00110 + WL_WAIT | 00110 | 01000 + WL_EDGE_CHECK | 11011 | 01001 + WL_DQS_CNT | 10100 | 01011 + WL_FINE_DEC | 00000 | 01110 + WL_FINE_DEC_WAIT1 | 00001 | 11010 + WL_FINE_DEC_WAIT | 10001 | 01111 + WL_CORSE_DEC | 10110 | 10100 + WL_CORSE_DEC_WAIT | 11010 | 10101 + WL_CORSE_DEC_WAIT1 | 10101 | 10110 + WL_2RANK_DQS_CNT | 00010 | 01101 + WL_DQS_CHECK | 00011 | 01010 + WL_FINE_INC | 01101 | 00111 + WL_FINE_INC_WAIT | 10011 | 10111 + WL_2RANK_FINAL_TAP | 01111 | 11000 + WL_CORSE_INC | 01011 | 10000 + WL_CORSE_INC_WAIT_TMP | 10000 | 11011 + WL_CORSE_INC_WAIT | 01010 | 10001 + WL_CORSE_INC_WAIT1 | 00111 | 10010 + WL_CORSE_INC_WAIT2 | 00101 | 10011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + FINE_ADJ_IDLE | 0000 | 0000 + RST_WAIT | 0001 | 0011 + FINE_ADJ_DONE | 0010 | 1111 + RST_POSTWAIT | 0011 | 0001 + RST_POSTWAIT1 | 0100 | 0010 + FINE_ADJ_INIT | 0101 | 0100 + FINE_INC | 0110 | 0101 + FINE_INC_WAIT | 0111 | 0110 + FINE_INC_PREWAIT | 1000 | 0111 + DETECT_PREWAIT | 1001 | 1000 + DETECT_DQSFOUND | 1010 | 1001 + FINE_DEC | 1011 | 1011 + FINE_DEC_WAIT | 1100 | 1100 + FINE_DEC_PREWAIT | 1101 | 1101 + FINAL_WAIT | 1110 | 1110 + PRECH_WAIT | 1111 | 1010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + CAL1_IDLE | 00000000000000000000000000010000000 | 000000 + CAL1_NEW_DQS_WAIT | 00000000000000000000010000000000000 | 000001 + CAL1_STORE_FIRST_WAIT | 00000000000000000010000000000000000 | 000010 + CAL1_PAT_DETECT | 00000000000000100000000000000000000 | 000011 + CAL1_DQ_IDEL_TAP_INC | 00000000000000000000000000000000100 | 000100 +CAL1_DQ_IDEL_TAP_INC_WAIT | 00000000000000000000000000000001000 | 000101 + CAL1_MPR_PAT_DETECT | 00000000000000000000000010000000000 | 011111 + CAL1_VALID_WAIT | 10000000000000000000000000000000000 | 011110 + CAL1_DETECT_EDGE | 00000000000001000000000000000000000 | 001000 + CAL1_CALC_IDEL | 00000100000000000000000000000000000 | 001011 + CAL1_CENTER_WAIT | 00000000000000000000000000000000001 | 100010 + CAL1_IDEL_DEC_CPT | 00000000000000000000000000000000010 | 001100 + CAL1_DQ_IDEL_TAP_DEC | 00000000000000000001000000000000000 | 000110 +CAL1_DQ_IDEL_TAP_DEC_WAIT | 00100000000000000000000000000000000 | 000111 + CAL1_NEXT_DQS | 00000000000000000000000000000010000 | 001110 + CAL1_REGL_LOAD | 00000000000000000000000000001000000 | 011011 + CAL1_DONE | 00000000000000000000000000000100000 | 001111 + CAL1_NEW_DQS_PREWAIT | 00000000000000000000000000100000000 | 100000 + CAL1_MPR_NEW_DQS_WAIT | 00000000000000000000000001000000000 | 011101 + CAL1_IDEL_DEC_CPT_WAIT | 00000000000000000000100000000000000 | 001101 + CAL1_RD_STOP_FOR_PI_INC | 00000000000000000000000100000000000 | 100001 + CAL1_IDEL_INC_CPT | 00000000000000000000001000000000000 | 001001 + CAL1_IDEL_INC_CPT_WAIT | 00010000000000000000000000000000000 | 001010 + CAL1_RDLVL_ERR | 00000000000010000000000000000000000 | 011100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 00000000001 | 00000000001 + INIT | 00000000010 | 00000000010 + NEUTRAL | 00001000000 | 00001000000 + ONE_DEC | 00010000000 | 00010000000 + TWO_DEC | 00100000000 | 00100000000 + THREE_DEC | 01000000000 | 01000000000 + FOUR_DEC | 10000000000 | 10000000000 + ONE_INC | 00000100000 | 00000100000 + TWO_INC | 00000010000 | 00000010000 + THREE_INC | 00000001000 | 00000001000 + FOUR_INC | 00000000100 | 00000000100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + ZERO | 11 | 10 + ONE | 01 | 11 + TWO | 00 | 01 + iSTATE | 10 | 00 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491753 ; free virtual = 628175 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 4 Input 32 Bit Adders := 2 + 3 Input 32 Bit Adders := 1 + 2 Input 28 Bit Adders := 2 + 2 Input 13 Bit Adders := 1 + 2 Input 12 Bit Adders := 15 + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 6 + 2 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 8 + 3 Input 7 Bit Adders := 2 + 2 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 30 + 3 Input 6 Bit Adders := 3 + 2 Input 5 Bit Adders := 37 + 2 Input 4 Bit Adders := 34 + 2 Input 3 Bit Adders := 20 + 3 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 51 + 3 Input 2 Bit Adders := 3 + 4 Input 2 Bit Adders := 5 + 5 Input 2 Bit Adders := 1 + 8 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 5 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 5 Input 1 Bit Adders := 1 + 6 Input 1 Bit Adders := 1 + 7 Input 1 Bit Adders := 1 + 8 Input 1 Bit Adders := 1 + 9 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 144 Bit Registers := 1 + 128 Bit Registers := 5 + 88 Bit Registers := 1 + 80 Bit Registers := 3 + 56 Bit Registers := 1 + 32 Bit Registers := 3 + 30 Bit Registers := 1 + 28 Bit Registers := 6 + 16 Bit Registers := 13 + 15 Bit Registers := 4 + 14 Bit Registers := 6 + 13 Bit Registers := 1 + 12 Bit Registers := 33 + 11 Bit Registers := 1 + 10 Bit Registers := 4 + 9 Bit Registers := 12 + 8 Bit Registers := 15 + 7 Bit Registers := 5 + 6 Bit Registers := 59 + 5 Bit Registers := 46 + 4 Bit Registers := 82 + 3 Bit Registers := 47 + 2 Bit Registers := 66 + 1 Bit Registers := 1542 ++---Muxes : + 2 Input 128 Bit Muxes := 10 + 4 Input 128 Bit Muxes := 1 + 2 Input 127 Bit Muxes := 1 + 2 Input 80 Bit Muxes := 6 + 2 Input 56 Bit Muxes := 1 + 24 Input 35 Bit Muxes := 1 + 2 Input 35 Bit Muxes := 22 + 2 Input 32 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 12 + 4 Input 30 Bit Muxes := 4 + 2 Input 28 Bit Muxes := 11 + 2 Input 21 Bit Muxes := 8 + 2 Input 16 Bit Muxes := 8 + 3 Input 16 Bit Muxes := 1 + 3 Input 14 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 8 + 4 Input 14 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 5 + 12 Input 11 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 7 + 4 Input 9 Bit Muxes := 6 + 2 Input 9 Bit Muxes := 18 + 2 Input 8 Bit Muxes := 61 + 5 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 64 + 3 Input 7 Bit Muxes := 1 + 4 Input 7 Bit Muxes := 1 + 5 Input 7 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 81 + 4 Input 6 Bit Muxes := 8 + 27 Input 6 Bit Muxes := 4 + 5 Input 6 Bit Muxes := 2 + 16 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 5 + 3 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 35 + 8 Input 5 Bit Muxes := 2 + 27 Input 5 Bit Muxes := 1 + 58 Input 5 Bit Muxes := 1 + 24 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 2 + 3 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 67 + 32 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 69 + 27 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 3 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 101 + 4 Input 2 Bit Muxes := 7 + 3 Input 2 Bit Muxes := 9 + 8 Input 2 Bit Muxes := 4 + 27 Input 2 Bit Muxes := 1 + 24 Input 2 Bit Muxes := 2 + 5 Input 2 Bit Muxes := 1 + 10 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 491 + 3 Input 1 Bit Muxes := 12 + 8 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 204 + 27 Input 1 Bit Muxes := 27 + 5 Input 1 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 21 + 24 Input 1 Bit Muxes := 30 + 10 Input 1 Bit Muxes := 17 + 12 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[33]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:15 ; elapsed = 00:01:15 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 492131 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------------------+------------+---------------+----------------+ +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | ++------------------------------+------------+---------------+----------------+ + + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 359 of /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:359] +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491922 ; free virtual = 628371 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491872 ; free virtual = 628347 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491502 ; free virtual = 628069 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491390 ; free virtual = 628027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491389 ; free virtual = 628027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491437 ; free virtual = 628074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491436 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491436 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491435 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.pat_data_match_valid_r_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + + +Dynamic Shift Register Report: ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|dsrl | memory_reg[7] | 4 | 4 | 4 | 0 | 0 | 0 | 0 | +|dsrl__1 | memory_reg[31] | 129 | 129 | 0 | 129 | 0 | 0 | 0 | +|dsrl__2 | memory_reg[29] | 7 | 7 | 0 | 7 | 0 | 0 | 0 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------------------+------+ +| |Cell |Count | ++------+----------------------+------+ +|1 |BUFG | 3| +|2 |BUFH | 1| +|3 |BUFIO | 1| +|4 |CARRY4 | 124| +|5 |IDELAYCTRL | 1| +|6 |IDELAYE2 | 16| +|7 |IN_FIFO | 2| +|8 |ISERDESE2 | 16| +|9 |LUT1 | 375| +|10 |LUT2 | 438| +|11 |LUT3 | 1023| +|12 |LUT4 | 905| +|13 |LUT5 | 1361| +|14 |LUT6 | 1262| +|15 |MMCME2_ADV | 1| +|16 |MUXF7 | 28| +|17 |ODDR | 5| +|18 |OSERDESE2 | 43| +|21 |OUT_FIFO | 4| +|23 |PHASER_IN_PHY | 2| +|24 |PHASER_OUT_PHY | 4| +|26 |PHASER_REF | 1| +|27 |PHY_CONTROL | 1| +|28 |PLLE2_ADV | 1| +|29 |RAM32M | 112| +|30 |RAM32X1D | 2| +|31 |SRL16E | 20| +|32 |SRLC32E | 134| +|33 |XADC | 1| +|34 |FDCE | 2| +|35 |FDPE | 73| +|36 |FDRE | 3995| +|37 |FDSE | 123| +|38 |IOBUFDS_INTERMDISABLE | 2| +|39 |IOBUF_INTERMDISABLE | 16| +|40 |OBUF | 24| +|41 |OBUFDS | 1| +|42 |OBUFT | 2| ++------+----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491435 ; free virtual = 628072 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:21 ; elapsed = 00:01:23 . Memory (MB): peak = 3300.871 ; gain = 950.266 ; free physical = 491411 ; free virtual = 628048 +Synthesis Optimization Complete : Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 3300.879 ; gain = 1060.109 ; free physical = 491410 ; free virtual = 628047 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3300.879 ; gain = 0.000 ; free physical = 491722 ; free virtual = 628364 +INFO: [Netlist 29-17] Analyzing 325 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Opt 31-138] Pushed 2 inverter(s) to 16 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3356.898 ; gain = 0.000 ; free physical = 491719 ; free virtual = 628364 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 133 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 112 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances + +Synth Design complete | Checksum: cc6d6f52 +INFO: [Common 17-83] Releasing license: Synthesis +249 Infos, 303 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:30 ; elapsed = 00:01:28 . Memory (MB): peak = 3356.898 ; gain = 1120.105 ; free physical = 491719 ; free virtual = 628364 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3059.030; main = 2758.349; forked = 445.011 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4342.461; main = 3356.902; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 88 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' has been generated. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top toy_axi_cdc -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491808 ; free virtual = 628479 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'toy_axi_cdc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6155] done synthesizing module 'toy_axi_cdc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_WR_EN in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module dmem__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FAB_REGOUT_EN in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SFT_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SLEEP in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTDBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTSBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INT_CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module input_blk__parameterized2 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3416.914 ; gain = 0.000 ; free physical = 491893 ; free virtual = 628563 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3462.727 ; gain = 0.000 ; free physical = 491923 ; free virtual = 628592 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3462.727 ; gain = 0.000 ; free physical = 491923 ; free virtual = 628592 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491974 ; free virtual = 628643 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491974 ; free virtual = 628643 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491979 ; free virtual = 628648 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' +INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + invalid | 00 | 00 + stage1_valid | 10 | 10 + both_stages_valid | 11 | 11 + stage2_valid | 01 | 01 +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491969 ; free virtual = 628639 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 10 ++---XORs : + 2 Input 4 Bit XORs := 10 + 2 Input 1 Bit XORs := 110 ++---Registers : + 145 Bit Registers := 2 + 135 Bit Registers := 2 + 61 Bit Registers := 4 + 6 Bit Registers := 2 + 5 Bit Registers := 10 + 4 Bit Registers := 83 + 2 Bit Registers := 15 + 1 Bit Registers := 88 ++---Muxes : + 4 Input 2 Bit Muxes := 5 + 2 Input 2 Bit Muxes := 50 + 5 Input 2 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 15 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491967 ; free virtual = 628638 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492037 ; free virtual = 628707 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492041 ; free virtual = 628712 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492048 ; free virtual = 628719 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |LUT1 | 76| +|2 |LUT2 | 66| +|3 |LUT3 | 35| +|4 |LUT4 | 65| +|5 |LUT5 | 10| +|6 |LUT6 | 25| +|7 |RAM32M | 68| +|8 |RAM32X1D | 3| +|9 |FDCE | 130| +|10 |FDPE | 115| +|11 |FDRE | 1081| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 206 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 3462.727 ; gain = 12.000 ; free physical = 492086 ; free virtual = 628757 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.734 ; gain = 57.812 ; free physical = 492086 ; free virtual = 628757 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3462.734 ; gain = 0.000 ; free physical = 492379 ; free virtual = 629050 +INFO: [Netlist 29-17] Analyzing 71 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3462.734 ; gain = 0.000 ; free physical = 492413 ; free virtual = 629084 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 71 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 68 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 3 instances + +Synth Design complete | Checksum: ed94db3a +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 3462.734 ; gain = 57.820 ; free physical = 492415 ; free virtual = 629086 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3101.122; main = 2799.306; forked = 445.645 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4504.316; main = 3462.730; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 101 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 3470.730 ; gain = 0.000 ; free physical = 492418 ; free virtual = 629089 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' has been generated. +INFO: [Vivado 12-3441] generate_netlist_ip - operation complete +synth_ip: Time (s): cpu = 00:02:04 ; elapsed = 00:02:00 . Memory (MB): peak = 3470.730 ; gain = 1247.883 ; free physical = 492416 ; free virtual = 629088 +INFO: [Common 17-2834] synth_ip peak Physical Memory [PSS] (MB): overall = 3101.122; main = 2799.306; forked = 445.645 +INFO: [Common 17-2834] synth_ip peak Virtual Memory [VSS] (MB): overall = 4504.316; main = 3470.734; forked = 1041.586 +# phase SYNTH_BOARD +BOARD_PHASE SYNTH_BOARD +# if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { +# read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +# } +# read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +# foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +# set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +# read_xdc $root/board/arty_a7.xdc +# read_xdc $root/board/flash_boot.xdc +# synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +Command: synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=0 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3470.852 ; gain = 0.000 ; free physical = 492075 ; free virtual = 628755 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6901] identifier 'reset' is used before its declaration [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:30] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:1] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7023] instance 'clock_mmcm' of module 'MMCME2_BASE' has 18 connections declared, but only 9 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_platform' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:2] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:3] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:3] +INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:1] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:1] +INFO: [Synth 8-6157] synthesizing module 'ddr_uart_loader' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:99] +INFO: [Synth 8-6155] done synthesizing module 'ddr_uart_loader' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxChip' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxSystem' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569] +INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3011] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139] +INFO: [Synth 8-6157] synthesizing module 'plusarg_reader' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301] + Parameter FORMAT bound to: tilelink_timeout=%d - type: string + Parameter WIDTH bound to: 32 - type: integer + Parameter DEFAULT bound to: 32'b00000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'plusarg_reader' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3033] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4310] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6157] synthesizing module 'AXI4Buffer' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'ram_2x58' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x58' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'ram_2x73' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x73' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleB' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'ram_2x4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleB' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6157] synthesizing module 'ram_2x69' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x69' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Buffer' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'ram_2x8' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x8' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'Queue1_BundleMap' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'AXI4Deinterleaver' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'Queue8_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6157] synthesizing module 'ram_8x77' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'ram_8x77' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'Queue8_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Deinterleaver' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7423] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8551] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11207] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_5' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_5' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12453] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_6' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'ram_2x114' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x114' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6157] synthesizing module 'ram_2x79' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x79' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399] +INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13829] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_7' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_7' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449] +INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14907] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_8' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_8' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16078] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_9' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_9' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'ram_2x100' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x100' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028] +INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17199] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_10' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_10' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18288] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_11' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_11' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19205] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_12' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19035] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_12' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'MemoryBus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'ProbePicker' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20649] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_13' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_13' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'ProbePicker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap_6' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6157] synthesizing module 'ram_2x10' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x10' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23450] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_14' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_14' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6155] done synthesizing module 'MemoryBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'CoherenceManagerWrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491] +INFO: [Synth 8-6157] synthesizing module 'TLBroadcast' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26482] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_15' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_15' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6157] synthesizing module 'BroadcastFilter' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'BroadcastFilter' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Synth 8-6155] done synthesizing module 'ram_4x144' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756] +INFO: [Synth 8-6155] done synthesizing module 'Queue4_TLBroadcastData' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcast' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27453] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_16' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29794] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29834] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43249] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43271] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44089] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44825] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45961] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47133] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68592] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68606] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68620] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82885] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82084] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86970] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85223] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85231] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90541] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90573] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90605] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90637] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90669] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90701] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90733] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98928] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98950] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99569] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99575] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99581] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100308] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101303] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102505] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101968] + Parameter FLASH_BOOT bound to: 0 - type: integer +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52403] +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52405] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52416] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52418] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52420] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52422] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52424] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52426] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61288] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62163] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62183] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62375] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62376] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62378] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62379] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62390] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62391] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62393] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62394] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62497] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62498] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62499] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62500] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63220] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63221] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63222] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63223] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63224] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63225] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63226] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_7_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63227] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_8_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63228] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_9_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63229] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_10_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63230] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_11_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63231] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_12_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63232] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_13_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63233] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_14_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63234] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_15_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63235] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76912] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76914] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76916] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76919] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76922] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76926] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76930] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76935] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76940] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76946] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76952] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76959] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76968] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76970] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76973] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76977] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76982] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76988] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_84_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77024] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_85_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77026] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_87_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77029] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_90_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77033] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_94_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77038] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_99_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77044] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_105_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77052] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_106_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77054] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_108_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77057] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_111_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77061] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_115_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77066] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_120_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77072] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76917] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76920] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76923] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76924] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76927] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76928] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76931] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76932] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76933] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76936] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76937] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76938] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76941] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76942] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76943] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76944] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76947] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76948] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76949] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76950] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76953] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76954] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76955] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76956] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76957] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76960] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76961] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76962] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76963] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76964] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76971] +INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_tag_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93740] +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +WARNING: [Synth 8-7129] Port wdata[63] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[62] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[61] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[60] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[59] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[58] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[57] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[56] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[55] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[54] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[53] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[52] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[51] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[50] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[49] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[48] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[47] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[46] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[45] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[44] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[43] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[42] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[41] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[40] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[39] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[38] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[37] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[36] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[35] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[34] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[33] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[32] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[7] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[6] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[5] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[4] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_miso in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_recovery in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[3] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[2] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[1] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[0] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[16] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[15] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[14] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[13] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[12] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[11] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[10] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[9] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[8] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_corrupt in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_28 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3813.723 ; gain = 342.871 ; free physical = 491660 ; free virtual = 628352 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3828.566 ; gain = 357.715 ; free physical = 491683 ; free virtual = 628374 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3828.566 ; gain = 357.715 ; free physical = 491683 ; free virtual = 628374 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3828.566 ; gain = 0.000 ; free physical = 491693 ; free virtual = 628384 +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3996.254 ; gain = 0.000 ; free physical = 491625 ; free virtual = 628316 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + MMCME2_BASE => MMCME2_ADV: 1 instance + +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'uart_rx' +WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13813] +WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '100' to '13' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14825] +WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30468] +WARNING: [Synth 8-3936] Found unconnected internal register 'r_raddr_reg' and it is trimmed from '11' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36089] +WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50199] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54509] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54256] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mcounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55509] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_scounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55511] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mideleg_reg' and it is trimmed from '64' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55493] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_medeleg_reg' and it is trimmed from '64' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55497] +WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62438] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_reg_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84823] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_cmd_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84821] +WARNING: [Synth 8-3936] Found unconnected internal register 'reqReg_vaddr_reg' and it is trimmed from '64' to '39' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86206] +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MemConfiger' +INFO: [Synth 8-802] inferred FSM for state register 'ws_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'rs_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'loader_axi' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000 | 000 + START | 001 | 001 + DATA | 010 | 010 + STOP | 011 | 011 + WAIT_HIGH | 100 | 100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'uart_rx' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE3 | 00000001 | 000 + iSTATE2 | 00000010 | 001 + iSTATE6 | 00000100 | 010 + iSTATE4 | 00010000 | 011 + iSTATE1 | 00100000 | 100 + iSTATE5 | 00001000 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'MemConfiger' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + P_D965DF20 | 00 | 00 + P_D965DC20 | 01 | 01 + P_D965E030 | 10 | 10 + P_D9611170 | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'ws_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + R_IDLE | 00 | 00 + R_SEND | 01 | 01 + R_RESP | 10 | 10 + R_RETURN | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'rs_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000001 | 000 + SEND_W | 100000 | 001 + WAIT_B | 010000 | 010 + SEND_R | 001000 | 011 + WAIT_R | 000100 | 100 + RELEASE | 000010 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'loader_axi' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:42 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 486720 ; free virtual = 623434 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/atomics/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/atomics/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/picker/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/picker/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'platform/chip/system/tile_prci_domain/intsource_2' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader_1' +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 109 Bit Adders := 1 + 2 Input 107 Bit Adders := 1 + 2 Input 73 Bit Adders := 1 + 3 Input 65 Bit Adders := 1 + 2 Input 64 Bit Adders := 21 + 3 Input 64 Bit Adders := 2 + 3 Input 58 Bit Adders := 1 + 2 Input 58 Bit Adders := 2 + 2 Input 55 Bit Adders := 4 + 2 Input 48 Bit Adders := 1 + 2 Input 40 Bit Adders := 3 + 3 Input 39 Bit Adders := 5 + 2 Input 39 Bit Adders := 3 + 2 Input 37 Bit Adders := 1 + 2 Input 34 Bit Adders := 1 + 2 Input 33 Bit Adders := 3 + 2 Input 32 Bit Adders := 18 + 3 Input 32 Bit Adders := 1 + 2 Input 30 Bit Adders := 8 + 3 Input 29 Bit Adders := 1 + 2 Input 28 Bit Adders := 1 + 2 Input 26 Bit Adders := 4 + 2 Input 20 Bit Adders := 64 + 2 Input 19 Bit Adders := 2 + 2 Input 17 Bit Adders := 2 + 3 Input 16 Bit Adders := 1 + 2 Input 16 Bit Adders := 12 + 2 Input 15 Bit Adders := 4 + 2 Input 14 Bit Adders := 7 + 4 Input 14 Bit Adders := 1 + 2 Input 13 Bit Adders := 6 + 3 Input 13 Bit Adders := 2 + 2 Input 12 Bit Adders := 12 + 3 Input 12 Bit Adders := 1 + 2 Input 11 Bit Adders := 4 + 2 Input 10 Bit Adders := 7 + 4 Input 10 Bit Adders := 1 + 3 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 14 + 3 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 16 + 3 Input 8 Bit Adders := 8 + 2 Input 7 Bit Adders := 6 + 3 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 13 + 3 Input 6 Bit Adders := 2 + 2 Input 5 Bit Adders := 9 + 2 Input 4 Bit Adders := 60 + 5 Input 4 Bit Adders := 1 + 4 Input 4 Bit Adders := 4 + 2 Input 3 Bit Adders := 65 + 3 Input 3 Bit Adders := 7 + 2 Input 2 Bit Adders := 70 + 3 Input 2 Bit Adders := 5 + 4 Input 2 Bit Adders := 1 + 3 Input 1 Bit Adders := 3 + 2 Input 1 Bit Adders := 126 + 4 Input 1 Bit Adders := 39 ++---XORs : + 2 Input 65 Bit XORs := 1 + 2 Input 64 Bit XORs := 5 + 2 Input 32 Bit XORs := 8 + 2 Input 29 Bit XORs := 8 + 2 Input 27 Bit XORs := 6 + 2 Input 25 Bit XORs := 16 + 2 Input 20 Bit XORs := 8 + 2 Input 18 Bit XORs := 8 + 2 Input 16 Bit XORs := 18 + 2 Input 11 Bit XORs := 8 + 2 Input 10 Bit XORs := 3 + 2 Input 4 Bit XORs := 3 + 2 Input 3 Bit XORs := 11 + 2 Input 2 Bit XORs := 8 + 2 Input 1 Bit XORs := 14 + 3 Input 1 Bit XORs := 2 + 4 Input 1 Bit XORs := 2 ++---Registers : + 1269 Bit Registers := 1 + 145 Bit Registers := 1 + 130 Bit Registers := 1 + 128 Bit Registers := 9 + 107 Bit Registers := 1 + 106 Bit Registers := 3 + 105 Bit Registers := 1 + 73 Bit Registers := 1 + 72 Bit Registers := 1 + 67 Bit Registers := 1 + 65 Bit Registers := 14 + 64 Bit Registers := 184 + 62 Bit Registers := 2 + 58 Bit Registers := 2 + 56 Bit Registers := 1 + 55 Bit Registers := 5 + 53 Bit Registers := 3 + 44 Bit Registers := 5 + 42 Bit Registers := 74 + 40 Bit Registers := 21 + 39 Bit Registers := 19 + 34 Bit Registers := 2 + 32 Bit Registers := 115 + 31 Bit Registers := 2 + 30 Bit Registers := 8 + 29 Bit Registers := 2 + 28 Bit Registers := 5 + 27 Bit Registers := 34 + 26 Bit Registers := 4 + 24 Bit Registers := 1 + 23 Bit Registers := 4 + 21 Bit Registers := 8 + 20 Bit Registers := 293 + 19 Bit Registers := 2 + 17 Bit Registers := 2 + 16 Bit Registers := 54 + 14 Bit Registers := 1 + 13 Bit Registers := 8 + 12 Bit Registers := 1 + 11 Bit Registers := 1 + 10 Bit Registers := 140 + 9 Bit Registers := 12 + 8 Bit Registers := 434 + 7 Bit Registers := 27 + 6 Bit Registers := 11 + 5 Bit Registers := 113 + 4 Bit Registers := 193 + 3 Bit Registers := 234 + 2 Bit Registers := 127 + 1 Bit Registers := 1664 ++---Multipliers : + 53x53 Multipliers := 1 + 73x73 Multipliers := 1 + 16x32 Multipliers := 6 + 16x39 Multipliers := 2 + 16x37 Multipliers := 1 ++---RAMs : + 64K Bit (1024 X 64 bit) RAMs := 8 + 8K Bit (256 X 32 bit) RAMs := 8 + 8K Bit (128 X 64 bit) RAMs := 8 + 2K Bit (16 X 128 bit) RAMs := 1 ++---Muxes : + 2 Input 130 Bit Muxes := 4 + 2 Input 128 Bit Muxes := 34 + 4 Input 128 Bit Muxes := 1 + 2 Input 109 Bit Muxes := 1 + 2 Input 108 Bit Muxes := 1 + 2 Input 65 Bit Muxes := 33 + 4 Input 65 Bit Muxes := 4 + 2 Input 64 Bit Muxes := 303 + 3 Input 64 Bit Muxes := 2 + 4 Input 64 Bit Muxes := 26 + 8 Input 64 Bit Muxes := 3 + 2 Input 62 Bit Muxes := 1 + 2 Input 61 Bit Muxes := 2 + 2 Input 58 Bit Muxes := 2 + 2 Input 56 Bit Muxes := 9 + 2 Input 55 Bit Muxes := 11 + 2 Input 54 Bit Muxes := 3 + 2 Input 53 Bit Muxes := 2 + 2 Input 52 Bit Muxes := 10 + 2 Input 51 Bit Muxes := 2 + 2 Input 48 Bit Muxes := 2 + 4 Input 44 Bit Muxes := 1 + 2 Input 44 Bit Muxes := 6 + 4 Input 42 Bit Muxes := 16 + 2 Input 40 Bit Muxes := 25 + 2 Input 39 Bit Muxes := 19 + 5 Input 39 Bit Muxes := 1 + 3 Input 39 Bit Muxes := 1 + 2 Input 38 Bit Muxes := 1 + 2 Input 34 Bit Muxes := 57 + 2 Input 33 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 129 + 3 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 4 + 13 Input 32 Bit Muxes := 2 + 10 Input 32 Bit Muxes := 1 + 8 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 4 + 2 Input 30 Bit Muxes := 8 + 2 Input 29 Bit Muxes := 5 + 2 Input 28 Bit Muxes := 13 + 2 Input 27 Bit Muxes := 5 + 2 Input 26 Bit Muxes := 15 + 2 Input 25 Bit Muxes := 6 + 2 Input 24 Bit Muxes := 2 + 2 Input 23 Bit Muxes := 11 + 2 Input 22 Bit Muxes := 388 + 2 Input 21 Bit Muxes := 6 + 2 Input 20 Bit Muxes := 621 + 2 Input 19 Bit Muxes := 11 + 4 Input 18 Bit Muxes := 1 + 2 Input 17 Bit Muxes := 1 + 4 Input 16 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 134 + 13 Input 16 Bit Muxes := 3 + 10 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 12 + 2 Input 13 Bit Muxes := 23 + 2 Input 12 Bit Muxes := 21 + 5 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 8 + 2 Input 10 Bit Muxes := 53 + 2 Input 9 Bit Muxes := 41 + 4 Input 9 Bit Muxes := 1 + 13 Input 9 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 370 + 6 Input 8 Bit Muxes := 1 + 3 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 13 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 28 + 4 Input 7 Bit Muxes := 1 + 7 Input 7 Bit Muxes := 2 + 6 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 32 + 4 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 1 + 6 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 103 + 4 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 10 + 2 Input 4 Bit Muxes := 198 + 3 Input 4 Bit Muxes := 5 + 5 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 4 + 6 Input 4 Bit Muxes := 1 + 13 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 225 + 8 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 7 + 4 Input 3 Bit Muxes := 11 + 5 Input 3 Bit Muxes := 5 + 6 Input 3 Bit Muxes := 2 + 2 Input 2 Bit Muxes := 257 + 4 Input 2 Bit Muxes := 16 + 3 Input 2 Bit Muxes := 9 + 5 Input 2 Bit Muxes := 2 + 16 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 1279 + 8 Input 1 Bit Muxes := 6 + 6 Input 1 Bit Muxes := 12 + 4 Input 1 Bit Muxes := 33 + 3 Input 1 Bit Muxes := 2 + 5 Input 1 Bit Muxes := 6 + 13 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3936] Found unconnected internal register 'subRob/sram/sram_ext/lanes[0].R0_data_reg' and it is trimmed from '1269' to '1262' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:103] +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52365] +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +INFO: [Synth 8-4471] merging register 'cfg_max_j_reg[15:0]' into 'cfg_max_j_reg[15:0]' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79428] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79511] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79576] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79605] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79627] +DSP Report: Generating DSP _GEN_363, operation Mode is: A2*B2. +DSP Report: register cfg_max_j_reg is absorbed into DSP _GEN_363. +DSP Report: register cfg_max_i_reg is absorbed into DSP _GEN_363. +DSP Report: operator _GEN_363 is absorbed into DSP _GEN_363. +DSP Report: Generating DSP _GEN_362, operation Mode is: A*B2. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP _GEN_362, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: A2*B2. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79677] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79681] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79681] +DSP Report: Generating DSP _irow_T_7, operation Mode is: C+A*B. +DSP Report: operator _irow_T_7 is absorbed into DSP _irow_T_7. +DSP Report: operator _irow_T_71 is absorbed into DSP _irow_T_7. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr5, operation Mode is: A*B. +DSP Report: operator io_inputAddr5 is absorbed into DSP io_inputAddr5. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP _icol_T_7, operation Mode is: C+A*B. +DSP Report: operator _icol_T_7 is absorbed into DSP _icol_T_7. +DSP Report: operator _icol_T_71 is absorbed into DSP _icol_T_7. +DSP Report: Generating DSP io_inputAddr2, operation Mode is: PCIN+A:B+C. +DSP Report: operator io_inputAddr2 is absorbed into DSP io_inputAddr2. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_weightAddr4, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr4 is absorbed into DSP io_weightAddr4. +DSP Report: operator io_weightAddr5 is absorbed into DSP io_weightAddr4. +DSP Report: Generating DSP io_weightAddr2, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr2 is absorbed into DSP io_weightAddr2. +DSP Report: operator io_weightAddr3 is absorbed into DSP io_weightAddr2. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr5, operation Mode is: A*B. +DSP Report: operator io_outputAddr5 is absorbed into DSP io_outputAddr5. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr2, operation Mode is: PCIN+(A:0x0):B+C. +DSP Report: operator io_outputAddr2 is absorbed into DSP io_outputAddr2. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_input_stride_reg' and it is trimmed from '32' to '22' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79776] +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_output_stride_reg' and it is trimmed from '32' to '24' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79780] +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +INFO: [Synth 8-4471] merging register 'reqReg_pixel_bytes_reg[9:0]' into 'reqReg_pixel_bytes_reg[9:0]' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86013] +DSP Report: Generating DSP rowSkip_reg, operation Mode is: (A*B)'. +DSP Report: register rowSkip_reg is absorbed into DSP rowSkip_reg. +DSP Report: operator rowSkip0 is absorbed into DSP rowSkip_reg. +DSP Report: Generating DSP readVaddr1, operation Mode is: A*B2. +DSP Report: register reqReg_pixel_bytes_reg is absorbed into DSP readVaddr1. +DSP Report: operator readVaddr1 is absorbed into DSP readVaddr1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 17 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58083] +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port auto_buffer_out_1_c_bits_source[1] driven by constant 0 +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +--------------------------------------------------------------------------------- +Start Pre Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Iterative Area Optimization +--------------------------------------------------------------------------------- +INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] ) +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[1]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[2]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (sharedFma/\io_out_pipe_b_exc_reg[3] ) +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[9]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[6]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[7]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[8]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_15_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[9]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[6]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[7]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[8]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_14_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[9]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[6]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[7]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[8]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_13_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[9]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[6]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[7]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[8]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_12_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[9]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[6]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[7]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[8]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_11_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[9]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[6]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[7]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[8]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_10_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[9]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[6]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[7]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[8]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_9_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[9]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[6]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[7]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[8]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_8_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[9]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[6]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[7]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[8]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_7_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[9]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[6]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[7]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[8]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_6_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[9]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[6]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[7]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[8]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_5_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[9]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[6]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[7]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[8]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_4_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[9]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[6]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[7]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[8]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_3_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[9]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[6]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[7]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[8]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_2_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[9]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[6]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[7]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[8]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_1_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[9]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[6]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[7]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[8]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_0_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[9]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[9]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[9]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[9]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[9]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[9]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[9]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[9]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[9]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[9]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[9]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[9]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[9]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[9]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[9]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[9]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[6]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[6]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[6]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[6]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[6]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[6]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[6]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[6]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[6]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[6]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[6]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[6]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[6]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[6]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[6]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[6]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[7]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[7]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_15_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_14_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_13_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_12_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_11_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_10_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_9_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_8_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_5_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_4_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_3_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_2_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_0_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[7]) is unused and will be removed from module MemConfiger. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[6]) is unused and will be removed from module MemConfiger. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/s1_req_tag_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/\ex_reg_cause_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mie_reg[38] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mcountinhibit_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/io_cache_s1_data_r_data_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/reg_singleStepped_reg) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_satp_mode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[40] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[41] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[42] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[43] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[44] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[45] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[46] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[47] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[48] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[49] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[50] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[51] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[52] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[53] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[54] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[55] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[56] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[57] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[58] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[59] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[60] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[61] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[62] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (cores_0/csr/\reg_misa_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[10] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_108_113 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_102_107 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_96_101 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_90_95 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_84_89 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_78_83 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_72_77 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_66_71 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_60_65 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_54_59 from module BBTile__GCB1 due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_10/buffer_1/nodeOut_a_q/ram_ext/Memory_reg_0_1_6_11 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_48_53 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_13/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_14/i_0/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg_0_7_60_65 from module extram__61 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +--------------------------------------------------------------------------------- +Start Post Area Optimization : Time (s): cpu = 00:12:02 ; elapsed = 00:12:36 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 468157 ; free virtual = 608469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:12:08 ; elapsed = 00:12:42 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 467930 ; free virtual = 608253 +--------------------------------------------------------------------------------- + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_11 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_12 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_13 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_14 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_15 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_16 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_17 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_18 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_19 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_20 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_21 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_22 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_23 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_24 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_25 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_26 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_27 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_28 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_29 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_30 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is BBTile__GCB0 remainder1_8 : 0 0 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 1 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 2 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 3 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 0 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 1 : 3475 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 2 : 3494 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 3 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 0 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 1 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 2 : 3494 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 3 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 0 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 1 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 2 : 3341 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 0 : 3274 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 1 : 3137 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 2 : 3322 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 0 : 3137 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 1 : 3156 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 2 : 3185 9478 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 0 : 2588 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 1 : 3219 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 0 : 3052 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 1 : 2738 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 0 : 3034 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 1 : 2738 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 0 : 2722 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 1 : 265 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr2_19 : 0 0 : 2838 2838 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 0 : 1946 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 1 : 222 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_363_0 : 0 0 : 1978 1978 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr5_d : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr5_1c : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_a : 0 0 : 1207 1207 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _icol_T_7_b : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _irow_T_7_11 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr4_17 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is MemFrontend rowSkip_reg_0 : 0 0 : 768 768 : Used 1 time 0 + Sort Area is MemFrontend readVaddr1_2 : 0 0 : 733 733 : Used 1 time 0 +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 16 | 16 | - | - | 32 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B2 | 18 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 18 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 24 | 16 | - | - | 40 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | 39 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 16 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 24 | 16 | 16 | - | 39 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+(A:0x0):B+C | 30 | 16 | 37 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 21 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|StreamReader | (A*B)' | 19 | 6 | - | - | 25 | 0 | 0 | - | - | - | 1 | 0 | +|StreamReader | A*B2 | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 6 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:12:14 ; elapsed = 00:12:49 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 466997 ; free virtual = 607433 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:12:27 ; elapsed = 00:13:02 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 466864 ; free virtual = 607304 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:12:46 ; elapsed = 00:13:20 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466890 ; free virtual = 607336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceComp of module ITraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceIssue of module ITraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceAlloc of module ITraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/pmc/pmcTraces_0 of module PMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/ldPmcTrace of module MemPMCTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/stPmcTrace of module MemPMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_0 of module MTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_1 of module MTraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_2 of module MTraceDPI__3 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_3 of module MTraceDPI__4 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_4 of module MTraceDPI__5 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_5 of module MTraceDPI__6 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_6 of module MTraceDPI having unconnected or no output ports +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:12:55 ; elapsed = 00:13:30 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466689 ; free virtual = 607217 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:12:55 ; elapsed = 00:13:30 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466688 ; free virtual = 607216 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:13:08 ; elapsed = 00:13:43 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466720 ; free virtual = 607249 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:13:08 ; elapsed = 00:13:43 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466720 ; free virtual = 607249 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466713 ; free virtual = 607242 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466706 ; free virtual = 607235 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_matmul_id_RegShifted_0_0_reg[2] | 16 | 3 | NO | NO | YES | 3 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_0_0_reg[19] | 7 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_1_6_0_reg[19] | 6 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_2_6_0_reg[19] | 5 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_6_0_reg[19] | 4 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_6_0_reg[19] | 3 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_last_RegShifted_0_0_reg | 16 | 1 | NO | NO | YES | 1 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_0_reg[7] | 3 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_0_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_0_reg[7] | 5 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_0_reg[7] | 6 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_0_reg[7] | 7 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_1_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_1_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_1_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_1_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_1_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_2_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_2_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_2_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_2_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_2_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/ibus_intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +DSP Final Report (the ' indicates corresponding REG is set) ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 24 | 16 | - | - | 40 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 16 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A*B'' | 24 | 16 | 16 | - | 39 | 0 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B'+C | 0 | 16 | - | - | 37 | 0 | 1 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 20 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|FpgaDspMac | C+A'*B | 30 | 18 | 48 | - | 20 | 1 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B'' | 16 | 16 | - | - | 32 | 2 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B' | 17 | 16 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A'*B'' | 16 | 15 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|StreamReader | (A*B')' | 19 | 4 | - | - | 25 | 0 | 1 | - | - | - | 0 | 1 | +|StreamReader | A*B' | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B'' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN>>17+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |toy_axi_cdc | 1| +|2 |arty_ddr3 | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |arty_ddr3 | 1| +|2 |toy_axi_cdc | 1| +|3 |BUFG | 4| +|4 |CARRY4 | 1950| +|5 |DSP48E1 | 117| +|18 |LUT1 | 817| +|19 |LUT2 | 4360| +|20 |LUT3 | 12197| +|21 |LUT4 | 10130| +|22 |LUT5 | 12422| +|23 |LUT6 | 18450| +|24 |MMCME2_BASE | 1| +|25 |MUXF7 | 629| +|26 |MUXF8 | 112| +|27 |RAM128X1D | 16| +|28 |RAM16X1D | 1| +|29 |RAM32M | 665| +|30 |RAM32X1D | 21| +|31 |RAM32X1S | 92| +|32 |RAM64M | 12| +|33 |RAM64X1S | 42| +|34 |RAMB18E1 | 8| +|35 |RAMB36E1 | 27| +|38 |SRL16E | 225| +|39 |FDCE | 8| +|40 |FDPE | 6| +|41 |FDRE | 28184| +|42 |FDSE | 457| +|43 |IBUF | 4| +|44 |OBUF | 9| ++------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466706 ; free virtual = 607235 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 571 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:12:56 ; elapsed = 00:13:37 . Memory (MB): peak = 6518.039 ; gain = 2875.582 ; free physical = 474549 ; free virtual = 615080 +Synthesis Optimization Complete : Time (s): cpu = 00:13:13 ; elapsed = 00:13:48 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 474565 ; free virtual = 615078 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' for cell 'memory_cdc' +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' for cell 'ddr_controller' +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474568 ; free virtual = 615080 +INFO: [Netlist 29-17] Analyzing 4089 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2024.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474581 ; free virtual = 615093 +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 16 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615073 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1054 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + MMCME2_BASE => MMCME2_ADV: 1 instance + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 16 instances + RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 845 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 26 instances + RAM32X1S => RAM32X1S (RAMS32): 92 instances + RAM64M => RAM64M (RAMD64E(x4)): 12 instances + RAM64X1S => RAM64X1S (RAMS64E): 42 instances + +Synth Design complete | Checksum: 2dfdb574 +INFO: [Common 17-83] Releasing license: Synthesis +608 Infos, 466 Warnings, 4 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:13:44 ; elapsed = 00:14:10 . Memory (MB): peak = 6518.039 ; gain = 3047.309 ; free physical = 474561 ; free virtual = 615074 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 13700.579; main = 5845.433; forked = 8252.530 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19180.555; main = 6514.125; forked = 12666.434 +# write_checkpoint -force $out/synthesized.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615074 +Write Physdb Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615074 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474553 ; free virtual = 615074 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synthesized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 6538.129 ; gain = 20.090 ; free physical = 474489 ; free virtual = 615068 +# report_utilization -file $out/synth-utilization.rpt +# report_utilization -hierarchical -file $out/synth-hierarchy.rpt +# report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474378 ; free virtual = 614957 +# set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +# if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +# phase OPTIMIZE +BOARD_PHASE OPTIMIZE +# opt_design -directive ExploreArea +Command: opt_design -directive ExploreArea +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreArea +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.74 . Memory (MB): peak = 6570.145 ; gain = 32.016 ; free physical = 474363 ; free virtual = 614942 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474154 ; free virtual = 614733 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474146 ; free virtual = 614725 +Phase 1 Initialization | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474146 ; free virtual = 614725 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473991 ; free virtual = 614570 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473983 ; free virtual = 614562 +Phase 2 Timer Update And Timing Data Collection | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473983 ; free virtual = 614562 + +Phase 3 Retarget +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-1566] Pulled 311 inverters resulting in an inversion of 2868 pins +INFO: [Opt 31-138] Pushed 8 inverter(s) to 9 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 21a22d777 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473922 ; free virtual = 614502 +Retarget | Checksum: 21a22d777 +INFO: [Opt 31-389] Phase Retarget created 97 cells and removed 603 cells +INFO: [Opt 31-1021] In phase Retarget, 52 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 2d2bd90bb + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473896 ; free virtual = 614496 +Constant propagation | Checksum: 2d2bd90bb +INFO: [Opt 31-389] Phase Constant propagation created 12 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Constant propagation, 30 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Sweep +Phase 5 Sweep | Checksum: 2d6232e06 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473899 ; free virtual = 614500 +Sweep | Checksum: 2d6232e06 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 333 cells +INFO: [Opt 31-1021] In phase Sweep, 150 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 264ce99c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473900 ; free virtual = 614501 +BUFG optimization | Checksum: 264ce99c3 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 264ce99c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473900 ; free virtual = 614500 +Shift Register Optimization | Checksum: 264ce99c3 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells +INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7a100t is unsupported + +Phase 8 Resynthesis +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-74] Optimized 105 modules. +INFO: [Opt 31-75] Optimized module 'AccPipe'. +INFO: [Opt 31-75] Optimized module 'AccPipe_11'. +INFO: [Opt 31-75] Optimized module 'AccPipe_12'. +INFO: [Opt 31-75] Optimized module 'AccPipe_13'. +INFO: [Opt 31-75] Optimized module 'AccPipe_14'. +INFO: [Opt 31-75] Optimized module 'AccPipe_15'. +INFO: [Opt 31-75] Optimized module 'AccPipe_16'. +INFO: [Opt 31-75] Optimized module 'BankScoreboard'. +INFO: [Opt 31-75] Optimized module 'DTLB'. +INFO: [Opt 31-75] Optimized module 'DivSqrtRawFN_small_e8_s24'. +INFO: [Opt 31-75] Optimized module 'FPToInt'. +INFO: [Opt 31-75] Optimized module 'GemminiExCtrl'. +INFO: [Opt 31-75] Optimized module 'IBuf'. +INFO: [Opt 31-75] Optimized module 'ICache'. +INFO: [Opt 31-75] Optimized module 'ITLB'. +INFO: [Opt 31-75] Optimized module 'LoopConvUnroller'. +INFO: [Opt 31-75] Optimized module 'MaxPeriodFibonacciLFSR_3'. +INFO: [Opt 31-75] Optimized module 'MemConfiger'. +INFO: [Opt 31-75] Optimized module 'MemMidend'. +INFO: [Opt 31-75] Optimized module 'MeshWithDelays'. +INFO: [Opt 31-75] Optimized module 'NonBlockingDCache'. +INFO: [Opt 31-75] Optimized module 'PE_64_186'. +INFO: [Opt 31-75] Optimized module 'PE_64_189'. +INFO: [Opt 31-75] Optimized module 'PE_64_192'. +INFO: [Opt 31-75] Optimized module 'PE_64_195'. +INFO: [Opt 31-75] Optimized module 'PE_64_198'. +INFO: [Opt 31-75] Optimized module 'PE_64_201'. +INFO: [Opt 31-75] Optimized module 'PE_64_204'. +INFO: [Opt 31-75] Optimized module 'PE_64_207'. +INFO: [Opt 31-75] Optimized module 'PE_64_210'. +INFO: [Opt 31-75] Optimized module 'PE_64_213'. +INFO: [Opt 31-75] Optimized module 'PE_64_216'. +INFO: [Opt 31-75] Optimized module 'PE_64_219'. +INFO: [Opt 31-75] Optimized module 'PE_64_222'. +INFO: [Opt 31-75] Optimized module 'PE_64_225'. +INFO: [Opt 31-75] Optimized module 'PE_64_228'. +INFO: [Opt 31-75] Optimized module 'PE_64_231'. +INFO: [Opt 31-75] Optimized module 'PE_64_234'. +INFO: [Opt 31-75] Optimized module 'PE_64_237'. +INFO: [Opt 31-75] Optimized module 'PE_64_240'. +INFO: [Opt 31-75] Optimized module 'PE_64_243'. +INFO: [Opt 31-75] Optimized module 'PE_64_246'. +INFO: [Opt 31-75] Optimized module 'PE_64_249'. +INFO: [Opt 31-75] Optimized module 'PE_64_252'. +INFO: [Opt 31-75] Optimized module 'PE_64_255'. +INFO: [Opt 31-75] Optimized module 'PE_64_258'. +INFO: [Opt 31-75] Optimized module 'PE_64_261'. +INFO: [Opt 31-75] Optimized module 'PE_64_264'. +INFO: [Opt 31-75] Optimized module 'PE_64_267'. +INFO: [Opt 31-75] Optimized module 'PE_64_270'. +INFO: [Opt 31-75] Optimized module 'PE_64_273'. +INFO: [Opt 31-75] Optimized module 'PE_64_276'. +INFO: [Opt 31-75] Optimized module 'PE_64_279'. +INFO: [Opt 31-75] Optimized module 'PE_64_282'. +INFO: [Opt 31-75] Optimized module 'PE_64_285'. +INFO: [Opt 31-75] Optimized module 'PE_64_288'. +INFO: [Opt 31-75] Optimized module 'PE_64_291'. +INFO: [Opt 31-75] Optimized module 'PE_64_294'. +INFO: [Opt 31-75] Optimized module 'PE_64_297'. +INFO: [Opt 31-75] Optimized module 'PE_64_300'. +INFO: [Opt 31-75] Optimized module 'PE_64_303'. +INFO: [Opt 31-75] Optimized module 'PE_64_306'. +INFO: [Opt 31-75] Optimized module 'PE_64_309'. +INFO: [Opt 31-75] Optimized module 'PE_64_312'. +INFO: [Opt 31-75] Optimized module 'PE_64_315'. +INFO: [Opt 31-75] Optimized module 'PE_64_318'. +INFO: [Opt 31-75] Optimized module 'PE_64_321'. +INFO: [Opt 31-75] Optimized module 'PE_64_324'. +INFO: [Opt 31-75] Optimized module 'PE_64_327'. +INFO: [Opt 31-75] Optimized module 'PE_64_330'. +INFO: [Opt 31-75] Optimized module 'PE_64_333'. +INFO: [Opt 31-75] Optimized module 'PE_64_336'. +INFO: [Opt 31-75] Optimized module 'PE_64_339'. +INFO: [Opt 31-75] Optimized module 'PE_64_342'. +INFO: [Opt 31-75] Optimized module 'PE_64_345'. +INFO: [Opt 31-75] Optimized module 'PE_64_348'. +INFO: [Opt 31-75] Optimized module 'PE_64_351'. +INFO: [Opt 31-75] Optimized module 'PE_64_354'. +INFO: [Opt 31-75] Optimized module 'Queue16_ReplayInternal'. +INFO: [Opt 31-75] Optimized module 'Queue1_RegMapperInput_i23_m8'. +INFO: [Opt 31-75] Optimized module 'Queue4_TLBroadcastData'. +INFO: [Opt 31-75] Optimized module 'Queue8_SramReadResp_39'. +INFO: [Opt 31-75] Optimized module 'Repeater_TLBundleA_a17d64s3k1z3u'. +INFO: [Opt 31-75] Optimized module 'ShiftQueue'. +INFO: [Opt 31-75] Optimized module 'SubROB'. +INFO: [Opt 31-75] Optimized module 'TLB'. +INFO: [Opt 31-75] Optimized module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c'. +INFO: [Opt 31-75] Optimized module 'TagQueue'. +INFO: [Opt 31-75] Optimized module 'WritebackUnit'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_bank_state__parameterized2'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_if_post_fifo'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_wrcal'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_rank_common'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_round_robin_arb'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_tempmon'. +INFO: [Opt 31-75] Optimized module 'axi_fullwidth'. +INFO: [Opt 31-75] Optimized module 'ram_2x58'. +INFO: [Opt 31-75] Optimized module 'ram_2x58_376'. +INFO: [Common 17-14] Message 'Opt 31-75' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Opt 31-1566] Pulled 2280 inverters resulting in an inversion of 7908 pins +INFO: [Opt 31-138] Pushed 4 inverter(s) to 19 load pin(s). +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 8 Resynthesis | Checksum: 23ff3679c + +Time (s): cpu = 00:02:41 ; elapsed = 00:00:53 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472072 ; free virtual = 612675 +Resynthesis | Checksum: 23ff3679c +INFO: [Opt 31-389] Phase Resynthesis created 19062 cells and removed 19811 cells +INFO: [Opt 31-1021] In phase Resynthesis, 151 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 9 Post Processing Netlist +Phase 9 Post Processing Netlist | Checksum: 23ff3679c + +Time (s): cpu = 00:02:41 ; elapsed = 00:00:53 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472074 ; free virtual = 612678 +Post Processing Netlist | Checksum: 23ff3679c +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 45 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 10 Finalization + +Phase 10.1 Finalizing Design Cores and Updating Shapes +Phase 10.1 Finalizing Design Cores and Updating Shapes | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472083 ; free virtual = 612686 + +Phase 10.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471942 ; free virtual = 612545 +Phase 10.2 Verifying Netlist Connectivity | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471934 ; free virtual = 612537 +Phase 10 Finalization | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471926 ; free virtual = 612529 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 97 | 603 | 52 | +| Constant propagation | 12 | 19 | 30 | +| Sweep | 0 | 333 | 150 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Resynthesis | 19062 | 19811 | 151 | +| Post Processing Netlist | 0 | 0 | 45 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471926 ; free virtual = 612529 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471723 ; free virtual = 612326 +Ending Netlist Obfuscation Task | Checksum: 1a072e151 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471715 ; free virtual = 612318 +INFO: [Common 17-83] Releasing license: Implementation +131 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:02:46 ; elapsed = 00:00:56 . Memory (MB): peak = 6570.145 ; gain = 32.016 ; free physical = 471661 ; free virtual = 612265 +# write_checkpoint -force $out/optimized.dcp +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470083 ; free virtual = 610686 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470083 ; free virtual = 610686 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610686 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610686 +Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610687 +Write Physdb Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470081 ; free virtual = 610686 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470074 ; free virtual = 610689 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/optimized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470006 ; free virtual = 610681 +# report_utilization -file $out/opt-utilization.rpt +# phase PLACE +BOARD_PHASE PLACE +# place_design -directive Explore +Command: place_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'Explore' directive. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470014 ; free virtual = 610691 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14f5d1a2b + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470014 ; free virtual = 610691 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470013 ; free virtual = 610690 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17dfc4ae4 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470042 ; free virtual = 610722 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610790 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610790 +Phase 1 Placer Initialization | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610791 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 20bb1dab5 + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470120 ; free virtual = 610816 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2286fe973 + +Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470140 ; free virtual = 610839 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 2286fe973 + +Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470127 ; free virtual = 610826 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a630b68c + +Time (s): cpu = 00:02:11 ; elapsed = 00:00:50 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470167 ; free virtual = 610887 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 5152 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2204 nets or LUTs. Breaked 0 LUT, combined 2204 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 470052 ; free virtual = 610865 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 2204 | 2204 | 0 | 1 | 00:00:02 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 2204 | 2204 | 0 | 4 | 00:00:02 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2a3298b58 + +Time (s): cpu = 00:02:21 ; elapsed = 00:00:55 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469384 ; free virtual = 610551 +Phase 2.4 Global Placement Core | Checksum: 28e960a12 + +Time (s): cpu = 00:02:34 ; elapsed = 00:01:00 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469678 ; free virtual = 610874 +Phase 2 Global Placement | Checksum: 28e960a12 + +Time (s): cpu = 00:02:34 ; elapsed = 00:01:01 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469678 ; free virtual = 610874 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 2ba6ea6d8 + +Time (s): cpu = 00:02:41 ; elapsed = 00:01:03 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469681 ; free virtual = 610876 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2733bb972 + +Time (s): cpu = 00:02:53 ; elapsed = 00:01:07 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469671 ; free virtual = 610867 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 27d09f09c + +Time (s): cpu = 00:02:54 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469668 ; free virtual = 610864 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 280076c81 + +Time (s): cpu = 00:02:54 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469675 ; free virtual = 610871 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 274e2b06e + +Time (s): cpu = 00:03:15 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465571 ; free virtual = 607195 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2462932d4 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465456 ; free virtual = 607080 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 3265b2010 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465404 ; free virtual = 607046 +Phase 3 Detail Placement | Checksum: 3265b2010 + +Time (s): cpu = 00:03:18 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465246 ; free virtual = 606904 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 260892d3c + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.277 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 1113813e2 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 459558 ; free virtual = 602864 +INFO: [Place 46-33] Processed net platform/loader/SR[0], BUFG insertion was skipped due to placement/routing conflicts. +INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 1f7ac6828 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 455937 ; free virtual = 600446 +Phase 4.1.1.1 BUFG Insertion | Checksum: 260892d3c + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:43 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 454364 ; free virtual = 599397 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.277. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 452011 ; free virtual = 597821 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 452010 ; free virtual = 597821 +Phase 4.1 Post Commit Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 450421 ; free virtual = 596761 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 448028 ; free virtual = 595156 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 8x8| +|___________|___________________|___________________| +| South| 2x2| 8x8| +|___________|___________________|___________________| +| East| 2x2| 8x8| +|___________|___________________|___________________| +| West| 1x1| 2x2| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 446097 ; free virtual = 593864 +Phase 4.3 Placer Reporting | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 444507 ; free virtual = 592800 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 444337 ; free virtual = 592687 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 444336 ; free virtual = 592686 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2e4b25a14 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 442564 ; free virtual = 591473 +Ending Placer Task | Checksum: 1eddddbab + +Time (s): cpu = 00:03:56 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 441290 ; free virtual = 590627 +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:04:00 ; elapsed = 00:01:48 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 440996 ; free virtual = 590428 +# write_checkpoint -force $out/placed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 440814 ; free virtual = 590264 +Wrote PlaceDB: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 451981 ; free virtual = 601581 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 451981 ; free virtual = 601581 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452075 ; free virtual = 601675 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 453042 ; free virtual = 603197 +# phase PHYS_OPT +BOARD_PHASE PHYS_OPT +# phys_opt_design -directive Explore +Command: phys_opt_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 441326 ; free virtual = 602523 +INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 1.277 | TNS= 0.000 | +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 441326 ; free virtual = 602523 +# phase ROUTE +BOARD_PHASE ROUTE +# route_design -directive Explore +Command: route_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'Explore'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: ee9480ea ConstDB: 0 ShapeSum: 4d76fb2b RouteDB: b1d25f96 +Post Restoration Checksum: NetGraph: 3122703f | NumContArr: 80923bb4 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 23706a12d + +Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434318 ; free virtual = 603900 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 23706a12d + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434125 ; free virtual = 603900 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 23706a12d + +Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434083 ; free virtual = 603902 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 2919fd49e + +Time (s): cpu = 00:01:07 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 429576 ; free virtual = 603961 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-1.411 | THS=-707.945| + + +Phase 2.4 Update Timing for Bus Skew + +Phase 2.4.1 Update Timing +Phase 2.4.1 Update Timing | Checksum: 24d0d505a + +Time (s): cpu = 00:01:30 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 426124 ; free virtual = 603406 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-2.372 | THS=-68.356| + +Phase 2.4 Update Timing for Bus Skew | Checksum: 25d8558af + +Time (s): cpu = 00:01:30 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 426009 ; free virtual = 603350 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 93600 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 93600 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 30f73531b + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 425562 ; free virtual = 603128 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 30f73531b + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 425546 ; free virtual = 603120 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass +Phase 4.1 Initial Net Routing Pass | Checksum: 373819a83 + +Time (s): cpu = 00:01:47 ; elapsed = 00:00:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424373 ; free virtual = 603481 +Phase 4 Initial Routing | Checksum: 373819a83 + +Time (s): cpu = 00:01:48 ; elapsed = 00:00:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424370 ; free virtual = 603478 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 + Number of Nodes with overlaps = 14547 + Number of Nodes with overlaps = 1474 + Number of Nodes with overlaps = 372 + Number of Nodes with overlaps = 120 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Global Iteration 0 | Checksum: 22ddfe875 + +Time (s): cpu = 00:03:05 ; elapsed = 00:01:18 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424370 ; free virtual = 603561 + +Phase 5.2 Global Iteration 1 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 18 + Number of Nodes with overlaps = 35 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.2 Global Iteration 1 | Checksum: 2caa5e21c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:25 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424320 ; free virtual = 603539 +Phase 5 Rip-up And Reroute | Checksum: 2caa5e21c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:26 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424320 ; free virtual = 603539 + +Phase 6 Delay and Skew Optimization + +Phase 6.1 Delay CleanUp + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 23ffe80c8 + +Time (s): cpu = 00:03:30 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 6.1 Delay CleanUp | Checksum: 2c7712393 + +Time (s): cpu = 00:03:30 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 + +Phase 6.2 Clock Skew Optimization +Phase 6.2 Clock Skew Optimization | Checksum: 2c7712393 + +Time (s): cpu = 00:03:31 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 +Phase 6 Delay and Skew Optimization | Checksum: 2c7712393 + +Time (s): cpu = 00:03:31 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603500 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +Phase 7.1 Hold Fix Iter | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:41 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424301 ; free virtual = 603520 +Phase 7 Post Hold Fix | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:41 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424301 ; free virtual = 603520 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 21.9621 % + Global Horizontal Routing Utilization = 26.5401 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:42 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424309 ; free virtual = 603528 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:42 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424309 ; free virtual = 603528 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 29fc7be2a + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424316 ; free virtual = 603535 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 29fc7be2a + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424316 ; free virtual = 603535 + +Phase 12 Post Router Timing +INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.276 | TNS=0.000 | WHS=0.012 | THS=0.000 | + +Phase 12 Post Router Timing | Checksum: 1f006e4a8 + +Time (s): cpu = 00:04:17 ; elapsed = 00:01:40 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424343 ; free virtual = 603562 +INFO: [Route 35-61] The design met the timing requirement. +Total Elapsed time in route_design: 100.15 secs + +Phase 13 Post-Route Event Processing +Phase 13 Post-Route Event Processing | Checksum: fa658e56 + +Time (s): cpu = 00:04:17 ; elapsed = 00:01:41 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424343 ; free virtual = 603562 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: fa658e56 + +Time (s): cpu = 00:04:18 ; elapsed = 00:01:41 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424351 ; free virtual = 603571 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:04:24 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424352 ; free virtual = 603571 +# write_checkpoint -force $out/routed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424337 ; free virtual = 603574 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424235 ; free virtual = 603557 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424235 ; free virtual = 603557 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.54 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424229 ; free virtual = 603567 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424222 ; free virtual = 603569 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424214 ; free virtual = 603561 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424214 ; free virtual = 603561 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424299 ; free virtual = 603605 +# phase REPORT +BOARD_PHASE REPORT +# report_utilization -file $out/routed-utilization.rpt +# report_utilization -hierarchical -file $out/routed-hierarchy.rpt +# report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424242 ; free virtual = 603549 +# report_route_status -file $out/route-status.rpt +# report_drc -file $out/drc.rpt +Command: report_drc -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt. +report_drc completed successfully +INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +# set cdc [report_cdc -details -return_string] +# set f [open $out/cdc.rpt w] +# puts $f $cdc +# close $f +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# set skew [report_bus_skew -return_string] +# set f [open $out/bus-skew.rpt w] +# puts $f $skew +# close $f +# report_methodology -file $out/methodology.rpt +Command: report_methodology -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 8 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424266 ; free virtual = 603608 +# report_io -file $out/io.rpt +report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424268 ; free virtual = 603610 +# report_clocks -file $out/clocks.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +# check_timing -verbose -file $out/check-timing.rpt +# if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +# if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +# foreach kind {max min} { +# set paths [get_timing_paths -delay_type $kind -max_paths 1] +# if {[llength $paths]==0} {error "Missing $kind timing paths"} +# if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +# } +# if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +# if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +# set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +# if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +# phase BITSTREAM +BOARD_PHASE BITSTREAM +# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +# write_bitstream -force $out/toy_a7.bit +Command: write_bitstream -force /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/toy_a7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +INFO: [Common 17-14] Message 'DRC DPIP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +INFO: [Common 17-14] Message 'DRC DPOP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +INFO: [Common 17-14] Message 'DRC DPOP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +WARNING: [DRC RTSTAT-10] No routable loads: 45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]... and (the first 15 of 25 listed). +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 360 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 7428160 bits. +Writing bitstream /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/toy_a7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +12 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424219 ; free virtual = 603708 +# phase COMPLETE +BOARD_PHASE COMPLETE +# puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" +PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=0; this build does not validate physical boot +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 20:37:08 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/drc.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/drc.rpt new file mode 100644 index 0000000..38a39cd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/drc.rpt @@ -0,0 +1,1855 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:22 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_drc -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 360 ++-----------+----------+------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+------------------------+------------+ +| DPIP-1 | Warning | Input pipelining | 152 | +| DPOP-1 | Warning | PREG Output pipelining | 102 | +| DPOP-2 | Warning | MREG Output pipelining | 104 | +| REQP-1709 | Warning | Clock output buffering | 1 | +| RTSTAT-10 | Warning | No routable loads | 1 | ++-----------+----------+------------------------+------------+ + +2. REPORT DETAILS +----------------- +DPIP-1#1 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#2 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#3 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#4 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#5 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#6 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#7 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#8 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#9 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#10 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#11 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#12 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#13 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#14 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#15 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#16 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#17 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#18 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#19 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#20 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#21 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#22 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#23 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#24 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#25 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#26 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#27 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#28 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#29 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#30 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#31 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#32 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#33 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#34 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#35 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#36 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#37 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#38 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#39 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#40 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#41 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#42 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#43 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#44 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#45 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#46 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#47 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#48 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#49 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#50 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#51 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#52 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#53 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#54 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#55 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#56 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#57 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#58 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#59 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#60 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#61 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#62 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#63 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#64 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#65 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#66 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#67 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#68 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#69 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#70 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#71 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#72 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#73 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#74 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#75 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#76 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#77 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#78 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#79 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#80 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#81 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#82 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#83 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#84 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#85 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#86 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#87 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#88 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#89 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#90 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#91 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#92 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#93 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#94 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#95 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#96 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#97 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#98 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#99 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#100 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#101 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#102 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#103 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#104 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#105 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#106 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#107 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#108 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#109 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#110 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#111 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#112 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#113 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#114 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#115 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#116 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#117 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#118 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#119 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#120 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#121 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#122 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#123 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#124 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#125 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#126 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#127 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#128 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#129 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#130 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#131 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#132 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#133 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#134 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#135 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#136 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#137 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#138 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#139 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#140 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#141 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#142 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#143 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#144 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#145 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#146 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#147 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#148 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#149 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#150 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#151 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPIP-1#152 Warning +Input pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +Related violations: + +DPOP-1#1 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#2 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#3 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#4 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#5 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#6 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#7 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#8 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#9 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#10 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#11 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#12 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#13 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#14 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#15 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#16 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#17 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#18 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#19 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#20 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#21 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#22 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#23 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#24 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#25 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#26 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#27 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#28 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#29 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#30 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#31 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#32 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#33 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#34 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#35 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#36 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#37 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#38 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#39 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#40 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#41 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#42 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#43 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#44 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#45 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#46 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#47 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#48 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#49 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#50 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#51 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#52 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#53 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#54 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#55 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#56 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#57 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#58 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#59 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#60 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#61 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#62 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#63 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#64 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#65 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#66 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#67 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#68 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#69 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#70 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#71 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#72 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#73 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#74 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#75 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#76 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#77 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#78 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#79 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#80 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#81 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#82 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#83 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#84 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#85 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#86 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#87 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#88 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#89 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#90 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#91 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#92 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#93 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#94 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#95 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#96 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#97 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#98 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#99 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#100 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#101 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-1#102 Warning +PREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +Related violations: + +DPOP-2#1 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#2 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#3 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#4 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#5 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#6 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#7 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#8 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#9 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#10 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#11 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#12 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#13 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#14 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#15 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#16 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#17 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#18 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#19 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#20 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#21 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#22 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#23 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#24 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#25 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#26 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#27 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#28 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#29 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#30 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#31 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#32 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#33 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#34 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#35 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#36 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#37 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#38 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#39 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#40 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#41 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#42 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#43 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#44 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#45 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#46 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#47 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#48 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#49 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#50 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#51 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#52 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#53 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#54 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#55 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#56 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#57 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#58 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#59 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#60 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#61 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#62 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#63 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#64 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#65 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#66 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#67 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#68 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#69 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#70 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#71 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#72 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#73 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#74 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#75 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#76 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#77 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#78 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#79 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#80 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#81 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#82 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#83 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#84 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#85 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#86 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#87 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#88 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#89 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#90 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#91 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#92 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#93 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#94 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#95 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#96 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#97 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#98 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#99 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#100 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#101 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#102 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#103 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +DPOP-2#104 Warning +MREG Output pipelining +DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +Related violations: + +REQP-1709#1 Warning +Clock output buffering +PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +Related violations: + +RTSTAT-10#1 Warning +No routable loads +45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], +memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0] + (the first 15 of 25 listed). +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/io.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/io.rpt new file mode 100644 index 0000000..67518e6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/io.rpt @@ -0,0 +1,366 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:37 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_io -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/io.rpt +| Design : toy_a7_top +| Device : xc7a100t +| Speed File : -1 +| Package : csg324 +| Package Version : FINAL 2012-07-17 +| Package Pin Delay Version : VERS. 2.0 2012-07-17 +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 62 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A4 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A5 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| A6 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| A8 | sw0 | High Range | IO_L12N_T1_MRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A9 | uart_txd_in | High Range | IO_L14N_T2_SRCC_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B4 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| B7 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | 3.30 | | | | | | | | | +| B11 | | High Range | IO_L4P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C5 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| C6 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| C7 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C12 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| D7 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| D8 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| D9 | btn0 | High Range | IO_L6N_T0_VREF_16 | INPUT | LVCMOS33 | 16 | | | | NONE | | FIXED | | | | NONE | | | | +| D10 | uart_rxd_out | High Range | IO_L19N_T3_VREF_16 | OUTPUT | LVCMOS33 | 16 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| E3 | CLK100MHZ | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | | +| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | | +| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | | +| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| H5 | led[0] | High Range | IO_L24N_T3_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | | +| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | | +| J5 | led[1] | High Range | IO_25_35 | OUTPUT | LVCMOS33 | 35 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | ddr3_dq[2] | High Range | IO_L2P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| K5 | ddr3_dq[0] | High Range | IO_L5P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| K6 | ddr3_reset_n | High Range | IO_0_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| K17 | flash_mosi | High Range | IO_L1P_T0_D00_MOSI_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| K18 | flash_miso | High Range | IO_L1N_T0_D01_DIN_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| L1 | ddr3_dm[0] | High Range | IO_L1P_T0_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | ddr3_dq[1] | High Range | IO_L2N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L4 | ddr3_dq[6] | High Range | IO_L5N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | ddr3_dq[3] | High Range | IO_L6P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L13 | flash_cs_n | High Range | IO_L6P_T0_FCS_B_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| L14 | flash_wp_n | High Range | IO_L2P_T0_D02_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| M1 | ddr3_dq[5] | High Range | IO_L1N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M2 | ddr3_dq[7] | High Range | IO_L4N_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M3 | ddr3_dq[4] | High Range | IO_L4P_T0_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| M4 | ddr3_cas_n | High Range | IO_L16P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M6 | ddr3_addr[1] | High Range | IO_L18P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| M14 | flash_hold_n | High Range | IO_L2N_T0_D03_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | ddr3_dqs_n[0] | High Range | IO_L3N_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N2 | ddr3_dqs_p[0] | High Range | IO_L3P_T0_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| N4 | ddr3_addr[2] | High Range | IO_L16N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N5 | ddr3_cke[0] | High Range | IO_L13P_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N6 | ddr3_addr[4] | High Range | IO_L18N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P2 | ddr3_ba[2] | High Range | IO_L15P_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P3 | ddr3_ras_n | High Range | IO_L14N_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P4 | ddr3_ba[1] | High Range | IO_L14P_T2_SRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P5 | ddr3_we_n | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | | +| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | ddr3_ba[0] | High Range | IO_L17P_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R2 | ddr3_addr[0] | High Range | IO_L15N_T2_DQS_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R3 | ddr3_dq[15] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R5 | ddr3_odt[0] | High Range | IO_L19N_T3_VREF_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R6 | ddr3_addr[10] | High Range | IO_L19P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R7 | ddr3_addr[5] | High Range | IO_L23P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R8 | ddr3_addr[8] | High Range | IO_L24P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | ddr3_addr[3] | High Range | IO_L17N_T2_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| T3 | ddr3_dq[13] | High Range | IO_L11N_T1_SRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | ddr3_dq[9] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| T6 | ddr3_addr[12] | High Range | IO_L23N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | ddr3_addr[13] | High Range | IO_L24N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| T9 | led[2] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T10 | led[3] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| U1 | ddr3_dm[1] | High Range | IO_L7P_T1_34 | TRISTATE | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U2 | ddr3_dqs_p[1] | High Range | IO_L9P_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U3 | ddr3_dq[14] | High Range | IO_L8N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U4 | ddr3_dq[10] | High Range | IO_L8P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| U6 | ddr3_addr[11] | High Range | IO_L22N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U7 | ddr3_addr[7] | High Range | IO_L22P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U8 | ddr3_cs_n[0] | High Range | IO_25_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U9 | ddr3_ck_p[0] | High Range | IO_L21P_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | ddr3_dq[12] | High Range | IO_L7N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V2 | ddr3_dqs_n[1] | High Range | IO_L9N_T1_DQS_34 | BIDIR | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V4 | ddr3_dq[8] | High Range | IO_L10N_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V5 | ddr3_dq[11] | High Range | IO_L10P_T1_34 | BIDIR | SSTL135 | 34 | | FAST | UNTUNED_SPLIT_50 | FP_VTT_50 | | FIXED | | | Internal | NONE | | | | +| V6 | ddr3_addr[6] | High Range | IO_L20N_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V7 | ddr3_addr[9] | High Range | IO_L20P_T3_34 | OUTPUT | SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.35 | | | | | | | | | +| V9 | ddr3_ck_n[0] | High Range | IO_L21N_T3_DQS_34 | OUTPUT | DIFF_SSTL135 | 34 | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | ++------------+---------------+------------+------------------------------+-------------+--------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/ip-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/ip-status.rpt new file mode 100644 index 0000000..0b91f38 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/ip-status.rpt @@ -0,0 +1,33 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:14:28 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_ip_status +--------------------------------------------------------------------------------------------------------------------------------------------- + +IP Status Summary + +1. Project IP Status +-------------------- +Your project uses 2 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. + +More information on the Xilinx versioning policy is available at www.xilinx.com. + +Project IP Instances ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | +| | | | Log | | Version | | License | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| arty_ddr3 | Up-to-date | No changes required | *(1) | Memory Interface | 4.2 | 4.2 (Rev. 1) | Included | xc7a100tcsg324-1 | +| | | | | Generator (MIG 7 | (Rev. | | | | +| | | | | Series) | 1) | | | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| toy_axi_cdc | Up-to-date | No changes required | *(2) | AXI Clock | 2.1 | 2.1 (Rev. 30) | Included | xc7a100tcsg324-1 | +| | | | | Converter | (Rev. | | | | +| | | | | | 30) | | | | ++---------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +*(1) /data0/tools/Xilinx/Vivado/2024.1/data/ip/xilinx/mig_7series_v4_2/doc/mig_7series_v4_2_changelog.txt +*(2) /data0/tools/Xilinx/Vivado/2024.1/data/ip/xilinx/axi_clock_converter_v2_1/doc/axi_clock_converter_v2_1_changelog.txt + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/launcher.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/launcher.log new file mode 100644 index 0000000..e69de29 diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/methodology.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/methodology.rpt new file mode 100644 index 0000000..7d07e7e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/methodology.rpt @@ -0,0 +1,389 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:37 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_methodology -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------------------------------------------ + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: toy_a7_top + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 65 ++-----------+----------+-----------------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------------------------------------+------------+ +| LUTAR-1 | Warning | LUT drives async reset alert | 2 | +| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 16 | +| SYNTH-9 | Warning | Small multiplier | 5 | +| SYNTH-10 | Warning | Wide multiplier | 21 | +| SYNTH-16 | Warning | Address collision | 1 | +| TIMING-10 | Warning | Missing property on synchronizer | 1 | +| ULMTCS-1 | Warning | Control Sets use limits recommend reduction | 1 | +| XDCB-5 | Warning | Runtime inefficient way to find pin objects | 2 | +| REQP-1959 | Advisory | connects_SERDES_RST_driver_not_FF | 16 | ++-----------+----------+-----------------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +LUTAR-1#1 Warning +LUT drives async reset alert +LUT cell ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__7/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__9/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[0]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[10]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[11]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[1]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[2]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[3]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[4]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[5]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[6]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[7]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[8]/PRE, +ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (the first 15 of 32 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +LUTAR-1#2 Warning +LUT drives async reset alert +LUT cell platform/loader/in_pipe_v_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR, +platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR, +platform/chip/system/ibus_intsource/reg_0__0/reg_0_reg/CLR, +platform/chip/system/plic_domain/intsource/reg_0/reg_0_reg/CLR +platform/chip/system/plic_domain/intsource_1/reg_0/reg_0_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +Related violations: + +SYNTH-5#1 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#2 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#3 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#4 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#5 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#6 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#7 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#8 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_0_127_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#9 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#10 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#11 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_2_2 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#12 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_3_3 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#13 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_4_4 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#14 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_5_5 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#15 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_6_6 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-5#16 Warning +Mapped onto distributed RAM because of timing constraints +The instance platform/loader/payload_reg_128_255_7_7 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. +Related violations: + +SYNTH-9#1 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[11]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#2 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[15]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#3 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[19]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#4 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[3]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-9#5 Warning +Small multiplier +Detected multiplier at sharedFma/fma/product_pipe_b_reg[7]_i_1 of size 20x3, it is implemented as LUTs due to its small size. To force the multiplier onto a DSP block, use the USE_DSP48 attribute. +Related violations: + +SYNTH-10#1 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#2 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__0 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#3 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 of size 23x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#4 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#5 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#6 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__2 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#7 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#8 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__4 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#9 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#10 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__6 of size 18x23, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#11 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#12 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#13 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__9 of size 18x18, it is decomposed from a wide multipler into 17 DSP blocks. +Related violations: + +SYNTH-10#14 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#15 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#16 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__1 of size 18x20, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#17 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__2 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#18 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__3 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#19 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__4 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#20 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__0 of size 20x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-10#21 Warning +Wide multiplier +Detected multiplier at platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg__1 of size 18x18, it is decomposed from a wide multipler into 10 DSP blocks. +Related violations: + +SYNTH-16#1 Warning +Address collision +Block RAM platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. +Related violations: + +TIMING-10#1 Warning +Missing property on synchronizer +One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage +Related violations: + +ULMTCS-1#1 Warning +Control Sets use limits recommend reduction +This design uses 1256 control sets (vs. available limit of 15850, determined by 1 control set per CLB). This exceeds the control set use guideline of 7.5 percent. This is at a level where reduction is RECOMMENDED (see UG949). Use report_control_sets to get more details. +Related violations: + +XDCB-5#1 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}]' of constraint 'set_false_path' uses inefficient query to find pin objects (see constraint position '12' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc (Line: 18) +Related violations: + +XDCB-5#2 Warning +Runtime inefficient way to find pin objects +The option '-to : [get_pins -hier -include_replicated_objects -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[*]/D}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '6' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. +Current XDC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc (Line: 356) +Related violations: + +REQP-1959#1 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#2 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#3 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#4 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#5 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#6 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#7 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#8 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#9 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#10 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#11 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#12 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#13 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#14 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#15 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + +REQP-1959#16 Advisory +connects_SERDES_RST_driver_not_FF +ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq: The RST pin should only be driven by a Flip-flop. +Related violations: + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/opt-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/opt-utilization.rpt new file mode 100644 index 0000000..88ddb17 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/opt-utilization.rpt @@ -0,0 +1,233 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:32:03 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/opt-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Optimized +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs* | 56386 | 0 | 0 | 63400 | 88.94 | +| LUT as Logic | 52343 | 0 | 0 | 63400 | 82.56 | +| LUT as Memory | 4043 | 0 | 0 | 19000 | 21.28 | +| LUT as Distributed RAM | 3664 | 0 | | | | +| LUT as Shift Register | 379 | 0 | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Flip Flop | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 562 | Yes | Set | - | +| 33078 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 60 | 60 | 0 | 210 | 28.57 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 28 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +7. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33078 | Flop & Latch | +| LUT6 | 20391 | LUT | +| LUT3 | 13504 | LUT | +| LUT5 | 12689 | LUT | +| LUT4 | 10385 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4885 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| LUT1 | 811 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 562 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| IBUF | 3 | IO | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/phase.txt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/phase.txt new file mode 100644 index 0000000..569f0b3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/phase.txt @@ -0,0 +1 @@ +COMPLETE diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/route-status.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/route-status.rpt new file mode 100644 index 0000000..d85abf0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/route-status.rpt @@ -0,0 +1,12 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 119398 : + # of nets not needing routing.......... : 25764 : + # of internally routed nets........ : 23639 : + # of nets with no loads............ : 2125 : + # of routable nets..................... : 93634 : + # of fully routed nets............. : 93634 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-hierarchy.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-hierarchy.rpt new file mode 100644 index 0000000..36d5e6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-hierarchy.rpt @@ -0,0 +1,1150 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:10 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -hierarchical -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed-hierarchy.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| toy_a7_top | (top) | 53929 | 50007 | 3644 | 278 | 33943 | 27 | 8 | 117 | +| (toy_a7_top) | (top) | 5 | 5 | 0 | 0 | 63 | 0 | 0 | 0 | +| ddr_controller | arty_ddr3 | 4569 | 3965 | 450 | 154 | 4081 | 0 | 0 | 0 | +| (ddr_controller) | arty_ddr3 | 216 | 0 | 216 | 0 | 0 | 0 | 0 | 0 | +| u_arty_ddr3_mig | arty_ddr3_mig | 4353 | 3965 | 234 | 154 | 4081 | 0 | 0 | 0 | +| temp_mon_enabled.u_tempmon | arty_ddr3mig_7series_v4_2_tempmon | 38 | 38 | 0 | 0 | 122 | 0 | 0 | 0 | +| u_ddr3_clk_ibuf | arty_ddr3mig_7series_v4_2_clk_ibuf | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr3_infrastructure | arty_ddr3mig_7series_v4_2_infrastructure | 6 | 6 | 0 | 0 | 32 | 0 | 0 | 0 | +| u_iodelay_ctrl | arty_ddr3mig_7series_v4_2_iodelay_ctrl | 1 | 1 | 0 | 0 | 15 | 0 | 0 | 0 | +| u_memc_ui_top_axi | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 4310 | 3922 | 234 | 154 | 3912 | 0 | 0 | 0 | +| (u_memc_ui_top_axi) | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem_intfc0 | arty_ddr3mig_7series_v4_2_mem_intfc | 3342 | 3287 | 38 | 17 | 2828 | 0 | 0 | 0 | +| ddr_phy_top0 | arty_ddr3mig_7series_v4_2_ddr_phy_top | 2738 | 2692 | 30 | 16 | 2301 | 0 | 0 | 0 | +| (ddr_phy_top0) | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr_calib_top | arty_ddr3mig_7series_v4_2_ddr_calib_top | 2242 | 2228 | 0 | 14 | 1980 | 0 | 0 | 0 | +| (u_ddr_calib_top) | arty_ddr3mig_7series_v4_2_ddr_calib_top | 95 | 94 | 0 | 1 | 29 | 0 | 0 | 0 | +| ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl | arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl | 527 | 527 | 0 | 0 | 872 | 0 | 0 | 0 | +| ddr_phy_tempmon_0 | arty_ddr3mig_7series_v4_2_ddr_phy_tempmon | 257 | 257 | 0 | 0 | 229 | 0 | 0 | 0 | +| dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr | arty_ddr3mig_7series_v4_2_ddr_phy_dqs_found_cal_hr | 146 | 145 | 0 | 1 | 91 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay | arty_ddr3mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay | 17 | 16 | 0 | 1 | 16 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_wrlvl | arty_ddr3mig_7series_v4_2_ddr_phy_wrlvl | 264 | 263 | 0 | 1 | 160 | 0 | 0 | 0 | +| u_ddr_phy_init | arty_ddr3mig_7series_v4_2_ddr_phy_init | 794 | 790 | 0 | 4 | 279 | 0 | 0 | 0 | +| u_ddr_phy_wrcal | arty_ddr3mig_7series_v4_2_ddr_phy_wrcal | 159 | 153 | 0 | 6 | 304 | 0 | 0 | 0 | +| u_ddr_mc_phy_wrapper | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 496 | 464 | 30 | 2 | 321 | 0 | 0 | 0 | +| (u_ddr_mc_phy_wrapper) | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | +| u_ddr_mc_phy | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 496 | 464 | 30 | 2 | 297 | 0 | 0 | 0 | +| (u_ddr_mc_phy) | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| ddr_phy_4lanes_0.u_ddr_phy_4lanes | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 496 | 464 | 30 | 2 | 281 | 0 | 0 | 0 | +| (ddr_phy_4lanes_0.u_ddr_phy_4lanes) | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 6 | 5 | 0 | 1 | 20 | 0 | 0 | 0 | +| ddr_byte_lane_A.ddr_byte_lane_A | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 51 | 21 | 30 | 0 | 20 | 0 | 0 | 0 | +| (ddr_byte_lane_A.ddr_byte_lane_A) | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_14 | 50 | 20 | 30 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_B.ddr_byte_lane_B | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 24 | 24 | 0 | 0 | 19 | 0 | 0 | 0 | +| (ddr_byte_lane_B.ddr_byte_lane_B) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_13 | 15 | 15 | 0 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_C.ddr_byte_lane_C | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 210 | 210 | 0 | 0 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_C.ddr_byte_lane_C) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 7 | 7 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo_11 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_12 | 22 | 22 | 0 | 0 | 24 | 0 | 0 | 0 | +| ddr_byte_lane_D.ddr_byte_lane_D | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 206 | 205 | 0 | 1 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_D.ddr_byte_lane_D) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 0 | 0 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo | 183 | 183 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 | 21 | 21 | 0 | 0 | 24 | 0 | 0 | 0 | +| mc0 | arty_ddr3mig_7series_v4_2_mc | 608 | 599 | 8 | 1 | 527 | 0 | 0 | 0 | +| (mc0) | arty_ddr3mig_7series_v4_2_mc | 6 | 6 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_mach0 | arty_ddr3mig_7series_v4_2_bank_mach | 495 | 495 | 0 | 0 | 362 | 0 | 0 | 0 | +| arb_mux0 | arty_ddr3mig_7series_v4_2_arb_mux | 195 | 195 | 0 | 0 | 45 | 0 | 0 | 0 | +| arb_row_col0 | arty_ddr3mig_7series_v4_2_arb_row_col | 195 | 195 | 0 | 0 | 40 | 0 | 0 | 0 | +| (arb_row_col0) | arty_ddr3mig_7series_v4_2_arb_row_col | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| col_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| config_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_6 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pre_4_1_1T_arb.pre_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_7 | 47 | 47 | 0 | 0 | 8 | 0 | 0 | 0 | +| row_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_8 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| arb_select0 | arty_ddr3mig_7series_v4_2_arb_select | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| bank_cntrl[0].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl | 71 | 71 | 0 | 0 | 75 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_5 | 8 | 8 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue | 41 | 41 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state | 23 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | +| bank_cntrl[1].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized0 | 69 | 69 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_4 | 13 | 13 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized0 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized0 | 21 | 21 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_cntrl[2].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized1 | 71 | 71 | 0 | 0 | 74 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_3 | 10 | 10 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized1 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized1 | 28 | 28 | 0 | 0 | 21 | 0 | 0 | 0 | +| bank_cntrl[3].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized2 | 71 | 71 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare | 14 | 14 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized2 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized2 | 25 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_common0 | arty_ddr3mig_7series_v4_2_bank_common | 26 | 26 | 0 | 0 | 22 | 0 | 0 | 0 | +| col_mach0 | arty_ddr3mig_7series_v4_2_col_mach | 26 | 18 | 8 | 0 | 26 | 0 | 0 | 0 | +| rank_mach0 | arty_ddr3mig_7series_v4_2_rank_mach | 81 | 80 | 0 | 1 | 66 | 0 | 0 | 0 | +| rank_cntrl[0].rank_cntrl0 | arty_ddr3mig_7series_v4_2_rank_cntrl | 10 | 9 | 0 | 1 | 13 | 0 | 0 | 0 | +| rank_common0 | arty_ddr3mig_7series_v4_2_rank_common | 71 | 71 | 0 | 0 | 53 | 0 | 0 | 0 | +| (rank_common0) | arty_ddr3mig_7series_v4_2_rank_common | 59 | 59 | 0 | 0 | 47 | 0 | 0 | 0 | +| maintenance_request.maint_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_axi_mc | arty_ddr3mig_7series_v4_2_axi_mc | 599 | 462 | 0 | 137 | 532 | 0 | 0 | 0 | +| (u_axi_mc) | arty_ddr3mig_7series_v4_2_axi_mc | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi_mc_ar_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 122 | 122 | 0 | 0 | 87 | 0 | 0 | 0 | +| (axi_mc_ar_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 1 | 1 | 0 | 0 | 45 | 0 | 0 | 0 | +| ar_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_fsm | 80 | 80 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator_0 | 43 | 43 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd_1 | 35 | 35 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd_2 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_aw_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 125 | 125 | 0 | 0 | 85 | 0 | 0 | 0 | +| (axi_mc_aw_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 0 | 0 | 0 | 0 | 43 | 0 | 0 | 0 | +| aw_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm | 79 | 79 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator | 47 | 47 | 0 | 0 | 41 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd | 39 | 39 | 0 | 0 | 33 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_b_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 11 | 7 | 0 | 4 | 9 | 0 | 0 | 0 | +| (axi_mc_b_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | +| bid_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo | 11 | 7 | 0 | 4 | 4 | 0 | 0 | 0 | +| axi_mc_cmd_arbiter_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_arbiter | 33 | 33 | 0 | 0 | 31 | 0 | 0 | 0 | +| axi_mc_r_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 160 | 27 | 0 | 133 | 24 | 0 | 0 | 0 | +| (axi_mc_r_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | +| rd_data_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized0 | 141 | 13 | 0 | 128 | 6 | 0 | 0 | 0 | +| transaction_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized1 | 19 | 14 | 0 | 5 | 6 | 0 | 0 | 0 | +| axi_mc_w_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_w_channel | 147 | 147 | 0 | 0 | 294 | 0 | 0 | 0 | +| u_ui_top | arty_ddr3mig_7series_v4_2_ui_top | 391 | 195 | 196 | 0 | 550 | 0 | 0 | 0 | +| ui_cmd0 | arty_ddr3mig_7series_v4_2_ui_cmd | 38 | 38 | 0 | 0 | 54 | 0 | 0 | 0 | +| ui_rd_data0 | arty_ddr3mig_7series_v4_2_ui_rd_data | 118 | 26 | 92 | 0 | 163 | 0 | 0 | 0 | +| ui_wr_data0 | arty_ddr3mig_7series_v4_2_ui_wr_data | 235 | 131 | 104 | 0 | 333 | 0 | 0 | 0 | +| memory_cdc | toy_axi_cdc | 452 | 190 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 452 | 190 | 262 | 0 | 1212 | 0 | 0 | 0 | +| (inst) | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_clock_conv.gen_async_conv.asyncfifo_axi | toy_axi_cdcfifo_generator_v13_2_10 | 451 | 189 | 262 | 0 | 1212 | 0 | 0 | 0 | +| inst_fifo_gen | toy_axi_cdcfifo_generator_v13_2_10_synth | 451 | 189 | 262 | 0 | 1212 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.axi_rach | toy_axi_cdcfifo_generator_top | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo | 73 | 39 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__17 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__16 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_21 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_27 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_29 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_22 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_25 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_26 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory_23 | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory_23 | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem_24 | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__16 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__11 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grdch2.axi_rdch | toy_axi_cdcfifo_generator_top__parameterized2 | 131 | 39 | 92 | 0 | 368 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized2 | 131 | 39 | 92 | 0 | 368 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__18 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_14 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_18 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_20 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_15 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_16 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_17 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized2 | 92 | 0 | 92 | 0 | 270 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized2 | 0 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized2 | 92 | 0 | 92 | 0 | 135 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__18 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__13 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.axi_wach | toy_axi_cdcfifo_generator_top__xdcDup__1 | 71 | 37 | 34 | 0 | 174 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__xdcDup__1 | 71 | 37 | 34 | 0 | 174 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 10 | 10 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__11 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__10 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_7 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_11 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_13 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_8 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_9 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_10 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory | 34 | 0 | 34 | 0 | 76 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem | 34 | 0 | 34 | 0 | 38 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__11 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__10 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch | toy_axi_cdcfifo_generator_top__parameterized0 | 136 | 38 | 98 | 0 | 386 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized0 | 136 | 38 | 98 | 0 | 386 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 11 | 11 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__13 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__12 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_0 | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_4 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_6 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_1 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_2 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_3 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized0 | 98 | 0 | 98 | 0 | 288 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized0 | 0 | 0 | 0 | 0 | 144 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized0 | 98 | 0 | 98 | 0 | 144 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__8 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__13 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__12 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__7 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch | toy_axi_cdcfifo_generator_top__parameterized1 | 41 | 37 | 4 | 0 | 110 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized1 | 41 | 37 | 4 | 0 | 110 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 10 | 10 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__15 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__14 | 4 | 4 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized1 | 4 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized1 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized1 | 4 | 0 | 4 | 0 | 6 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 26 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__10 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__15 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__14 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__9 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| platform | toy_a7_platform | 48907 | 45851 | 2932 | 124 | 28587 | 27 | 8 | 117 | +| chip | ToyLinuxChip | 47912 | 44968 | 2820 | 124 | 27535 | 27 | 8 | 117 | +| system | ToyLinuxSystem | 47912 | 44968 | 2820 | 124 | 27535 | 27 | 8 | 117 | +| (system) | ToyLinuxSystem | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bootrom_domain | bootromClockSinkDomain | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| bootrom | TLROM | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| cbus | PeripheryBus_cbus | 969 | 815 | 154 | 0 | 364 | 0 | 0 | 0 | +| atomics | TLAtomicAutomata_cbus | 377 | 377 | 0 | 0 | 203 | 0 | 0 | 0 | +| buffer | TLBuffer_a28d64s3k1z4u | 263 | 133 | 130 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a28d64s3k1z4u | 111 | 57 | 54 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a28d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79_445 | 107 | 53 | 54 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a28d64s3k1z4u | 152 | 76 | 76 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a28d64s3k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x114 | 151 | 75 | 76 | 0 | 0 | 0 | 0 | 0 | +| coupler_to_bootrom | TLInterconnectCoupler_cbus_to_bootrom | 74 | 74 | 0 | 0 | 29 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_bootrom | 74 | 74 | 0 | 0 | 29 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_bootrom | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a17d64s3k1z3u | 73 | 73 | 0 | 0 | 20 | 0 | 0 | 0 | +| coupler_to_clint | TLInterconnectCoupler_cbus_to_clint | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_CLINT | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_CLINT | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a26d64s3k1z3u | 79 | 79 | 0 | 0 | 23 | 0 | 0 | 0 | +| coupler_to_plic | TLInterconnectCoupler_cbus_to_plic | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_PLIC | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_PLIC | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a28d64s3k1z3u | 21 | 21 | 0 | 0 | 33 | 0 | 0 | 0 | +| out_xbar | TLXbar_cbus_out_i1_o4_a28d64s3k1z4u | 81 | 81 | 0 | 0 | 17 | 0 | 0 | 0 | +| wrapped_error_device | ErrorDeviceWrapper | 77 | 53 | 24 | 0 | 35 | 0 | 0 | 0 | +| buffer | TLBuffer_a14d64s3k1z4u | 40 | 16 | 24 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a14d64s3k1z4u | 25 | 13 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a14d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79 | 21 | 9 | 12 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a14d64s3k1z4u | 15 | 3 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a14d64s3k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x100 | 13 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | +| error | TLError | 37 | 37 | 0 | 0 | 29 | 0 | 0 | 0 | +| (error) | TLError | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | +| a_q | Queue1_TLBundleA_a14d64s3k1z4u | 30 | 30 | 0 | 0 | 11 | 0 | 0 | 0 | +| clint_domain | CLINTClockSinkDomain | 70 | 70 | 0 | 0 | 131 | 0 | 0 | 0 | +| clint | CLINT | 70 | 70 | 0 | 0 | 129 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| coh_wrapper | CoherenceManagerWrapper | 539 | 347 | 192 | 0 | 142 | 0 | 0 | 0 | +| broadcast_1 | TLBroadcast | 539 | 347 | 192 | 0 | 142 | 0 | 0 | 0 | +| (broadcast_1) | TLBroadcast | 16 | 16 | 0 | 0 | 44 | 0 | 0 | 0 | +| TLBroadcastTracker | TLBroadcastTracker | 379 | 283 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker) | TLBroadcastTracker | 20 | 20 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData_443 | 360 | 264 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData_443 | 99 | 99 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144_444 | 261 | 165 | 96 | 0 | 0 | 0 | 0 | 0 | +| TLBroadcastTracker_1 | TLBroadcastTracker_1 | 147 | 51 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData | 115 | 19 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData | 14 | 14 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144 | 101 | 5 | 96 | 0 | 0 | 0 | 0 | 0 | +| ibus_intsink | IntSyncAsyncCrossingSink_n1x1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| chain | SynchronizerShiftReg_w1_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| ibus_intsource | IntSyncCrossingSource_n1x1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0__0 | AsyncResetRegVec_w1_i0_442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| mbus | MemoryBus | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 | 719 | 463 | 256 | 0 | 330 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker_1 | 439 | 183 | 256 | 0 | 96 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap_6 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap_6 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_441 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_6_380 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_6_380 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_440 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_10 | Queue2_BundleMap_6_381 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_10) | Queue2_BundleMap_6_381 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_439 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_11 | Queue2_BundleMap_6_382 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_11) | Queue2_BundleMap_6_382 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_438 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_12 | Queue2_BundleMap_6_383 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_12) | Queue2_BundleMap_6_383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_437 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_13 | Queue2_BundleMap_6_384 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_13) | Queue2_BundleMap_6_384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_436 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_14 | Queue2_BundleMap_6_385 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_14) | Queue2_BundleMap_6_385 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_435 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_15 | Queue2_BundleMap_6_386 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_15) | Queue2_BundleMap_6_386 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_434 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_16 | Queue2_BundleMap_6_387 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_16) | Queue2_BundleMap_6_387 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_433 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_17 | Queue2_BundleMap_6_388 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_17) | Queue2_BundleMap_6_388 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_432 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_18 | Queue2_BundleMap_6_389 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_18) | Queue2_BundleMap_6_389 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_431 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_19 | Queue2_BundleMap_6_390 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_19) | Queue2_BundleMap_6_390 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_430 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_6_391 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_6_391 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_429 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_20 | Queue2_BundleMap_6_392 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_20) | Queue2_BundleMap_6_392 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_428 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_21 | Queue2_BundleMap_6_393 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_21) | Queue2_BundleMap_6_393 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_427 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_22 | Queue2_BundleMap_6_394 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_22) | Queue2_BundleMap_6_394 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_426 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_23 | Queue2_BundleMap_6_395 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_23) | Queue2_BundleMap_6_395 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_425 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_24 | Queue2_BundleMap_6_396 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_24) | Queue2_BundleMap_6_396 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_424 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_25 | Queue2_BundleMap_6_397 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_25) | Queue2_BundleMap_6_397 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_423 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_26 | Queue2_BundleMap_6_398 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_26) | Queue2_BundleMap_6_398 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_422 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_27 | Queue2_BundleMap_6_399 | 43 | 35 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_27) | Queue2_BundleMap_6_399 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_421 | 42 | 34 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_28 | Queue2_BundleMap_6_400 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_28) | Queue2_BundleMap_6_400 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_420 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_29 | Queue2_BundleMap_6_401 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_29) | Queue2_BundleMap_6_401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_419 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_6_402 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_6_402 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_418 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_30 | Queue2_BundleMap_6_403 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_30) | Queue2_BundleMap_6_403 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_417 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_31 | Queue2_BundleMap_6_404 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_31) | Queue2_BundleMap_6_404 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_416 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_6_405 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_6_405 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_415 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_6_406 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_6_406 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_414 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_6 | Queue2_BundleMap_6_407 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_6) | Queue2_BundleMap_6_407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_413 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_7 | Queue2_BundleMap_6_408 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_7) | Queue2_BundleMap_6_408 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_412 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_8 | Queue2_BundleMap_6_409 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_8) | Queue2_BundleMap_6_409 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_411 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_9 | Queue2_BundleMap_6_410 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_9) | Queue2_BundleMap_6_410 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4_1 | 293 | 293 | 0 | 0 | 234 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4_1 | 3 | 3 | 0 | 0 | 41 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW_1 | 83 | 83 | 0 | 0 | 146 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW_1 | 208 | 208 | 0 | 0 | 47 | 0 | 0 | 0 | +| plic_domain | PLICClockSinkDomain | 33 | 33 | 0 | 0 | 52 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x1_377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0_379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| intsource_1 | IntSyncCrossingSource_n1x1_378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| plic | TLPLIC | 33 | 33 | 0 | 0 | 50 | 0 | 0 | 0 | +| (plic) | TLPLIC | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| gateways_gateway | LevelGateway | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| out_back_front_q | Queue1_RegMapperInput_i23_m8 | 28 | 28 | 0 | 0 | 41 | 0 | 0 | 0 | +| sbus | SystemBus | 1370 | 1036 | 334 | 0 | 608 | 0 | 0 | 0 | +| coupler_to_bus_named_cbus | TLInterconnectCoupler_sbus_to_bus_named_cbus | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| widget | TLWidthWidget16 | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16 | 64 | 64 | 0 | 0 | 68 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a28d128s3k1z4u | 79 | 79 | 0 | 0 | 123 | 0 | 0 | 0 | +| coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4 | 740 | 406 | 334 | 0 | 353 | 0 | 0 | 0 | +| axi4buf | AXI4Buffer | 204 | 66 | 138 | 0 | 15 | 0 | 0 | 0 | +| nodeIn_b_deq_q | Queue2_AXI4BundleB | 18 | 14 | 4 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_deq_q) | Queue2_AXI4BundleB | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x4 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_r_deq_q | Queue2_AXI4BundleR | 42 | 6 | 36 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_r_deq_q) | Queue2_AXI4BundleR | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x69 | 39 | 3 | 36 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_ar_deq_q | Queue2_AXI4BundleAR | 59 | 27 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_ar_deq_q) | Queue2_AXI4BundleAR | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58_376 | 55 | 23 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_aw_deq_q | Queue2_AXI4BundleAW | 47 | 15 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_aw_deq_q) | Queue2_AXI4BundleAW | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58 | 41 | 9 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue2_AXI4BundleW | 38 | 4 | 34 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_w_deq_q) | Queue2_AXI4BundleW | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x73 | 36 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | +| axi4deint | AXI4Deinterleaver | 276 | 116 | 160 | 0 | 47 | 0 | 0 | 0 | +| (axi4deint) | AXI4Deinterleaver | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | +| qs_queue_0 | Queue8_AXI4BundleR | 51 | 11 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_0) | Queue8_AXI4BundleR | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_375 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_1 | Queue8_AXI4BundleR_370 | 73 | 33 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_1) | Queue8_AXI4BundleR_370 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_374 | 67 | 27 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_2 | Queue8_AXI4BundleR_371 | 49 | 9 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_2) | Queue8_AXI4BundleR_371 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_373 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_3 | Queue8_AXI4BundleR_372 | 104 | 64 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_3) | Queue8_AXI4BundleR_372 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77 | 98 | 58 | 40 | 0 | 0 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker | 76 | 40 | 36 | 0 | 34 | 0 | 0 | 0 | +| Queue1_BundleMap | Queue1_BundleMap | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue1_BundleMap_1 | Queue1_BundleMap_359 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_369 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_360 | 11 | 5 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_368 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_361 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_361 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_367 | 9 | 3 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_362 | 12 | 6 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_362 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_366 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_363 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_363 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_365 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_364 | 9 | 3 | 6 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_364 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8 | 8 | 2 | 6 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4 | 86 | 86 | 0 | 0 | 114 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4 | 22 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW | 33 | 33 | 0 | 0 | 50 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW | 31 | 31 | 0 | 0 | 47 | 0 | 0 | 0 | +| widget | TLWidthWidget16_2 | 101 | 101 | 0 | 0 | 143 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16_2 | 45 | 45 | 0 | 0 | 48 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a31d128s3k1z3u | 56 | 56 | 0 | 0 | 95 | 0 | 0 | 0 | +| system_bus_xbar | TLXbar_sbus_i2_o3_a32d128s3k1z4c | 490 | 490 | 0 | 0 | 64 | 0 | 0 | 0 | +| tile_prci_domain | TilePRCIDomain | 43756 | 41749 | 1884 | 123 | 25900 | 27 | 8 | 117 | +| buffer | TLBuffer_a32d128s2k1z4u_1 | 1208 | 624 | 584 | 0 | 21 | 0 | 0 | 0 | +| nodeIn_b_q | Queue2_TLBundleB_a32d128s2k1z4c | 28 | 4 | 24 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_q) | Queue2_TLBundleB_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x60 | 25 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d128s2k1z4u | 101 | 5 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d128s2k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142_358 | 97 | 1 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q_1 | Queue2_TLBundleD_a32d128s2k1z4c | 158 | 62 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q_1) | Queue2_TLBundleD_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142 | 156 | 60 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d128s2k1z4u | 144 | 16 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d128s2k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189_357 | 142 | 14 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q_1 | Queue2_TLBundleA_a32d128s2k1z4c | 644 | 518 | 126 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q_1) | Queue2_TLBundleA_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189 | 641 | 515 | 126 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_c_q | Queue2_TLBundleC_a32d128s2k1z4c | 127 | 15 | 112 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_c_q) | Queue2_TLBundleC_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x173 | 125 | 13 | 112 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_e_q | Queue2_TLBundleE_a32d128s2k1z4c | 6 | 4 | 2 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_e_q) | Queue2_TLBundleE_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_sink_ext | ram_sink_2x1 | 3 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | +| element_reset_domain_bbtile | BBTile | 42551 | 41128 | 1300 | 123 | 25879 | 27 | 8 | 117 | +| (element_reset_domain_bbtile) | BBTile | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| accelerators_0 | BuckyballAccelerator | 22610 | 21977 | 510 | 123 | 15033 | 18 | 0 | 95 | +| ballDomain | BallDomain | 13143 | 12830 | 190 | 123 | 10879 | 0 | 0 | 93 | +| ballRs | BallReservationStation | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_BallReservationStation_Anon | 144 | 48 | 96 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_BallReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x281 | 141 | 45 | 96 | 0 | 0 | 0 | 0 | 0 | +| bbus | BBus | 13000 | 12783 | 94 | 123 | 10874 | 0 | 0 | 93 | +| (bbus) | BBus | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| balls_0 | GemminiBall | 13000 | 12783 | 94 | 123 | 10864 | 0 | 0 | 93 | +| (balls_0) | GemminiBall | 1 | 1 | 0 | 0 | 470 | 0 | 0 | 0 | +| convUnroller | LoopConvUnroller | 476 | 476 | 0 | 0 | 375 | 0 | 0 | 20 | +| (convUnroller) | LoopConvUnroller | 33 | 33 | 0 | 0 | 375 | 0 | 0 | 0 | +| addrGen | LoopConvAddrGen | 446 | 446 | 0 | 0 | 0 | 0 | 0 | 20 | +| exCtrl | GemminiExCtrl | 11897 | 11680 | 94 | 123 | 9717 | 0 | 0 | 64 | +| (exCtrl) | GemminiExCtrl | 1310 | 1310 | 0 | 0 | 2444 | 0 | 0 | 0 | +| mesh | MeshWithDelays | 10211 | 10082 | 6 | 123 | 7259 | 0 | 0 | 64 | +| (mesh) | MeshWithDelays | 530 | 407 | 0 | 123 | 557 | 0 | 0 | 0 | +| mesh | Mesh | 9035 | 9035 | 0 | 0 | 6098 | 0 | 0 | 64 | +| (mesh) | Mesh | 225 | 225 | 0 | 0 | 3530 | 0 | 0 | 0 | +| mesh_0_0 | Tile | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_354 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_354 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_355 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_356 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_1 | Tile_104 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_351 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_351 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_352 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_353 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_2 | Tile_105 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_348 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_348 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_349 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_350 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_3 | Tile_106 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_345 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_345 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_346 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_347 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_4 | Tile_107 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_342 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_342 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_343 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_344 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_5 | Tile_108 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_339 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_339 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_340 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_341 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_6 | Tile_109 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_336 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_336 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_337 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_338 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_7 | Tile_110 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_333 | 141 | 141 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_333 | 92 | 92 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_334 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_335 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_0 | Tile_111 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_330 | 137 | 137 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_330 | 88 | 88 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_331 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_332 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_1 | Tile_112 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_327 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_327 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_328 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_329 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_2 | Tile_113 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_324 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_324 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_325 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_326 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_3 | Tile_114 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_321 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_321 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_322 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_323 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_4 | Tile_115 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_318 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_318 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_319 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_320 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_5 | Tile_116 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_315 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_315 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_316 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_317 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_6 | Tile_117 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_312 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_312 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_313 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_314 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_7 | Tile_118 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_309 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_309 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_310 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_311 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_0 | Tile_119 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_306 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_306 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_307 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_308 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_1 | Tile_120 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_303 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_303 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_304 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_305 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_2 | Tile_121 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_300 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_300 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_301 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_302 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_3 | Tile_122 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_297 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_297 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_298 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_299 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_4 | Tile_123 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_294 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_294 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_295 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_296 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_5 | Tile_124 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_291 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_291 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_292 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_293 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_6 | Tile_125 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_288 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_288 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_289 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_290 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_7 | Tile_126 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_285 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_285 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_286 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_287 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_0 | Tile_127 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_282 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_282 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_283 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_284 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_1 | Tile_128 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_279 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_279 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_280 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_281 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_2 | Tile_129 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_276 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_276 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_277 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_278 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_3 | Tile_130 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_273 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_273 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_274 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_275 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_4 | Tile_131 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_270 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_270 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_271 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_272 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_5 | Tile_132 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_267 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_267 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_268 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_269 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_6 | Tile_133 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_264 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_264 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_265 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_266 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_7 | Tile_134 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_261 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_261 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_262 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_263 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_0 | Tile_135 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_258 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_258 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_259 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_260 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_1 | Tile_136 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_255 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_255 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_256 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_257 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_2 | Tile_137 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_252 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_252 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_253 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_254 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_3 | Tile_138 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_249 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_249 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_250 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_251 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_4 | Tile_139 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_246 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_246 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_247 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_248 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_5 | Tile_140 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_243 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_243 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_244 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_245 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_6 | Tile_141 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_240 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_240 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_241 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_242 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_7 | Tile_142 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_237 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_237 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_238 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_239 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_0 | Tile_143 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_234 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_234 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_235 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_236 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_1 | Tile_144 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_231 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_231 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_232 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_233 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_2 | Tile_145 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_228 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_228 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_229 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_230 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_3 | Tile_146 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_225 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_225 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_226 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_227 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_4 | Tile_147 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_222 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_222 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_223 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_224 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_5 | Tile_148 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_219 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_219 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_220 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_221 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_6 | Tile_149 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_216 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_216 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_217 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_218 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_7 | Tile_150 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_213 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_213 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_214 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_215 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_0 | Tile_151 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_210 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_210 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_211 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_212 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_1 | Tile_152 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_207 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_207 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_208 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_209 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_2 | Tile_153 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_204 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_204 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_205 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_206 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_3 | Tile_154 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_201 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_201 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_202 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_203 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_4 | Tile_155 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_198 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_198 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_199 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_200 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_5 | Tile_156 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_195 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_195 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_196 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_197 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_6 | Tile_157 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_192 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_192 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_193 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_194 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_7 | Tile_158 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_189 | 136 | 136 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_189 | 87 | 87 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_190 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_191 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_0 | Tile_159 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_186 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_186 | 95 | 95 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_187 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_188 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_1 | Tile_160 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_183 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_183 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_184 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_185 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_2 | Tile_161 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_180 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_180 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_181 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_182 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_3 | Tile_162 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_177 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_177 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_178 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_179 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_4 | Tile_163 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_174 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_174 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_175 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_176 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_5 | Tile_164 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_171 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_171 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_172 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_173 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_6 | Tile_165 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_168 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_168 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_169 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_170 | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_7 | Tile_166 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_167 | 145 | 145 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_167 | 96 | 96 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 1 | +| tagq | TagQueue | 106 | 106 | 0 | 0 | 75 | 0 | 0 | 0 | +| total_rows_q | Queue6_TagWithIdAndTotalRows | 30 | 24 | 6 | 0 | 7 | 0 | 0 | 0 | +| (total_rows_q) | Queue6_TagWithIdAndTotalRows | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_6x7 | 25 | 19 | 6 | 0 | 0 | 0 | 0 | 0 | +| transposer | AlwaysOutTransposer | 511 | 511 | 0 | 0 | 522 | 0 | 0 | 0 | +| (transposer) | AlwaysOutTransposer | 5 | 5 | 0 | 0 | 10 | 0 | 0 | 0 | +| pes_0_0 | PE | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_1 | PE_41 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_2 | PE_42 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_3 | PE_43 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_4 | PE_44 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_5 | PE_45 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_6 | PE_46 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_7 | PE_47 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_0 | PE_48 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_1 | PE_49 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_2 | PE_50 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_3 | PE_51 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_4 | PE_52 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_5 | PE_53 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_6 | PE_54 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_7 | PE_55 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_0 | PE_56 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_1 | PE_57 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_2 | PE_58 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_3 | PE_59 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_4 | PE_60 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_5 | PE_61 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_6 | PE_62 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_7 | PE_63 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_0 | PE_64 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_1 | PE_65 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_2 | PE_66 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_3 | PE_67 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_4 | PE_68 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_5 | PE_69 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_6 | PE_70 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_7 | PE_71 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_0 | PE_72 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_1 | PE_73 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_2 | PE_74 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_3 | PE_75 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_4 | PE_76 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_5 | PE_77 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_6 | PE_78 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_7 | PE_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_0 | PE_80 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_1 | PE_81 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_2 | PE_82 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_3 | PE_83 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_4 | PE_84 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_5 | PE_85 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_6 | PE_86 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_7 | PE_87 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_0 | PE_88 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_1 | PE_89 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_2 | PE_90 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_3 | PE_91 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_4 | PE_92 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_5 | PE_93 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_6 | PE_94 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_7 | PE_95 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_0 | PE_96 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_1 | PE_97 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_2 | PE_98 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_3 | PE_99 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_4 | PE_100 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_5 | PE_101 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_6 | PE_102 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_7 | PE_103 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | +| rdQueue0 | Queue8_SramReadResp | 305 | 261 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue0) | Queue8_SramReadResp | 100 | 100 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64_40 | 206 | 162 | 44 | 0 | 0 | 0 | 0 | 0 | +| rdQueue1 | Queue8_SramReadResp_39 | 83 | 39 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue1) | Queue8_SramReadResp_39 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64 | 46 | 2 | 44 | 0 | 0 | 0 | 0 | 0 | +| matmulUnroller | LoopMatmulUnroller | 626 | 626 | 0 | 0 | 302 | 0 | 0 | 9 | +| cmdRouter | CmdRouter | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| bankReadReqQ_q | Queue8_BuckyballAccelerator_Anon | 32 | 16 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q) | Queue8_BuckyballAccelerator_Anon | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21_38 | 26 | 10 | 16 | 0 | 0 | 0 | 0 | 0 | +| bankReadReqQ_q_1 | Queue8_BuckyballAccelerator_Anon_10 | 34 | 18 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q_1) | Queue8_BuckyballAccelerator_Anon_10 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21 | 29 | 13 | 16 | 0 | 0 | 0 | 0 | 0 | +| frontend | Frontend_1 | 5105 | 4909 | 196 | 0 | 2205 | 2 | 0 | 0 | +| boot | BootRom | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| scheduler | GlobalScheduler | 5096 | 4900 | 196 | 0 | 2199 | 2 | 0 | 0 | +| (scheduler) | GlobalScheduler | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| completeQueue | Queue16_UInt4 | 34 | 30 | 4 | 0 | 9 | 0 | 0 | 0 | +| (completeQueue) | Queue16_UInt4 | 10 | 10 | 0 | 0 | 9 | 0 | 0 | 0 | +| ram_ext | ram_16x4 | 24 | 20 | 4 | 0 | 0 | 0 | 0 | 0 | +| rob | GlobalROB | 4572 | 4572 | 0 | 0 | 1668 | 2 | 0 | 0 | +| (rob) | GlobalROB | 1439 | 1439 | 0 | 0 | 1476 | 0 | 0 | 0 | +| bat | BankAliasTable | 1006 | 1006 | 0 | 0 | 176 | 0 | 0 | 0 | +| robOperands | robOperands | 1721 | 1721 | 0 | 0 | 0 | 2 | 0 | 0 | +| robOperands_ext | robOperands_ext | 1721 | 1721 | 0 | 0 | 0 | 2 | 0 | 0 | +| scoreboard | BankScoreboard | 421 | 421 | 0 | 0 | 16 | 0 | 0 | 0 | +| subRob | SubROB | 492 | 300 | 192 | 0 | 519 | 0 | 0 | 0 | +| (subRob) | SubROB | 299 | 299 | 0 | 0 | 273 | 0 | 0 | 0 | +| sram | sram | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| sram_ext | sram_ext | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| gpDomain | GpDomain | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| completeQ | Queue1_GlobalSchedComplete | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| memDomain | MemDomain | 4300 | 4208 | 92 | 0 | 1928 | 16 | 0 | 2 | +| backend | MemBackend | 2149 | 2149 | 0 | 0 | 472 | 16 | 0 | 0 | +| privateBackend | PrivateMemBackend | 2149 | 2149 | 0 | 0 | 472 | 16 | 0 | 0 | +| (privateBackend) | PrivateMemBackend | 200 | 200 | 0 | 0 | 243 | 0 | 0 | 0 | +| accPipes_0 | AccPipe | 285 | 285 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_1 | AccPipe_11 | 265 | 265 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_2 | AccPipe_12 | 57 | 57 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_3 | AccPipe_13 | 282 | 282 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_4 | AccPipe_14 | 325 | 325 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_5 | AccPipe_15 | 508 | 508 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_6 | AccPipe_16 | 227 | 227 | 0 | 0 | 67 | 0 | 0 | 0 | +| banks_0 | SramBank | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_0) | SramBank | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_36 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_37 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_1 | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_1) | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_34 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_35 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_2 | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_2) | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_32 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_33 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_3 | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_3) | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_30 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_31 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_4 | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_4) | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_28 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_29 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_5 | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_5) | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_26 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_27 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_6 | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_6) | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_24 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_25 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_7 | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_7) | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| frontend | MemFrontend | 2117 | 2025 | 92 | 0 | 1446 | 0 | 0 | 2 | +| (frontend) | MemFrontend | 574 | 574 | 0 | 0 | 2 | 0 | 0 | 0 | +| configer | MemConfiger | 133 | 133 | 0 | 0 | 63 | 0 | 0 | 0 | +| (configer) | MemConfiger | 95 | 95 | 0 | 0 | 29 | 0 | 0 | 0 | +| zeroLines | ZeroLineGenerator | 39 | 39 | 0 | 0 | 34 | 0 | 0 | 0 | +| groupQuery | MemGroupQueryArbiter | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| (groupQuery) | MemGroupQueryArbiter | 7 | 7 | 0 | 0 | 11 | 0 | 0 | 0 | +| arbiter | RRArbiter_2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| memLoader | MemLoader | 240 | 240 | 0 | 0 | 242 | 0 | 0 | 0 | +| memRs | MemReservationStation | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_MemReservationStation_Anon | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_MemReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x158 | 161 | 69 | 92 | 0 | 0 | 0 | 0 | 0 | +| memStorer | MemStorer | 380 | 380 | 0 | 0 | 447 | 0 | 0 | 0 | +| reader | StreamReader | 542 | 542 | 0 | 0 | 304 | 0 | 0 | 2 | +| tlbCluster | BBTLBCluster | 142 | 142 | 0 | 0 | 261 | 0 | 0 | 0 | +| (tlbCluster) | BBTLBCluster | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| tlb | TLB | 142 | 142 | 0 | 0 | 259 | 0 | 0 | 0 | +| tlbArb | RRArbiter_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| writer | StreamWriter | 5 | 5 | 0 | 0 | 110 | 0 | 0 | 0 | +| midend | MemMidend | 38 | 38 | 0 | 0 | 10 | 0 | 0 | 0 | +| barrierUnit | BarrierUnit | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| buffer | TLBuffer_a32d64s1k1z4u | 127 | 49 | 78 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u_7 | 93 | 41 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s1k1z4u_7 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x77 | 90 | 38 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u_8 | 34 | 8 | 26 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116_9 | 31 | 5 | 26 | 0 | 0 | 0 | 0 | 0 | +| buffer_1 | TLBuffer_a32d64s1k1z4u_1 | 111 | 41 | 70 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u | 107 | 37 | 70 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116 | 104 | 34 | 70 | 0 | 0 | 0 | 0 | 0 | +| buffer_2 | TLBuffer_a32d64s2k1z4u | 237 | 105 | 132 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s2k1z4u | 56 | 4 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s2k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x78 | 53 | 1 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s2k1z4u | 181 | 101 | 80 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s2k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x117 | 180 | 100 | 80 | 0 | 0 | 0 | 0 | 0 | +| cores_0 | RocketBB | 5905 | 5817 | 88 | 0 | 1895 | 0 | 0 | 13 | +| (cores_0) | RocketBB | 2332 | 2332 | 0 | 0 | 753 | 0 | 0 | 0 | +| csr | CSRFile | 1828 | 1828 | 0 | 0 | 869 | 0 | 0 | 0 | +| div | MulDiv | 1530 | 1530 | 0 | 0 | 214 | 0 | 0 | 13 | +| ibuf | IBuf | 101 | 101 | 0 | 0 | 59 | 0 | 0 | 0 | +| rf_ext | rf_31x64 | 119 | 31 | 88 | 0 | 0 | 0 | 0 | 0 | +| dcache | NonBlockingDCache | 2954 | 2862 | 92 | 0 | 3330 | 9 | 0 | 0 | +| (dcache) | NonBlockingDCache | 514 | 514 | 0 | 0 | 1150 | 0 | 0 | 0 | +| data | DataArray | 192 | 192 | 0 | 0 | 2 | 8 | 0 | 0 | +| (data) | DataArray | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| array_0_0 | array_0_0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_6 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_1 | array_0_1 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_5 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_0 | array_2_0 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_4 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_1 | array_2_1 | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| dtlb | DTLB | 1147 | 1147 | 0 | 0 | 1692 | 0 | 0 | 0 | +| lfsr_prng | MaxPeriodFibonacciLFSR_3 | 12 | 12 | 0 | 0 | 16 | 0 | 0 | 0 | +| meta | L1MetadataArray | 129 | 37 | 92 | 0 | 98 | 0 | 0 | 0 | +| (meta) | L1MetadataArray | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| tag_array | tag_array | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| tag_array_ext | tag_array_ext | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| mshrs | MSHRFile | 632 | 632 | 0 | 0 | 292 | 1 | 0 | 0 | +| (mshrs) | MSHRFile | 2 | 2 | 0 | 0 | 26 | 0 | 0 | 0 | +| mmios_0 | IOMSHR | 261 | 261 | 0 | 0 | 180 | 0 | 0 | 0 | +| mshrs_0 | MSHR | 297 | 297 | 0 | 0 | 86 | 0 | 0 | 0 | +| (mshrs_0) | MSHR | 117 | 117 | 0 | 0 | 75 | 0 | 0 | 0 | +| grantackq | Queue1_TLBundleE_a32d128s1k1z4c | 72 | 72 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpq | Queue16_ReplayInternal | 109 | 109 | 0 | 0 | 9 | 0 | 0 | 0 | +| sdq_ext | sdq_17x64 | 77 | 77 | 0 | 0 | 0 | 1 | 0 | 0 | +| prober | ProbeUnit | 78 | 78 | 0 | 0 | 40 | 0 | 0 | 0 | +| wb | WritebackUnit | 256 | 256 | 0 | 0 | 40 | 0 | 0 | 0 | +| dcacheArb | HellaCacheArbiter | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | +| fpuOpts_0 | FPU | 7790 | 7526 | 264 | 0 | 2618 | 0 | 0 | 9 | +| (fpuOpts_0) | FPU | 26 | 26 | 0 | 0 | 193 | 0 | 0 | 0 | +| divSqrt | DivSqrtRecFM_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e5_s11 | 150 | 150 | 0 | 0 | 60 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e5_s11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_1 | DivSqrtRecFM_small_e8_s24 | 316 | 316 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e8_s24 | 312 | 312 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e8_s24 | 312 | 312 | 0 | 0 | 103 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e8_s24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_2 | DivSqrtRecFM_small_e11_s53 | 844 | 844 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e11_s53 | 835 | 835 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e11_s53 | 835 | 835 | 0 | 0 | 195 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e11_s53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpiu | FPToInt | 1020 | 1020 | 0 | 0 | 140 | 0 | 0 | 0 | +| (fpiu) | FPToInt | 970 | 970 | 0 | 0 | 140 | 0 | 0 | 0 | +| dcmp | CompareRecFN | 51 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpmu | FPToFP | 418 | 418 | 0 | 0 | 208 | 0 | 0 | 0 | +| (fpmu) | FPToFP | 83 | 83 | 0 | 0 | 208 | 0 | 0 | 0 | +| narrower | RecFNToRecFN | 125 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe5_os11 | 125 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | +| narrower_1 | RecFNToRecFN_1 | 215 | 215 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 | 215 | 215 | 0 | 0 | 0 | 0 | 0 | 0 | +| ifpu | IntToFP | 1520 | 1520 | 0 | 0 | 695 | 0 | 0 | 0 | +| (ifpu) | IntToFP | 61 | 61 | 0 | 0 | 140 | 0 | 0 | 0 | +| i2f_0 | PipelinedINToRecFN | 779 | 779 | 0 | 0 | 281 | 0 | 0 | 0 | +| (i2f_0) | PipelinedINToRecFN | 753 | 753 | 0 | 0 | 281 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_1 | PipelinedINToRecFN_1 | 344 | 344 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_1) | PipelinedINToRecFN_1 | 316 | 316 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_2 | PipelinedINToRecFN_2 | 342 | 342 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_2) | PipelinedINToRecFN_2 | 301 | 301 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 | 41 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | +| regfile_ext | regfile_32x65 | 1066 | 802 | 264 | 0 | 32 | 0 | 0 | 0 | +| sharedFma | FPUSharedFMAPipe | 2442 | 2442 | 0 | 0 | 992 | 0 | 0 | 9 | +| (sharedFma) | FPUSharedFMAPipe | 15 | 15 | 0 | 0 | 238 | 0 | 0 | 0 | +| fma | SharedMulAddRecFNPipe | 2428 | 2428 | 0 | 0 | 754 | 0 | 0 | 9 | +| frontend | Frontend | 2041 | 1999 | 42 | 0 | 2221 | 0 | 8 | 0 | +| (frontend) | Frontend | 3 | 3 | 0 | 0 | 90 | 0 | 0 | 0 | +| fq | ShiftQueue | 746 | 746 | 0 | 0 | 375 | 0 | 0 | 0 | +| icache | ICache | 545 | 503 | 42 | 0 | 294 | 0 | 8 | 0 | +| (icache) | ICache | 264 | 264 | 0 | 0 | 236 | 0 | 0 | 0 | +| bbtile_icache_data_arrays_0 | bbtile_icache_data_arrays_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_1 | bbtile_icache_data_arrays_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_2 | bbtile_icache_data_arrays_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_3 | bbtile_icache_data_arrays_3 | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_tag_array | bbtile_icache_tag_array | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| bbtile_icache_tag_array_ext | bbtile_icache_tag_array_ext | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| repl_way_v0_prng | MaxPeriodFibonacciLFSR | 129 | 129 | 0 | 0 | 16 | 0 | 0 | 0 | +| tlb | ITLB | 750 | 750 | 0 | 0 | 1462 | 0 | 0 | 0 | +| ptw | PTW | 678 | 678 | 0 | 0 | 567 | 0 | 0 | 0 | +| roccMemIF | SimpleHellaCacheIF | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| (roccMemIF) | SimpleHellaCacheIF | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| replayq | SimpleHellaCacheIFReplayQueue | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| (replayq) | SimpleHellaCacheIFReplayQueue | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| nackq | Queue3_UInt2 | 8 | 8 | 0 | 0 | 5 | 0 | 0 | 0 | +| tlMasterXbar | TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c | 42 | 42 | 0 | 0 | 11 | 0 | 0 | 0 | +| widget_3 | TLWidthWidget8_4 | 78 | 78 | 0 | 0 | 160 | 0 | 0 | 0 | +| (widget_3) | TLWidthWidget8_4 | 1 | 1 | 0 | 0 | 81 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleD_a32d128s2k1z4u | 77 | 77 | 0 | 0 | 79 | 0 | 0 | 0 | +| xbar | TLXbar_i2_o1_a32d64s2k1z4u | 60 | 60 | 0 | 0 | 13 | 0 | 0 | 0 | +| load_bridge | loader_axi | 41 | 41 | 0 | 0 | 306 | 0 | 0 | 0 | +| loader | ddr_uart_loader | 435 | 371 | 64 | 0 | 159 | 0 | 0 | 0 | +| normalizer | axi_fullwidth | 330 | 330 | 0 | 0 | 376 | 0 | 0 | 0 | +| peripherals | axi_scu | 147 | 99 | 48 | 0 | 162 | 0 | 0 | 0 | +| receiver | uart_rx | 37 | 37 | 0 | 0 | 31 | 0 | 0 | 0 | +| transmitter | uart_tx | 13 | 13 | 0 | 0 | 18 | 0 | 0 | 0 | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-timing.rpt new file mode 100644 index 0000000..71fe54f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-timing.rpt @@ -0,0 +1,6691 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:17 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (2) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + +btn0 +uart_txd_in + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + +ddr3_reset_n +led[0] +led[1] +led[2] +led[3] +uart_rxd_out + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.276 0.000 0 107738 0.012 0.000 0 107696 0.187 0.000 0 41738 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_pll_i {0.000 6.000} 12.000 83.333 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 8.550 0.000 0 92342 0.012 0.000 0 92342 18.750 0.000 0 35501 + fb 7.845 0.000 0 3 + ref_raw 1.756 0.000 0 130 0.122 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.974 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.843 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.842 0.000 0 1 0.336 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.051 0.000 0 44 0.090 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.574 0.000 0 48 0.094 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.423 0.000 0 4 0.413 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.245 0.000 0 36 0.092 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.439 0.000 0 4 0.408 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.597 0.000 0 36 0.086 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_pll_i 2.912 0.000 0 14674 0.027 0.000 0 14674 3.850 0.000 0 5987 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.665 0.000 0 20 +clk_pll_i ref_raw 16.907 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 10.088 0.000 0 8 45.348 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 8.404 0.000 0 8 46.023 0.000 0 8 +sync_pulse mem_refclk 1.276 0.000 0 1 0.909 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 0.095 0.000 0 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 0.095 0.000 0 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 0.095 0.000 0 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 0.095 0.000 0 15 +core_raw clk_pll_i 38.557 0.000 0 20 +ref_raw clk_pll_i 16.759 0.000 0 12 0.112 0.000 0 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 8.947 0.000 0 111 0.176 0.000 0 111 +**async_default** core_raw core_raw 20.362 0.000 0 116 0.154 0.000 0 116 +**default** clk_pll_i 1.977 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) core_raw +(none) clk_pll_i clk_pll_i +(none) core_raw clk_pll_i +(none) mem_refclk clk_pll_i +(none) ref_raw clk_pll_i +(none) core_raw +(none) clk_pll_i core_raw +(none) core_raw core_raw +(none) ref_raw +(none) clk_pll_i ref_raw +(none) ref_raw ref_raw + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) clk_pll_i +(none) fb +(none) freq_refclk +(none) pll_clkfbout +(none) ref_raw +(none) clk_pll_i + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 8.550ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.012ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.550ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 31.373ns (logic 7.987ns (25.458%) route 23.386ns (74.542%)) + Logic Levels: 35 (CARRY4=3 LUT2=6 LUT3=4 LUT4=8 LUT5=7 LUT6=7) + Clock Path Skew: -0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.360ns = ( 38.640 - 40.000 ) + Source Clock Delay (SCD): -0.857ns + Clock Pessimism Removal (CPR): 0.488ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.683 -0.857 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/clk + SLICE_X74Y126 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/C + ------------------------------------------------------------------- ------------------- + SLICE_X74Y126 FDRE (Prop_fdre_C_Q) 0.478 -0.379 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0_reg[63]/Q + net (fo=2, routed) 1.253 0.874 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/regs_1_0[63] + SLICE_X82Y128 LUT6 (Prop_lut6_I4_O) 0.296 1.170 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT6_24/O + net (fo=1, routed) 0.513 1.683 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_49 + SLICE_X81Y128 LUT5 (Prop_lut5_I4_O) 0.124 1.807 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT5_49/O + net (fo=8, routed) 1.224 3.031 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_114 + SLICE_X68Y129 LUT5 (Prop_lut5_I4_O) 0.124 3.155 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/load_wb_data[31]_i_3/O + net (fo=5, routed) 0.910 4.065 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[31] + SLICE_X59Y137 LUT4 (Prop_lut4_I3_O) 0.124 4.189 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_LUT4_25/O + net (fo=33, routed) 0.999 5.188 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/NonBlockingDCac_net_232 + SLICE_X56Y134 LUT4 (Prop_lut4_I3_O) 0.150 5.338 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/in_pipe_b_in1[47]_i_3/O + net (fo=2, routed) 1.169 6.507 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/_dcacheArb_io_requestor_1_resp_bits_data_word_bypass[47] + SLICE_X48Y156 LUT6 (Prop_lut6_I0_O) 0.348 6.855 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_2/O + net (fo=1, routed) 1.171 8.026 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_2_n_0 + SLICE_X44Y161 LUT3 (Prop_lut3_I0_O) 0.124 8.150 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/in_pipe_b_in1[47]_i_1/O + net (fo=7, routed) 1.244 9.394 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_cores_0_io_fpu_fromint_data[47] + SLICE_X39Y179 LUT4 (Prop_lut4_I3_O) 0.118 9.512 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[49]_i_9/O + net (fo=2, routed) 0.611 10.123 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[49]_i_9_n_0 + SLICE_X39Y178 LUT3 (Prop_lut3_I1_O) 0.320 10.443 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_10/O + net (fo=1, routed) 0.569 11.011 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_10_n_0 + SLICE_X41Y178 LUT6 (Prop_lut6_I2_O) 0.326 11.337 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7/O + net (fo=11, routed) 0.982 12.319 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[50]_i_7_n_0 + SLICE_X45Y174 LUT4 (Prop_lut4_I3_O) 0.150 12.469 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217/O + net (fo=3, routed) 0.591 13.060 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_217_n_0 + SLICE_X45Y178 LUT2 (Prop_lut2_I1_O) 0.332 13.392 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213/O + net (fo=5, routed) 0.590 13.982 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_213_n_0 + SLICE_X43Y178 LUT3 (Prop_lut3_I0_O) 0.124 14.106 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227/O + net (fo=3, routed) 0.815 14.921 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_227_n_0 + SLICE_X45Y178 LUT2 (Prop_lut2_I0_O) 0.150 15.071 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223/O + net (fo=3, routed) 0.564 15.635 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_223_n_0 + SLICE_X41Y177 LUT2 (Prop_lut2_I0_O) 0.332 15.967 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229/O + net (fo=2, routed) 0.277 16.244 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_229_n_0 + SLICE_X41Y177 LUT2 (Prop_lut2_I0_O) 0.124 16.368 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220/O + net (fo=5, routed) 0.666 17.034 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_220_n_0 + SLICE_X46Y180 LUT3 (Prop_lut3_I0_O) 0.124 17.158 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262/O + net (fo=3, routed) 0.602 17.759 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_262_n_0 + SLICE_X45Y180 LUT2 (Prop_lut2_I0_O) 0.149 17.908 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259/O + net (fo=3, routed) 0.668 18.576 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_259_n_0 + SLICE_X45Y180 LUT2 (Prop_lut2_I0_O) 0.332 18.908 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257/O + net (fo=4, routed) 0.579 19.487 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_257_n_0 + SLICE_X45Y177 LUT5 (Prop_lut5_I3_O) 0.124 19.611 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264/O + net (fo=4, routed) 0.604 20.215 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_264_n_0 + SLICE_X45Y181 LUT6 (Prop_lut6_I0_O) 0.124 20.339 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251/O + net (fo=1, routed) 0.626 20.965 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_251_n_0 + SLICE_X44Y181 CARRY4 (Prop_carry4_DI[0]_O[1]) + 0.407 21.372 f platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_185/O[1] + net (fo=1, routed) 0.424 21.797 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/_popc_in_T_1370[62] + SLICE_X42Y181 LUT4 (Prop_lut4_I0_O) 0.303 22.100 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135/O + net (fo=3, routed) 0.824 22.924 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_135_n_0 + SLICE_X41Y181 LUT4 (Prop_lut4_I0_O) 0.152 23.076 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_100/O + net (fo=2, routed) 0.584 23.660 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_100_n_0 + SLICE_X41Y180 LUT4 (Prop_lut4_I3_O) 0.326 23.986 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_97/O + net (fo=2, routed) 0.583 24.569 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_97_n_0 + SLICE_X40Y179 LUT6 (Prop_lut6_I5_O) 0.124 24.693 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_60/O + net (fo=2, routed) 0.837 25.530 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_60_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I4_O) 0.118 25.648 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56/O + net (fo=2, routed) 0.451 26.099 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_56_n_0 + SLICE_X41Y171 LUT5 (Prop_lut5_I3_O) 0.326 26.425 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39/O + net (fo=2, routed) 0.507 26.932 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[4]_i_39_n_0 + SLICE_X40Y171 LUT6 (Prop_lut6_I5_O) 0.124 27.056 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30/O + net (fo=1, routed) 0.000 27.056 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[2]_i_30_n_0 + SLICE_X40Y171 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 27.457 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13/CO[3] + net (fo=1, routed) 0.000 27.457 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[2]_i_13_n_0 + SLICE_X40Y172 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 27.685 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[4]_i_14/CO[2] + net (fo=2, routed) 0.583 28.268 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/alu/data5[6] + SLICE_X43Y170 LUT4 (Prop_lut4_I3_O) 0.307 28.575 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_13/O + net (fo=1, routed) 0.452 29.026 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_13_n_0 + SLICE_X46Y170 LUT6 (Prop_lut6_I3_O) 0.326 29.352 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_5/O + net (fo=1, routed) 0.423 29.775 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_5_n_0 + SLICE_X48Y169 LUT5 (Prop_lut5_I0_O) 0.124 29.899 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_2/O + net (fo=1, routed) 0.493 30.392 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_2_n_0 + SLICE_X48Y169 LUT5 (Prop_lut5_I0_O) 0.124 30.516 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata[6]_i_1/O + net (fo=1, routed) 0.000 30.516 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/_alu_io_out[6] + SLICE_X48Y169 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=35517, routed) 1.660 38.640 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/clk + SLICE_X48Y169 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6]/C + clock pessimism 0.488 39.128 + clock uncertainty -0.091 39.037 + SLICE_X48Y169 FDRE (Setup_fdre_C_D) 0.029 39.066 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/mem_reg_wdata_reg[6] + ------------------------------------------------------------------- + required time 39.066 + arrival time -30.516 + ------------------------------------------------------------------- + slack 8.550 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.012ns (arrival time - required time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.285ns (logic 0.128ns (44.914%) route 0.157ns (55.086%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.847ns + Source Clock Delay (SCD): -0.604ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.560 -0.604 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/clk + SLICE_X51Y66 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y66 FDRE (Prop_fdre_C_Q) 0.128 -0.476 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/memStorer/dma_data_reg[56]/Q + net (fo=1, routed) 0.157 -0.319 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[63]_1[56] + SLICE_X52Y67 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.826 -0.847 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/clk + SLICE_X52Y67 FDRE r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56]/C + clock pessimism 0.504 -0.343 + SLICE_X52Y67 FDRE (Hold_fdre_C_D) 0.012 -0.331 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/writer/reqReg_data_reg[56] + ------------------------------------------------------------------- + required time 0.331 + arrival time -0.319 + ------------------------------------------------------------------- + slack 0.012 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 DSP48_X0Y69 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X58Y81 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X58Y81 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_12_17/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y19 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 1.756ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.122ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.756ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 2.724ns (logic 0.716ns (26.281%) route 2.008ns (73.719%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.519ns = ( 3.481 - 5.000 ) + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): 0.560ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.605 -0.935 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y125 FDRE (Prop_fdre_C_Q) 0.419 -0.516 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, routed) 0.876 0.360 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + SLICE_X32Y131 LUT2 (Prop_lut2_I0_O) 0.297 0.657 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/arty_ddr3mig_7s_LUT2_2/O + net (fo=11, routed) 1.132 1.789 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer0__20 + SLICE_X28Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, routed) 1.162 7.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 0.249 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 1.888 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 1.979 r ref_buffer/O + net (fo=67, routed) 1.502 3.481 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X28Y138 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1]/C + clock pessimism 0.560 4.041 + clock uncertainty -0.067 3.974 + SLICE_X28Y138 FDRE (Setup_fdre_C_R) -0.429 3.545 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[1] + ------------------------------------------------------------------- + required time 3.545 + arrival time -1.789 + ------------------------------------------------------------------- + slack 1.756 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.122ns (arrival time - required time) + Source: btn_ref_meta_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: btn_ref_sync_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.240ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.468 r btn_ref_meta_reg/Q + net (fo=1, routed) 0.056 -0.412 btn_ref_meta + SLICE_X67Y74 FDRE r btn_ref_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.824 -0.849 ref_clk + SLICE_X67Y74 FDRE r btn_ref_sync_reg/C + clock pessimism 0.240 -0.609 + SLICE_X67Y74 FDRE (Hold_fdre_C_D) 0.075 -0.534 btn_ref_sync_reg + ------------------------------------------------------------------- + required time 0.534 + arrival time -0.412 + ------------------------------------------------------------------- + slack 0.122 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 XADC_X0Y0 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X67Y74 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 SLICE_X67Y74 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 BUFGCTRL_X0Y17 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.974ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.974ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.954ns (logic 0.425ns (44.547%) route 0.529ns (55.453%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.970ns = ( 12.970 - 12.000 ) + Source Clock Delay (SCD): 2.107ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.607 -0.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.484 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.657 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.450 2.107 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.532 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, routed) 0.529 3.061 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[3] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 11.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.807 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.970 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.970 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.657 + clock uncertainty -0.051 13.606 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 13.035 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.035 + arrival time -3.061 + ------------------------------------------------------------------- + slack 9.974 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.908ns + Source Clock Delay (SCD): 1.095ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 1.005 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.153 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.153 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 -0.568 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.095 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.082 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.082 + arrival time 1.153 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.843ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.843ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D2[0] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.117ns (logic 0.425ns (38.045%) route 0.692ns (61.955%)) + Logic Levels: 0 + Clock Path Skew: -0.465ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.960ns = ( 12.960 - 12.000 ) + Source Clock Delay (SCD): 2.112ns + Clock Pessimism Removal (CPR): 0.686ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.474 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.647 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.465 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y89 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q4) + 0.425 2.537 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/Q4 + net (fo=1, routed) 0.692 3.229 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d2[0] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D2[0] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 11.173 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.797 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.960 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 12.960 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.686 13.647 + clock uncertainty -0.051 13.596 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D2[0]) + -0.524 13.072 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 13.072 + arrival time -3.229 + ------------------------------------------------------------------- + slack 9.843 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.902ns + Source Clock Delay (SCD): 1.089ns + Clock Pessimism Removal (CPR): -0.187ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.191 -0.357 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.999 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.089 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, routed) 0.000 1.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 -0.574 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.902 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, routed) 0.000 0.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.187 1.089 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.076 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.076 + arrival time 1.147 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.842ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.336ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.842ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 2.196 - 3.000 ) + Source Clock Delay (SCD): -0.165ns + Clock Pessimism Removal (CPR): 0.639ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 0.457 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.471 0.928 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 2.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.639 2.835 + clock uncertainty -0.054 2.781 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.770 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.770 + arrival time -0.928 + ------------------------------------------------------------------- + slack 1.842 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.336ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.459ns (logic 0.313ns (68.192%) route 0.146ns (31.808%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.570ns + Source Clock Delay (SCD): -0.353ns + Clock Pessimism Removal (CPR): -0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.195 -0.353 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.040 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, routed) 0.146 0.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.215 -0.570 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.217 -0.353 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.230 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.230 + arrival time 0.106 + ------------------------------------------------------------------- + slack 0.336 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.051ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.090ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.051ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.681ns (logic 0.674ns (40.087%) route 1.007ns (59.913%)) + Logic Levels: 0 + Clock Path Skew: 0.412ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.119ns = ( 14.119 - 12.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, routed) 1.007 4.101 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.412 14.119 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 14.831 + clock uncertainty -0.054 14.777 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 14.152 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.152 + arrival time -4.101 + ------------------------------------------------------------------- + slack 10.051 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.090ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.179ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.840ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.179 1.840 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.003 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.022 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.022 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.090 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.574ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.574ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.396ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.093ns = ( 14.093 - 12.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.396 14.093 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 14.804 + clock uncertainty -0.054 14.750 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 14.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 14.125 + arrival time -3.551 + ------------------------------------------------------------------- + slack 10.574 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.094ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.175ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.827ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[9] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.175 1.827 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 1.992 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.011 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.011 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.094 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.423ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.413ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.423ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.400ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.698ns = ( 5.698 - 3.000 ) + Source Clock Delay (SCD): 3.046ns + Clock Pessimism Removal (CPR): 0.748ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.046 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.084 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 2.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.298 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.400 5.698 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.748 6.446 + clock uncertainty -0.054 6.392 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.507 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.507 + arrival time -4.084 + ------------------------------------------------------------------- + slack 1.423 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.413ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.176ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.419ns + Source Clock Delay (SCD): 2.371ns + Clock Pessimism Removal (CPR): -0.128ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.371 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.717 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.868 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.243 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.176 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.128 2.547 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D2) -0.093 2.454 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.454 + arrival time 2.868 + ------------------------------------------------------------------- + slack 0.413 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.245ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.245ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.483ns (logic 0.674ns (45.456%) route 0.809ns (54.544%)) + Logic Levels: 0 + Clock Path Skew: 0.407ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.114ns = ( 8.114 - 6.000 ) + Source Clock Delay (SCD): 2.419ns + Clock Pessimism Removal (CPR): 0.712ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 -0.172 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.419 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.419 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.674 3.093 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[1] + net (fo=1, routed) 0.809 3.902 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.407 8.114 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.712 8.826 + clock uncertainty -0.054 8.772 + OLOGIC_X1Y77 OSERDESE2 (Setup_oserdese2_CLKDIV_D2) + -0.625 8.147 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.147 + arrival time -3.902 + ------------------------------------------------------------------- + slack 4.245 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.092ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.177ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.838ns + Source Clock Delay (SCD): 1.824ns + Clock Pessimism Removal (CPR): -0.163ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.824 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.824 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[2] + net (fo=1, routed) 0.150 2.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.177 1.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.163 2.001 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 2.020 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.020 + arrival time 2.112 + ------------------------------------------------------------------- + slack 0.092 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.439ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.408ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.439ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.037ns (logic 0.562ns (54.177%) route 0.475ns (45.823%)) + Logic Levels: 0 + Clock Path Skew: 0.416ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.704ns = ( 5.704 - 3.000 ) + Source Clock Delay (SCD): 3.035ns + Clock Pessimism Removal (CPR): 0.747ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 3.035 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.597 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, routed) 0.475 4.073 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, routed) 1.162 5.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -1.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -0.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -0.021 r sys_buffer/O + net (fo=1, routed) 1.544 1.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 2.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 5.288 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.416 5.704 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.747 6.451 + clock uncertainty -0.054 6.397 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.512 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.512 + arrival time -4.073 + ------------------------------------------------------------------- + slack 1.439 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.408ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.346ns (69.715%) route 0.150ns (30.285%)) + Logic Levels: 0 + Clock Path Skew: 0.181ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.415ns + Source Clock Delay (SCD): 2.364ns + Clock Pessimism Removal (CPR): -0.130ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.364 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[1]) + 0.346 2.710 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[1] + net (fo=1, routed) 0.150 2.861 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[1] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.234 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, routed) 0.181 2.415 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.130 2.545 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D2) -0.093 2.452 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.452 + arrival time 2.861 + ------------------------------------------------------------------- + slack 0.408 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.597ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.597ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.142ns (logic 0.674ns (59.004%) route 0.468ns (40.996%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.116ns = ( 8.116 - 6.000 ) + Source Clock Delay (SCD): 2.408ns + Clock Pessimism Removal (CPR): 0.711ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 -0.183 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 2.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 2.408 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 2.408 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 3.082 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, routed) 0.468 3.551 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.419 8.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.711 8.827 + clock uncertainty -0.054 8.773 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 8.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 8.148 + arrival time -3.551 + ------------------------------------------------------------------- + slack 4.597 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.086ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.138ns (47.866%) route 0.150ns (52.134%)) + Logic Levels: 0 + Clock Path Skew: 0.183ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.835ns + Source Clock Delay (SCD): 1.817ns + Clock Pessimism Removal (CPR): -0.165ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.817 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[1]) + 0.138 1.955 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[1] + net (fo=1, routed) 0.150 2.105 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[5] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D2 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.183 1.835 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.165 2.000 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D2) + 0.019 2.019 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.019 + arrival time 2.105 + ------------------------------------------------------------------- + slack 0.086 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 BUFHCE_X1Y12 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 2.912ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.027ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.912ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/CE + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.395ns (logic 0.743ns (8.850%) route 7.652ns (91.150%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: -0.213ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.672ns = ( 12.672 - 12.000 ) + Source Clock Delay (SCD): 1.534ns + Clock Pessimism Removal (CPR): 0.649ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.712 1.534 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg_rep__0_0 + SLICE_X77Y88 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X77Y88 FDRE (Prop_fdre_C_Q) 0.419 1.953 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_w_channel_0/wready_reg/Q + net (fo=145, routed) 4.268 6.221 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/m_axi_wready + SLICE_X89Y110 LUT4 (Prop_lut4_I3_O) 0.324 6.545 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/goreg_dm.dout_i[144]_i_1/O + net (fo=144, routed) 3.384 9.929 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[144]_1[0] + SLICE_X71Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.500 12.672 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/m_aclk + SLICE_X71Y100 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18]/C + clock pessimism 0.649 13.322 + clock uncertainty -0.067 13.255 + SLICE_X71Y100 FDRE (Setup_fdre_C_CE) -0.413 12.842 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[18] + ------------------------------------------------------------------- + required time 12.842 + arrival time -9.929 + ------------------------------------------------------------------- + slack 2.912 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.027ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.302ns (logic 0.128ns (42.423%) route 0.174ns (57.577%)) + Logic Levels: 0 + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.192ns + Source Clock Delay (SCD): 0.136ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.560 0.136 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_count_r_reg[0]_rep_0 + SLICE_X53Y60 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X53Y60 FDRE (Prop_fdre_C_Q) 0.128 0.264 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0][4]/Q + net (fo=2, routed) 0.174 0.437 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest_reg[0]_4[4] + SLICE_X50Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.831 0.192 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/dqs_count_r_reg[0]_rep_0 + SLICE_X50Y61 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4]/C + clock pessimism 0.210 0.402 + SLICE_X50Y61 FDRE (Hold_fdre_C_D) 0.009 0.411 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/gen_final_tap[0].final_val_reg[0][4] + ------------------------------------------------------------------- + required time -0.411 + arrival time 0.437 + ------------------------------------------------------------------- + slack 0.027 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.665ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.665ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 1.065ns (logic 0.419ns (39.345%) route 0.646ns (60.655%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X59Y78 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X59Y78 FDRE (Prop_fdre_C_Q) 0.419 0.419 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.646 1.065 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X59Y79 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + SLICE_X59Y79 FDRE (Setup_fdre_C_D) -0.270 11.730 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 11.730 + arrival time -1.065 + ------------------------------------------------------------------- + slack 10.665 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 16.907ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 16.907ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 3.012ns (logic 0.456ns (15.138%) route 2.556ns (84.862%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.556 3.012 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + SLICE_X32Y125 FDRE (Setup_fdre_C_D) -0.081 19.919 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 19.919 + arrival time -3.012 + ------------------------------------------------------------------- + slack 16.907 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 10.088ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 45.348ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.088ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 6.328ns (logic 3.867ns (61.105%) route 2.461ns (38.895%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.301ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.219ns = ( 2.719 - 1.500 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.456 1.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 2.461 4.443 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUFDISABLE + V1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 7.039 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 7.039 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y85 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 7.854 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 7.854 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.576 15.683 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.307 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.412 17.719 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y85 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.327 + clock uncertainty -0.220 18.107 + ILOGIC_X1Y85 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.942 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.942 + arrival time -7.854 + ------------------------------------------------------------------- + slack 10.088 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 45.348ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.688ns (logic 1.068ns (63.257%) route 0.620ns (36.743%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.065ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.990ns + Source Clock Delay (SCD): 0.163ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.587 60.163 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.141 60.304 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 0.620 60.924 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUFDISABLE + T3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 61.608 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 61.608 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y77 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.851 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 61.851 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.217 14.432 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.812 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.178 15.990 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.227 + clock uncertainty 0.220 16.447 + ILOGIC_X1Y77 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.503 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.503 + arrival time 61.851 + ------------------------------------------------------------------- + slack 45.348 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 8.404ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 46.023ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.404ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 8.019ns (logic 3.867ns (48.222%) route 4.152ns (51.778%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 0.308ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.226ns = ( 2.726 - 1.500 ) + Source Clock Delay (SCD): 1.525ns + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.703 1.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.456 1.981 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 4.152 6.133 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUFDISABLE + M1 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.596 8.729 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 8.729 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[7] + IDELAY_X1Y97 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 9.544 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 9.544 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_8 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, routed) 1.162 19.073 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 11.749 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 13.388 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 13.479 f sys_buffer/O + net (fo=1, routed) 1.544 15.024 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 15.107 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.566 15.673 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 17.297 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.429 17.726 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y97 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.607 18.334 + clock uncertainty -0.220 18.114 + ILOGIC_X1Y97 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.949 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.949 + arrival time -9.544 + ------------------------------------------------------------------- + slack 8.404 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 46.023ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 2.362ns (logic 1.068ns (45.210%) route 1.294ns (54.790%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.064ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.989ns + Source Clock Delay (SCD): 0.163ns + Clock Pessimism Removal (CPR): -0.237ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, routed) 0.440 60.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 58.311 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 58.810 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 58.836 r sys_buffer/O + net (fo=1, routed) 0.566 59.402 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.452 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 59.846 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 59.866 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 60.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 59.051 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 59.550 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 59.576 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.587 60.163 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + SLICE_X75Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X75Y69 FDRE (Prop_fdre_C_Q) 0.141 60.304 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, routed) 1.294 61.598 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUFDISABLE + L6 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.684 62.282 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq/IBUF/O + net (fo=2, routed) 0.000 62.282 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[0] + IDELAY_X1Y88 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 62.525 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, routed) 0.000 62.525 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_1 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, routed) 0.480 15.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 12.755 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 13.298 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 13.327 r sys_buffer/O + net (fo=1, routed) 0.835 14.162 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.215 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.211 14.426 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.806 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, routed) 0.183 15.989 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.237 16.226 + clock uncertainty 0.220 16.446 + ILOGIC_X1Y88 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.502 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.502 + arrival time 62.525 + ------------------------------------------------------------------- + slack 46.023 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.276ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.909ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.276ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.589ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.804ns = ( 5.196 - 6.000 ) + Source Clock Delay (SCD): -0.786ns = ( 3.527 - 4.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, routed) 1.233 7.027 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -0.043 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 1.676 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 1.772 f sys_buffer/O + net (fo=1, routed) 1.666 3.439 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.527 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.621 4.148 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.589 5.196 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.607 5.803 + clock uncertainty -0.198 5.605 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 5.423 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 5.423 + arrival time -4.148 + ------------------------------------------------------------------- + slack 1.276 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.909ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.589ns (logic 0.000ns (0.000%) route 0.589ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.165ns + Source Clock Delay (SCD): -1.393ns = ( -0.081 - 1.312 ) + Clock Pessimism Removal (CPR): 0.607ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, routed) 1.162 3.886 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -3.438 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -1.799 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -1.708 r sys_buffer/O + net (fo=1, routed) 1.544 -0.164 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.081 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, routed) 0.589 0.508 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.621 -0.165 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.607 -0.772 + clock uncertainty 0.198 -0.574 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.400 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.400 + arrival time 0.508 + ------------------------------------------------------------------- + slack 0.909 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 13.707 - 12.000 ) + Source Clock Delay (SCD): 2.262ns = ( 11.262 - 9.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 8.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 11.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 13.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.703 14.410 + clock uncertainty -0.054 14.356 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.705 + arrival time -11.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y4 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 13.697 - 12.000 ) + Source Clock Delay (SCD): 2.251ns = ( 11.251 - 9.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, routed) 1.233 11.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 4.645 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 6.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 6.460 r sys_buffer/O + net (fo=1, routed) 1.666 8.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 8.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 8.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 11.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 11.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 11.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 13.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.702 14.399 + clock uncertainty -0.054 14.345 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.694 + arrival time -11.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y5 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.707ns = ( 7.707 - 6.000 ) + Source Clock Delay (SCD): 2.262ns = ( 5.262 - 3.000 ) + Clock Pessimism Removal (CPR): 0.703ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.614 2.828 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.262 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.600 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.582 5.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.559 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.707 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.707 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.703 8.410 + clock uncertainty -0.054 8.356 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.705 + arrival time -5.600 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.661ns + Source Clock Delay (SCD): 1.741ns + Clock Pessimism Removal (CPR): -0.168ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.741 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.913 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.913 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.218 -0.567 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.573 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.661 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.661 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.168 1.829 + OUT_FIFO_X1Y6 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.818 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time -1.818 + arrival time 1.913 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.697ns = ( 7.697 - 6.000 ) + Source Clock Delay (SCD): 2.251ns = ( 5.251 - 3.000 ) + Clock Pessimism Removal (CPR): 0.702ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 r sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 2.214 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.603 2.817 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 5.251 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.589 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 5.589 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, routed) 1.162 8.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 1.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 2.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 2.979 r sys_buffer/O + net (fo=1, routed) 1.544 4.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.572 5.179 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.549 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.697 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 7.697 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.702 8.399 + clock uncertainty -0.054 8.345 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.694 + arrival time -5.589 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.095ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.172ns (logic 0.172ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.088ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.652ns + Source Clock Delay (SCD): 1.734ns + Clock Pessimism Removal (CPR): -0.170ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.190 -0.358 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.734 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.172 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, routed) 0.000 1.906 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.209 -0.576 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.564 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.652 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, routed) 0.000 1.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.170 1.822 + OUT_FIFO_X1Y7 OUT_FIFO (Hold_out_fifo_RDCLK_RDEN) + -0.011 1.811 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time -1.811 + arrival time 1.906 + ------------------------------------------------------------------- + slack 0.095 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.557ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.557ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 1.165ns (logic 0.419ns (35.978%) route 0.746ns (64.022%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X53Y80 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X53Y80 FDRE (Prop_fdre_C_Q) 0.419 0.419 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.746 1.165 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X48Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + SLICE_X48Y80 FDRE (Setup_fdre_C_D) -0.278 39.722 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + ------------------------------------------------------------------- + required time 39.722 + arrival time -1.165 + ------------------------------------------------------------------- + slack 38.557 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 16.759ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.112ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 16.759ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 4.944ns (logic 0.456ns (9.223%) route 4.488ns (90.777%)) + Logic Levels: 0 + Clock Path Skew: 1.995ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.667ns + Source Clock Delay (SCD): -0.933ns + Clock Pessimism Removal (CPR): 0.395ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.607 -0.933 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y126 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X32Y126 FDRE (Prop_fdre_C_Q) 0.456 -0.477 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[7]/Q + net (fo=1, routed) 4.488 4.011 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[7] + SLICE_X35Y129 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 21.411 r input_clock/O + net (fo=1, routed) 1.162 22.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 15.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 16.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 16.979 r sys_buffer/O + net (fo=1, routed) 1.544 18.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 18.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 19.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 19.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 20.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 17.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 19.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 19.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.495 20.667 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X35Y129 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7]/C + clock pessimism 0.395 21.062 + clock uncertainty -0.245 20.817 + SLICE_X35Y129 FDRE (Setup_fdre_C_D) -0.047 20.770 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[7] + ------------------------------------------------------------------- + required time 20.770 + arrival time -4.011 + ------------------------------------------------------------------- + slack 16.759 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.112ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.784ns (logic 0.141ns (7.901%) route 1.643ns (92.099%)) + Logic Levels: 0 + Clock Path Skew: 1.352ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.185ns + Source Clock Delay (SCD): -0.611ns + Clock Pessimism Removal (CPR): -0.557ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.553 -0.611 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X33Y126 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y126 FDRE (Prop_fdre_C_Q) 0.141 -0.470 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[4]/Q + net (fo=1, routed) 1.643 1.173 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[4] + SLICE_X35Y127 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.823 0.185 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + SLICE_X35Y127 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4]/C + clock pessimism 0.557 0.741 + clock uncertainty 0.245 0.986 + SLICE_X35Y127 FDRE (Hold_fdre_C_D) 0.075 1.061 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[4] + ------------------------------------------------------------------- + required time -1.061 + arrival time 1.173 + ------------------------------------------------------------------- + slack 0.112 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 8.947ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.176ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 8.947ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 2.717ns (logic 0.518ns (19.068%) route 2.199ns (80.932%)) + Logic Levels: 0 + Clock Path Skew: 0.050ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.763ns = ( 12.763 - 12.000 ) + Source Clock Delay (SCD): 1.442ns + Clock Pessimism Removal (CPR): 0.729ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.620 1.442 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X58Y66 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + ------------------------------------------------------------------- ------------------- + SLICE_X58Y66 FDPE (Prop_fdpe_C_Q) 0.518 1.960 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/Q + net (fo=47, routed) 2.199 4.159 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_ctl_wren_reg_7 + SLICE_X78Y66 FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, routed) 1.162 14.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 7.249 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 8.888 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 8.979 r sys_buffer/O + net (fo=1, routed) 1.544 10.524 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.607 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 11.812 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 11.893 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 12.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 9.442 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 11.081 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.172 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.590 12.763 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X78Y66 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + clock pessimism 0.729 13.492 + clock uncertainty -0.067 13.425 + SLICE_X78Y66 FDCE (Recov_fdce_C_CLR) -0.319 13.106 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg + ------------------------------------------------------------------- + required time 13.106 + arrival time -4.159 + ------------------------------------------------------------------- + slack 8.947 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.176ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.291ns (logic 0.128ns (43.969%) route 0.163ns (56.031%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.180ns + Source Clock Delay (SCD): 0.129ns + Clock Pessimism Removal (CPR): -0.210ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.553 0.129 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X51Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y77 FDPE (Prop_fdpe_C_Q) 0.128 0.257 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, routed) 0.163 0.420 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + SLICE_X53Y77 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.819 0.180 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk + SLICE_X53Y77 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.210 0.390 + SLICE_X53Y77 FDCE (Remov_fdce_C_CLR) -0.146 0.244 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time -0.244 + arrival time 0.420 + ------------------------------------------------------------------- + slack 0.176 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 20.362ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.154ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 20.362ns (required time - arrival time) + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 19.149ns (logic 1.308ns (6.831%) route 17.841ns (93.169%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.079ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.493ns = ( 38.507 - 40.000 ) + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.487ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.825 2.294 platform/normalizer/sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.153 2.447 f platform/normalizer/axi_fullwidth_LUT4_10/O + net (fo=899, routed) 3.798 6.246 platform/loader/cpu_run_reg_inv_20 + SLICE_X85Y102 LUT2 (Prop_lut2_I0_O) 0.327 6.573 f platform/loader/in_pipe_v_i_1__0/O + net (fo=3764, routed) 11.649 18.222 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + SLICE_X10Y93 FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, routed) 1.162 42.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 35.249 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 36.888 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 36.979 r core_buffer/O + net (fo=35517, routed) 1.527 38.507 platform/chip/system/clint_domain/intsource/reg_0/clk + SLICE_X10Y93 FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1]/C + clock pessimism 0.487 38.994 + clock uncertainty -0.091 38.903 + SLICE_X10Y93 FDCE (Recov_fdce_C_CLR) -0.319 38.584 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[1] + ------------------------------------------------------------------- + required time 38.584 + arrival time -18.222 + ------------------------------------------------------------------- + slack 20.362 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.154ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.349ns (logic 0.141ns (40.345%) route 0.208ns (59.655%)) + Logic Levels: 0 + Clock Path Skew: 0.262ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): -0.607ns + Clock Pessimism Removal (CPR): -0.504ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.557 -0.607 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/s_aclk + SLICE_X51Y80 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X51Y80 FDPE (Prop_fdpe_C_Q) 0.141 -0.466 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.sckt_wr_rst_ic_reg/Q + net (fo=15, routed) 0.208 -0.258 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0] + SLICE_X54Y80 FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.824 -0.849 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_aclk + SLICE_X54Y80 FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C + clock pessimism 0.504 -0.345 + SLICE_X54Y80 FDCE (Remov_fdce_C_CLR) -0.067 -0.412 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1] + ------------------------------------------------------------------- + required time 0.412 + arrival time -0.258 + ------------------------------------------------------------------- + slack 0.154 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 1.977ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.977ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 3.023ns (logic 0.456ns (15.083%) route 2.567ns (84.917%)) + Logic Levels: 0 + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.456 0.456 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 2.567 3.023 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -3.023 + ------------------------------------------------------------------- + slack 1.977 + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + (rising edge-triggered cell FDCE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr3_reset_n + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 5.748ns (logic 2.163ns (37.622%) route 3.586ns (62.378%)) + Logic Levels: 2 (LUT2=1 OBUF=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.711 1.533 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X78Y66 FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y66 FDCE (Prop_fdce_C_Q) 0.518 2.051 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/Q + net (fo=1, routed) 0.961 3.012 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n + SLICE_X87Y66 LUT2 (Prop_lut2_I1_O) 0.124 3.136 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/gen_reset_obuf.u_reset_obuf_i_1/O + net (fo=1, routed) 2.625 5.761 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/mux_reset_n + K6 OBUF (Prop_obuf_I_O) 1.521 7.282 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_reset_obuf.u_reset_obuf/O + net (fo=0) 0.000 7.282 ddr3_reset_n + K6 r ddr3_reset_n (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.376ns (logic 0.141ns (10.246%) route 1.235ns (89.754%)) + Logic Levels: 0 + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X69Y117 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.235 1.510 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: platform/loader/cpu_run_reg_inv/C + (rising edge-triggered cell FDSE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 12.328ns (logic 4.784ns (38.808%) route 7.544ns (61.192%)) + Logic Levels: 2 (LUT5=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.721 -0.819 platform/loader/clk + SLICE_X78Y96 FDSE r platform/loader/cpu_run_reg_inv/C + ------------------------------------------------------------------- ------------------- + SLICE_X78Y96 FDSE (Prop_fdse_C_Q) 0.478 -0.341 f platform/loader/cpu_run_reg_inv/Q + net (fo=264, routed) 3.176 2.835 platform/loader/rx_valid1 + SLICE_X69Y78 LUT5 (Prop_lut5_I4_O) 0.295 3.130 r platform/loader/led_OBUF[2]_inst_i_1/O + net (fo=1, routed) 4.368 7.498 led_OBUF[2] + T9 OBUF (Prop_obuf_I_O) 4.011 11.509 r led_OBUF[2]_inst/O + net (fo=0) 0.000 11.509 led[2] + T9 r led[2] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: platform/peripherals/exit_code_reg[19]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: led[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.331ns (logic 2.205ns (66.189%) route 1.126ns (33.811%)) + Logic Levels: 3 (LUT5=1 LUT6=1 OBUF=1) + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.559 -0.605 platform/peripherals/clk + SLICE_X54Y101 FDRE r platform/peripherals/exit_code_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X54Y101 FDRE (Prop_fdre_C_Q) 0.164 -0.441 r platform/peripherals/exit_code_reg[19]/Q + net (fo=2, routed) 0.094 -0.347 platform/peripherals/exit_code[19] + SLICE_X55Y101 LUT6 (Prop_lut6_I3_O) 0.045 -0.302 r platform/peripherals/led_OBUF[1]_inst_i_4/O + net (fo=1, routed) 0.082 -0.220 platform/peripherals/led_OBUF[1]_inst_i_4_n_0 + SLICE_X55Y101 LUT5 (Prop_lut5_I2_O) 0.045 -0.175 r platform/peripherals/led_OBUF[1]_inst_i_1/O + net (fo=1, routed) 0.950 0.775 led_OBUF[1] + J5 OBUF (Prop_obuf_I_O) 1.951 2.726 r led_OBUF[1]_inst/O + net (fo=0) 0.000 2.726 led[1] + J5 r led[1] (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: clk_pll_i + +Max Delay 13 Endpoints +Min Delay 13 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.076ns (logic 0.711ns (17.445%) route 3.365ns (82.555%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.670ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): 1.436ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.419 1.855 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.267 2.122 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.292 2.414 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.098 5.512 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 0.744ns (logic 0.232ns (31.172%) route 0.512ns (68.828%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.049ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.181ns + Source Clock Delay (SCD): 0.132ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.556 0.132 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.128 0.260 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.086 0.345 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.104 0.449 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.427 0.876 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X51Y77 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.820 0.181 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X51Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: clk_pll_i + +Max Delay 235 Endpoints +Min Delay 255 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 7.211ns (logic 1.308ns (18.138%) route 5.903ns (81.862%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: 1.693ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.766ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.440 1.910 sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.119 2.029 r memory_cdc_i_1/O + net (fo=1, routed) 0.797 2.826 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.361 3.187 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 3.098 6.285 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/src_arst + SLICE_X89Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.594 0.766 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + SLICE_X89Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.586ns (logic 0.337ns (57.552%) route 0.249ns (42.448%)) + Logic Levels: 0 + Clock Path Skew: 2.961ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.453ns + Source Clock Delay (SCD): -1.508ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.247ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.117ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.512 -1.508 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_clk + SLICE_X68Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y94 FDRE (Prop_fdre_C_Q) 0.337 -1.171 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.249 -0.923 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.631 1.453 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_clk + SLICE_X69Y94 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: mem_refclk + To Clock: clk_pll_i + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 1.754ns (logic 0.402ns (22.913%) route 1.352ns (77.087%)) + Logic Levels: 0 + Clock Path Skew: 0.947ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.758ns + Source Clock Delay (SCD): -0.189ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.597 -0.189 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.402 0.213 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 1.352 1.566 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[1] + SLICE_X81Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.585 0.758 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X81Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[3]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + (rising edge-triggered cell PHASER_IN_PHY clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.546ns (logic 0.204ns (37.365%) route 0.342ns (62.635%)) + Logic Levels: 0 + Clock Path Skew: 0.574ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.223ns + Source Clock Delay (SCD): -0.351ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, routed) 0.197 -0.351 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_MEMREFCLK_DQSFOUND) + 0.204 -0.147 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/DQSFOUND + net (fo=1, routed) 0.342 0.195 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes[0] + SLICE_X89Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.862 0.223 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg_0 + SLICE_X89Y73 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/pi_dqs_found_lanes_r1_reg[2]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: clk_pll_i + +Max Delay 32 Endpoints +Min Delay 32 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.619ns (logic 0.779ns (11.769%) route 5.840ns (88.231%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 1.586ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.659ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.478 -0.449 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.326 0.877 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT4 (Prop_lut4_I2_O) 0.301 1.178 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.514 5.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X51Y119 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.659 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X51Y119 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.567ns (logic 0.247ns (15.765%) route 1.320ns (84.235%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.847ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.238ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.148 -0.461 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.601 0.140 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT4 (Prop_lut4_I2_O) 0.099 0.239 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 0.719 0.957 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X83Y97 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.877 0.238 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X83Y97 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r_reg[9]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: core_raw + +Max Delay 2 Endpoints +Min Delay 2 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.988ns (logic 1.487ns (18.620%) route 6.501ns (81.380%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.522ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.522ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.186ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.501 7.988 btn0_IBUF + SLICE_X67Y77 FDRE r btn_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.498 -1.522 clk + SLICE_X67Y77 FDRE r btn_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: uart_txd_in + (input port) + Destination: platform/receiver/rx_meta_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.930ns (logic 0.294ns (15.218%) route 1.637ns (84.782%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.838ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.838ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + A9 0.000 0.000 r uart_txd_in (IN) + net (fo=0) 0.000 0.000 uart_txd_in + A9 IBUF (Prop_ibuf_I_O) 0.294 0.294 r uart_txd_in_IBUF_inst/O + net (fo=1, routed) 1.637 1.930 platform/receiver/rx + SLICE_X39Y102 FDRE r platform/receiver/rx_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.835 -0.838 platform/receiver/clk + SLICE_X39Y102 FDRE r platform/receiver/rx_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: core_raw + +Max Delay 157 Endpoints +Min Delay 177 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ui_reset_pipe_reg[2]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 3.789ns (logic 0.711ns (18.764%) route 3.078ns (81.236%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -2.866ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): 1.436ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -4.355 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -2.636 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -2.540 r sys_buffer/O + net (fo=1, routed) 1.666 -0.874 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -0.786 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 0.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 0.622 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 1.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 -1.993 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 -0.274 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 -0.178 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.614 1.436 ui_clk + SLICE_X65Y77 FDPE r ui_reset_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X65Y77 FDPE (Prop_fdpe_C_Q) 0.419 1.855 f ui_reset_pipe_reg[2]/Q + net (fo=2, routed) 0.267 2.122 memory_cdc/inst/m_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I1_O) 0.292 2.414 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.812 5.225 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.238ns (logic 0.128ns (53.830%) route 0.110ns (46.170%)) + Logic Levels: 0 + Clock Path Skew: -0.978ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.847ns + Source Clock Delay (SCD): 0.131ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.255ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.555 0.131 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_clk + SLICE_X57Y80 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X57Y80 FDRE (Prop_fdre_C_Q) 0.128 0.259 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.110 0.369 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.826 -0.847 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_clk + SLICE_X57Y81 FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: core_raw + To Clock: core_raw + +Max Delay 10 Endpoints +Min Delay 10 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: reset_count_reg[2]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.925ns (logic 1.308ns (18.888%) route 5.617ns (81.112%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.503ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.430ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.070 -4.355 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.719 -2.636 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -2.540 r core_buffer/O + net (fo=35517, routed) 1.613 -0.927 clk + SLICE_X68Y74 FDRE r reset_count_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X68Y74 FDRE (Prop_fdre_C_Q) 0.456 -0.471 r reset_count_reg[2]/Q + net (fo=2, routed) 0.843 0.372 platform/normalizer/reset_count_reg[2] + SLICE_X69Y76 LUT6 (Prop_lut6_I3_O) 0.124 0.496 r platform/normalizer/axi_fullwidth_LUT6_1/O + net (fo=1, routed) 0.292 0.789 platform/normalizer/axi_fullwidth_net_1 + SLICE_X69Y77 LUT5 (Prop_lut5_I4_O) 0.124 0.913 r platform/normalizer/axi_fullwidth_LUT5_1/O + net (fo=1, routed) 0.433 1.346 platform/normalizer/axi_fullwidth_net_3 + SLICE_X69Y77 LUT4 (Prop_lut4_I3_O) 0.124 1.470 f platform/normalizer/axi_fullwidth_LUT4_9/O + net (fo=21, routed) 0.440 1.910 sel + SLICE_X69Y78 LUT4 (Prop_lut4_I3_O) 0.119 2.029 r memory_cdc_i_1/O + net (fo=1, routed) 0.797 2.826 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.361 3.187 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 2.812 5.998 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X87Y113 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.324 -4.751 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 1.639 -3.112 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.021 r core_buffer/O + net (fo=35517, routed) 1.591 -1.430 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X87Y113 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: lock_sync_reg[2]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.285ns (logic 0.293ns (22.796%) route 0.992ns (77.204%)) + Logic Levels: 2 (LUT2=1 LUT4=1) + Clock Path Skew: -0.245ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.851ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.379 -1.689 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.499 -1.190 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.164 r core_buffer/O + net (fo=35517, routed) 0.558 -0.606 clk + SLICE_X63Y78 FDPE r lock_sync_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X63Y78 FDPE (Prop_fdpe_C_Q) 0.141 -0.465 f lock_sync_reg[2]/Q + net (fo=4, routed) 0.287 -0.179 lock_sync[2] + SLICE_X69Y78 LUT4 (Prop_lut4_I1_O) 0.043 -0.136 r memory_cdc_i_1/O + net (fo=1, routed) 0.279 0.143 memory_cdc/inst/s_axi_aresetn + SLICE_X65Y77 LUT2 (Prop_lut2_I0_O) 0.109 0.252 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1/O + net (fo=20, routed) 0.427 0.679 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst + SLICE_X50Y77 FDPE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -3.163 -2.245 r clock_mmcm/CLKOUT0 + net (fo=1, routed) 0.544 -1.702 core_raw + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.673 r core_buffer/O + net (fo=35517, routed) 0.822 -0.851 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk + SLICE_X50Y77 FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: ref_raw + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.119ns (logic 1.487ns (18.320%) route 6.632ns (81.680%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -1.525ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.525ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 1.487 1.487 r btn0_IBUF_inst/O + net (fo=2, routed) 6.632 8.119 btn0_IBUF + SLICE_X67Y74 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.495 -1.525 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: btn0 + (input port) + Destination: btn_ref_meta_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.179ns (logic 0.255ns (8.026%) route 2.924ns (91.974%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.849ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.849ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + D9 0.000 0.000 r btn0 (IN) + net (fo=0) 0.000 0.000 btn0 + D9 IBUF (Prop_ibuf_I_O) 0.255 0.255 r btn0_IBUF_inst/O + net (fo=2, routed) 2.924 3.179 btn0_IBUF + SLICE_X67Y74 FDRE r btn_ref_meta_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.824 -0.849 ref_clk + SLICE_X67Y74 FDRE r btn_ref_meta_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: ref_raw + +Max Delay 0 Endpoints +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.213ns (logic 0.141ns (11.621%) route 1.072ns (88.379%)) + Logic Levels: 0 + Clock Path Skew: -0.987ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.853ns + Source Clock Delay (SCD): 0.134ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.231ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.164ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.558 0.134 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X69Y117 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y117 FDPE (Prop_fdpe_C_Q) 0.141 0.275 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=50, routed) 1.072 1.347 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.820 -0.853 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + SLICE_X32Y125 FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: ref_raw + +Max Delay 15 Endpoints +Min Delay 15 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/PRE + (recovery check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 4.125ns (logic 0.808ns (19.586%) route 3.317ns (80.414%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.481ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.408ns + Source Clock Delay (SCD): -0.927ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, routed) 1.233 2.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.070 -4.355 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.719 -2.636 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r ref_buffer/O + net (fo=67, routed) 1.613 -0.927 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.478 -0.449 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 1.326 0.877 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT1 (Prop_lut1_I0_O) 0.330 1.207 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 1.992 3.199 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X89Y53 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.612 -1.408 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X89Y53 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][11]/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: mig_resetn_pipe_reg[2]/C + (rising edge-triggered cell FDCE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/PRE + (removal check against rising-edge clock ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 1.482ns (logic 0.244ns (16.461%) route 1.238ns (83.539%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.184ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.793ns + Source Clock Delay (SCD): -0.609ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + Timing Exception: False Path + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.379 -1.689 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.499 -1.190 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r ref_buffer/O + net (fo=67, routed) 0.555 -0.609 ref_clk + SLICE_X70Y75 FDCE r mig_resetn_pipe_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X70Y75 FDCE (Prop_fdce_C_Q) 0.148 -0.461 r mig_resetn_pipe_reg[2]/Q + net (fo=2, routed) 0.601 0.140 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/sys_rst_i + SLICE_X89Y75 LUT1 (Prop_lut1_I0_O) 0.096 0.236 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/plle2_i_i_1/O + net (fo=16, routed) 0.637 0.873 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/AS[0] + SLICE_X89Y50 FDPE f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/PRE + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 -2.245 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 -1.702 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r ref_buffer/O + net (fo=67, routed) 0.880 -0.793 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + SLICE_X89Y50 FDPE r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rst_ref_sync_r_reg[0][0]/C + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: clk_pll_i + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 3.457ns (logic 0.096ns (2.777%) route 3.361ns (97.223%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i fall edge) + 6.000 6.000 f + E3 0.000 6.000 f CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 7.482 f input_clock/O + net (fo=1, routed) 1.233 8.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 1.645 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 3.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 3.460 f sys_buffer/O + net (fo=1, routed) 1.666 5.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 5.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.281 6.495 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.127 6.622 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.841 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.457 4.007 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.719 5.726 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.096 5.822 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.641 7.463 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + (clock source 'clk_pll_i' {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 1.084ns (logic 0.026ns (2.400%) route 1.058ns (97.600%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, routed) 0.440 0.690 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.379 -1.689 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.499 -1.190 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.164 r sys_buffer/O + net (fo=1, routed) 0.566 -0.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.548 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.394 -0.154 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.020 -0.134 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.269 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.083 -0.949 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.499 -0.450 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -0.424 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.559 0.135 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + MMCME2_ADV_X1Y1 MMCME2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: fb + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb fall edge) 5.000 5.000 f + E3 0.000 5.000 f CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 5.438 f input_clock/O + net (fo=1, routed) 0.480 5.918 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.163 2.755 f clock_mmcm/CLKFBOUT + net (fo=1, routed) 0.544 3.298 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 3.327 f fb_buffer/O + net (fo=1, routed) 0.824 4.151 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV f clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKFBOUT + (clock source 'fb' {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: clock_mmcm/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.236ns (logic 0.091ns (2.812%) route 3.145ns (97.188%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.147ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock fb rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -7.324 -4.751 r clock_mmcm/CLKFBOUT + net (fo=1, routed) 1.639 -3.112 fb + BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.021 r fb_buffer/O + net (fo=1, routed) 1.506 -1.515 fb_buf + MMCME2_ADV_X1Y2 MMCME2_ADV r clock_mmcm/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: freq_refclk + To Clock: + +Max Delay 5 Endpoints +Min Delay 5 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.647ns (logic 0.000ns (0.000%) route 0.647ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk fall edge) + 0.750 0.750 f + E3 0.000 0.750 f CLK100MHZ (IN) + net (fo=0) 0.000 0.750 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 2.232 f input_clock/O + net (fo=1, routed) 1.233 3.465 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -3.605 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 -1.886 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -1.790 f sys_buffer/O + net (fo=1, routed) 1.666 -0.124 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -0.036 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.647 0.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/freq_refclk + PHASER_REF_X1Y1 PHASER_REF f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + (clock source 'freq_refclk' {rise@0.000ns fall@0.750ns period=1.500ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.572ns (logic 0.000ns (0.000%) route 0.572ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.123ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.071ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock freq_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, routed) 0.572 -0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/FREQREFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: pll_clkfbout + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 0.014ns (logic 0.000ns (0.000%) route 0.014ns (100.001%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout fall edge) + 3.000 3.000 f + E3 0.000 3.000 f CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 f input_clock/O + net (fo=1, routed) 1.233 5.715 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.070 -1.355 f clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.719 0.364 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 0.460 f sys_buffer/O + net (fo=1, routed) 1.666 2.126 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.088 2.214 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.014 2.228 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + (clock source 'pll_clkfbout' {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 0.013ns (logic 0.000ns (0.000%) route 0.013ns (100.000%)) + Logic Levels: 0 + Clock Uncertainty: 0.120ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.062ns + Phase Error (PE): 0.080ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock pll_clkfbout rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT + net (fo=1, routed) 0.013 -1.380 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clkfbout + PLLE2_ADV_X1Y1 PLLE2_ADV r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: ref_raw + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Max at Fast Process Corner + Data Path Delay: 1.340ns (logic 0.029ns (2.164%) route 1.311ns (97.836%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw fall edge) 2.500 2.500 f + E3 0.000 2.500 f CLK100MHZ (IN) + net (fo=0) 0.000 2.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 2.938 f input_clock/O + net (fo=1, routed) 0.480 3.418 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -3.163 0.255 f clock_mmcm/CLKOUT2 + net (fo=1, routed) 0.544 0.798 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.827 f ref_buffer/O + net (fo=67, routed) 0.768 1.595 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: clock_mmcm/CLKOUT2 + (clock source 'ref_raw' {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + Path Group: (none) + Path Type: Min at Slow Process Corner + Data Path Delay: 3.031ns (logic 0.091ns (3.003%) route 2.940ns (96.997%)) + Logic Levels: 1 (BUFG=1) + Clock Uncertainty: 0.160ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.099ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -7.324 -4.751 r clock_mmcm/CLKOUT2 + net (fo=1, routed) 1.639 -3.112 ref_raw + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r ref_buffer/O + net (fo=67, routed) 1.300 -1.720 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/clk_ref_i + IDELAYCTRL_X1Y1 IDELAYCTRL r ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK + ------------------------------------------------------------------- ------------------- + + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: clk_pll_i + +Max Delay 33 Endpoints +Min Delay 33 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Slow Process Corner) + Data Path Delay: 6.581ns (logic 0.124ns (1.884%) route 6.457ns (98.116%)) + Logic Levels: 1 (LUT4=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + MMCME2_ADV_X1Y1 MMCME2_ADV 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/LOCKED + net (fo=3, routed) 1.943 1.943 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r_reg[11] + SLICE_X89Y75 LUT4 (Prop_lut4_I0_O) 0.124 2.067 f ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/rstdiv2_sync_r[11]_i_1/O + net (fo=32, routed) 4.514 6.581 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_tmp + SLICE_X51Y119 FDPE f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, routed) 1.162 2.573 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -7.324 -4.751 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 1.639 -3.112 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r sys_buffer/O + net (fo=1, routed) 1.544 -1.476 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 -1.393 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 1.205 -0.188 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.081 -0.107 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.799 0.692 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -3.249 -2.558 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 1.639 -0.919 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 -0.828 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 1.487 0.659 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + SLICE_X51Y119 FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__11/C + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + (internal pin) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 0.723ns (logic 0.045ns (6.224%) route 0.678ns (93.776%)) + Logic Levels: 1 (LUT2=1) + Clock Uncertainty: 0.193ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.132ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/PHASELOCKED + net (fo=1, routed) 0.317 0.317 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in_n_6 + SLICE_X89Y75 LUT2 (Prop_lut2_I0_O) 0.045 0.362 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/pi_phase_locked_all_inferred_i_1/O + net (fo=1, routed) 0.361 0.723 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/in0 + SLICE_X81Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, routed) 0.480 0.918 clk_in + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -3.163 -2.245 r clock_mmcm/CLKOUT1 + net (fo=1, routed) 0.544 -1.702 sys_raw + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.673 r sys_buffer/O + net (fo=1, routed) 0.835 -0.838 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.785 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, routed) 0.437 -0.348 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFHCE_X1Y12 BUFH (Prop_bufh_I_O) 0.043 -0.305 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, routed) 0.494 0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.400 -1.211 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, routed) 0.544 -0.668 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -0.639 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=5985, routed) 0.862 0.223 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + SLICE_X81Y69 FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pi_phase_locked_all_r1_reg/C + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-utilization.rpt new file mode 100644 index 0000000..a543491 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/routed-utilization.rpt @@ -0,0 +1,264 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:36:07 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs | 53929 | 0 | 0 | 63400 | 85.06 | +| LUT as Logic | 50007 | 0 | 0 | 63400 | 78.88 | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| LUT as Shift Register | 278 | 0 | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Flip Flop | 33943 | 0 | 0 | 126800 | 26.77 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 163 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 562 | Yes | Set | - | +| 33078 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +| Slice | 15579 | 0 | 0 | 15850 | 98.29 | +| SLICEL | 10888 | 0 | | | | +| SLICEM | 4691 | 0 | | | | +| LUT as Logic | 50007 | 0 | 0 | 63400 | 78.88 | +| using O5 output only | 31 | | | | | +| using O6 output only | 37318 | | | | | +| using O5 and O6 | 12658 | | | | | +| LUT as Memory | 3922 | 0 | 0 | 19000 | 20.64 | +| LUT as Distributed RAM | 3644 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 260 | | | | | +| using O5 and O6 | 3384 | | | | | +| LUT as Shift Register | 278 | 0 | | | | +| using O5 output only | 17 | | | | | +| using O6 output only | 160 | | | | | +| using O5 and O6 | 101 | | | | | +| Slice Registers | 33943 | 0 | 0 | 126800 | 26.77 | +| Register driven from within the Slice | 15009 | | | | | +| Register driven from outside the Slice | 18934 | | | | | +| LUT in front of the register is unused | 4958 | | | | | +| LUT in front of the register is used | 13976 | | | | | +| Unique Control Sets | 1256 | | 0 | 15850 | 7.92 | ++--------------------------------------------+-------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 60 | 60 | 0 | 210 | 28.57 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 28 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +8. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33078 | Flop & Latch | +| LUT6 | 20391 | LUT | +| LUT3 | 13504 | LUT | +| LUT5 | 12689 | LUT | +| LUT4 | 10385 | LUT | +| RAMD32 | 5100 | Distributed Memory | +| LUT2 | 4885 | LUT | +| CARRY4 | 2073 | CarryLogic | +| RAMS32 | 1774 | Distributed Memory | +| LUT1 | 811 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 562 | Flop & Latch | +| SRL16E | 246 | Distributed Memory | +| FDPE | 163 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 133 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| ODDR | 5 | IO | +| BUFG | 5 | Clock | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| INV | 3 | LUT | +| IBUF | 3 | IO | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-hierarchy.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-hierarchy.rpt new file mode 100644 index 0000000..84b4c82 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-hierarchy.rpt @@ -0,0 +1,1157 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:30:49 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -hierarchical -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synth-hierarchy.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| toy_a7_top | (top) | 57555 | 53496 | 3680 | 379 | 34174 | 27 | 8 | 117 | +| (toy_a7_top) | (top) | 7 | 7 | 0 | 0 | 65 | 0 | 0 | 0 | +| ddr_controller | arty_ddr3 | 5052 | 4446 | 452 | 154 | 4193 | 0 | 0 | 0 | +| (ddr_controller) | arty_ddr3 | 216 | 0 | 216 | 0 | 0 | 0 | 0 | 0 | +| u_arty_ddr3_mig | arty_ddr3_mig | 4836 | 4446 | 236 | 154 | 4193 | 0 | 0 | 0 | +| temp_mon_enabled.u_tempmon | arty_ddr3mig_7series_v4_2_tempmon | 39 | 39 | 0 | 0 | 122 | 0 | 0 | 0 | +| u_ddr3_clk_ibuf | arty_ddr3mig_7series_v4_2_clk_ibuf | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr3_infrastructure | arty_ddr3mig_7series_v4_2_infrastructure | 27 | 27 | 0 | 0 | 58 | 0 | 0 | 0 | +| u_iodelay_ctrl | arty_ddr3mig_7series_v4_2_iodelay_ctrl | 2 | 2 | 0 | 0 | 15 | 0 | 0 | 0 | +| u_memc_ui_top_axi | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 4768 | 4378 | 236 | 154 | 3998 | 0 | 0 | 0 | +| (u_memc_ui_top_axi) | arty_ddr3mig_7series_v4_2_memc_ui_top_axi | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem_intfc0 | arty_ddr3mig_7series_v4_2_mem_intfc | 3681 | 3624 | 40 | 17 | 2902 | 0 | 0 | 0 | +| ddr_phy_top0 | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3047 | 2999 | 32 | 16 | 2370 | 0 | 0 | 0 | +| (ddr_phy_top0) | arty_ddr3mig_7series_v4_2_ddr_phy_top | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_ddr_calib_top | arty_ddr3mig_7series_v4_2_ddr_calib_top | 2376 | 2362 | 0 | 14 | 1986 | 0 | 0 | 0 | +| (u_ddr_calib_top) | arty_ddr3mig_7series_v4_2_ddr_calib_top | 107 | 106 | 0 | 1 | 29 | 0 | 0 | 0 | +| ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl | arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl | 543 | 543 | 0 | 0 | 872 | 0 | 0 | 0 | +| ddr_phy_tempmon_0 | arty_ddr3mig_7series_v4_2_ddr_phy_tempmon | 258 | 258 | 0 | 0 | 229 | 0 | 0 | 0 | +| dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr | arty_ddr3mig_7series_v4_2_ddr_phy_dqs_found_cal_hr | 150 | 149 | 0 | 1 | 97 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay | arty_ddr3mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay | 17 | 16 | 0 | 1 | 16 | 0 | 0 | 0 | +| mb_wrlvl_inst.u_ddr_phy_wrlvl | arty_ddr3mig_7series_v4_2_ddr_phy_wrlvl | 266 | 265 | 0 | 1 | 160 | 0 | 0 | 0 | +| u_ddr_phy_init | arty_ddr3mig_7series_v4_2_ddr_phy_init | 872 | 868 | 0 | 4 | 279 | 0 | 0 | 0 | +| u_ddr_phy_wrcal | arty_ddr3mig_7series_v4_2_ddr_phy_wrcal | 163 | 157 | 0 | 6 | 304 | 0 | 0 | 0 | +| u_ddr_mc_phy_wrapper | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 668 | 634 | 32 | 2 | 384 | 0 | 0 | 0 | +| (u_ddr_mc_phy_wrapper) | arty_ddr3mig_7series_v4_2_ddr_mc_phy_wrapper | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_0 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_1 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized0 | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| genblk24.phy_ctl_pre_fifo_2 | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_9 | 33 | 33 | 0 | 0 | 21 | 0 | 0 | 0 | +| u_ddr_mc_phy | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 569 | 535 | 32 | 2 | 297 | 0 | 0 | 0 | +| (u_ddr_mc_phy) | arty_ddr3mig_7series_v4_2_ddr_mc_phy | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| ddr_phy_4lanes_0.u_ddr_phy_4lanes | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 569 | 535 | 32 | 2 | 281 | 0 | 0 | 0 | +| (ddr_phy_4lanes_0.u_ddr_phy_4lanes) | arty_ddr3mig_7series_v4_2_ddr_phy_4lanes | 10 | 9 | 0 | 1 | 20 | 0 | 0 | 0 | +| ddr_byte_lane_A.ddr_byte_lane_A | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 55 | 23 | 32 | 0 | 20 | 0 | 0 | 0 | +| (ddr_byte_lane_A.ddr_byte_lane_A) | arty_ddr3mig_7series_v4_2_ddr_byte_lane | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_14 | 54 | 22 | 32 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_B.ddr_byte_lane_B | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 25 | 25 | 0 | 0 | 19 | 0 | 0 | 0 | +| (ddr_byte_lane_B.ddr_byte_lane_B) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized0 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_13 | 16 | 16 | 0 | 0 | 19 | 0 | 0 | 0 | +| ddr_byte_lane_C.ddr_byte_lane_C | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 241 | 241 | 0 | 0 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_C.ddr_byte_lane_C) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized1 | 7 | 7 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo_11 | 212 | 212 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_12 | 22 | 22 | 0 | 0 | 24 | 0 | 0 | 0 | +| ddr_byte_lane_D.ddr_byte_lane_D | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 238 | 237 | 0 | 1 | 111 | 0 | 0 | 0 | +| (ddr_byte_lane_D.ddr_byte_lane_D) | arty_ddr3mig_7series_v4_2_ddr_byte_lane__parameterized2 | 0 | 0 | 0 | 0 | 69 | 0 | 0 | 0 | +| ddr_byte_group_io | arty_ddr3mig_7series_v4_2_ddr_byte_group_io__parameterized1 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | +| dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo | arty_ddr3mig_7series_v4_2_ddr_if_post_fifo | 215 | 215 | 0 | 0 | 17 | 0 | 0 | 0 | +| of_pre_fifo_gen.u_ddr_of_pre_fifo | arty_ddr3mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 | 21 | 21 | 0 | 0 | 24 | 0 | 0 | 0 | +| mc0 | arty_ddr3mig_7series_v4_2_mc | 634 | 625 | 8 | 1 | 532 | 0 | 0 | 0 | +| (mc0) | arty_ddr3mig_7series_v4_2_mc | 8 | 8 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_mach0 | arty_ddr3mig_7series_v4_2_bank_mach | 508 | 508 | 0 | 0 | 362 | 0 | 0 | 0 | +| arb_mux0 | arty_ddr3mig_7series_v4_2_arb_mux | 197 | 197 | 0 | 0 | 45 | 0 | 0 | 0 | +| arb_row_col0 | arty_ddr3mig_7series_v4_2_arb_row_col | 197 | 197 | 0 | 0 | 40 | 0 | 0 | 0 | +| (arb_row_col0) | arty_ddr3mig_7series_v4_2_arb_row_col | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| col_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1 | 66 | 66 | 0 | 0 | 8 | 0 | 0 | 0 | +| config_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_6 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pre_4_1_1T_arb.pre_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_7 | 47 | 47 | 0 | 0 | 8 | 0 | 0 | 0 | +| row_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb__parameterized1_8 | 65 | 65 | 0 | 0 | 8 | 0 | 0 | 0 | +| arb_select0 | arty_ddr3mig_7series_v4_2_arb_select | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| bank_cntrl[0].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl | 72 | 72 | 0 | 0 | 75 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_5 | 8 | 8 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue | 41 | 41 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state | 23 | 23 | 0 | 0 | 22 | 0 | 0 | 0 | +| bank_cntrl[1].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized0 | 70 | 70 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_4 | 13 | 13 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized0 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized0 | 21 | 21 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_cntrl[2].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized1 | 71 | 71 | 0 | 0 | 74 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare_3 | 10 | 10 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized1 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized1 | 28 | 28 | 0 | 0 | 21 | 0 | 0 | 0 | +| bank_cntrl[3].bank0 | arty_ddr3mig_7series_v4_2_bank_cntrl__parameterized2 | 72 | 72 | 0 | 0 | 73 | 0 | 0 | 0 | +| bank_compare0 | arty_ddr3mig_7series_v4_2_bank_compare | 14 | 14 | 0 | 0 | 35 | 0 | 0 | 0 | +| bank_queue0 | arty_ddr3mig_7series_v4_2_bank_queue__parameterized2 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | +| bank_state0 | arty_ddr3mig_7series_v4_2_bank_state__parameterized2 | 25 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | +| bank_common0 | arty_ddr3mig_7series_v4_2_bank_common | 26 | 26 | 0 | 0 | 22 | 0 | 0 | 0 | +| col_mach0 | arty_ddr3mig_7series_v4_2_col_mach | 27 | 19 | 8 | 0 | 26 | 0 | 0 | 0 | +| rank_mach0 | arty_ddr3mig_7series_v4_2_rank_mach | 91 | 90 | 0 | 1 | 71 | 0 | 0 | 0 | +| rank_cntrl[0].rank_cntrl0 | arty_ddr3mig_7series_v4_2_rank_cntrl | 11 | 10 | 0 | 1 | 13 | 0 | 0 | 0 | +| rank_common0 | arty_ddr3mig_7series_v4_2_rank_common | 80 | 80 | 0 | 0 | 58 | 0 | 0 | 0 | +| (rank_common0) | arty_ddr3mig_7series_v4_2_rank_common | 67 | 67 | 0 | 0 | 52 | 0 | 0 | 0 | +| maintenance_request.maint_arb0 | arty_ddr3mig_7series_v4_2_round_robin_arb | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 | +| u_axi_mc | arty_ddr3mig_7series_v4_2_axi_mc | 615 | 478 | 0 | 137 | 544 | 0 | 0 | 0 | +| (u_axi_mc) | arty_ddr3mig_7series_v4_2_axi_mc | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi_mc_ar_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 129 | 129 | 0 | 0 | 93 | 0 | 0 | 0 | +| (axi_mc_ar_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_ar_channel | 1 | 1 | 0 | 0 | 48 | 0 | 0 | 0 | +| ar_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_fsm | 83 | 83 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator_0 | 46 | 46 | 0 | 0 | 44 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd_1 | 38 | 38 | 0 | 0 | 36 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd_2 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_aw_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 132 | 132 | 0 | 0 | 91 | 0 | 0 | 0 | +| (axi_mc_aw_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_aw_channel | 0 | 0 | 0 | 0 | 46 | 0 | 0 | 0 | +| aw_cmd_fsm_0 | arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm | 82 | 82 | 0 | 0 | 1 | 0 | 0 | 0 | +| axi_mc_cmd_translator_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_translator | 51 | 51 | 0 | 0 | 44 | 0 | 0 | 0 | +| axi_mc_incr_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_incr_cmd | 43 | 43 | 0 | 0 | 36 | 0 | 0 | 0 | +| axi_mc_wrap_cmd_0 | arty_ddr3mig_7series_v4_2_axi_mc_wrap_cmd | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| axi_mc_b_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 12 | 8 | 0 | 4 | 9 | 0 | 0 | 0 | +| (axi_mc_b_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_b_channel | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | +| bid_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo | 11 | 7 | 0 | 4 | 4 | 0 | 0 | 0 | +| axi_mc_cmd_arbiter_0 | arty_ddr3mig_7series_v4_2_axi_mc_cmd_arbiter | 34 | 34 | 0 | 0 | 31 | 0 | 0 | 0 | +| axi_mc_r_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 160 | 27 | 0 | 133 | 24 | 0 | 0 | 0 | +| (axi_mc_r_channel_0) | arty_ddr3mig_7series_v4_2_axi_mc_r_channel | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | +| rd_data_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized0 | 141 | 13 | 0 | 128 | 6 | 0 | 0 | 0 | +| transaction_fifo_0 | arty_ddr3mig_7series_v4_2_axi_mc_fifo__parameterized1 | 19 | 14 | 0 | 5 | 6 | 0 | 0 | 0 | +| axi_mc_w_channel_0 | arty_ddr3mig_7series_v4_2_axi_mc_w_channel | 147 | 147 | 0 | 0 | 294 | 0 | 0 | 0 | +| u_ui_top | arty_ddr3mig_7series_v4_2_ui_top | 472 | 276 | 196 | 0 | 550 | 0 | 0 | 0 | +| ui_cmd0 | arty_ddr3mig_7series_v4_2_ui_cmd | 38 | 38 | 0 | 0 | 54 | 0 | 0 | 0 | +| ui_rd_data0 | arty_ddr3mig_7series_v4_2_ui_rd_data | 124 | 32 | 92 | 0 | 163 | 0 | 0 | 0 | +| ui_wr_data0 | arty_ddr3mig_7series_v4_2_ui_wr_data | 310 | 206 | 104 | 0 | 333 | 0 | 0 | 0 | +| memory_cdc | toy_axi_cdc | 530 | 252 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (memory_cdc) | toy_axi_cdc | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 530 | 252 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (inst) | toy_axi_cdcaxi_clock_converter_v2_1_30_axi_clock_converter | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_clock_conv.gen_async_conv.asyncfifo_axi | toy_axi_cdcfifo_generator_v13_2_10 | 529 | 251 | 278 | 0 | 1326 | 0 | 0 | 0 | +| (gen_clock_conv.gen_async_conv.asyncfifo_axi) | toy_axi_cdcfifo_generator_v13_2_10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst_fifo_gen | toy_axi_cdcfifo_generator_v13_2_10_synth | 529 | 251 | 278 | 0 | 1326 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.axi_rach | toy_axi_cdcfifo_generator_top | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__4 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__17 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__16 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_21 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_27 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_29 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_22 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_25 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_26 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory_23 | 42 | 0 | 42 | 0 | 122 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory_23 | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem_24 | 42 | 0 | 42 | 0 | 61 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__4 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__16 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__11 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 | toy_axi_cdcxpm_cdc_single | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gread_ch.grdch2.axi_rdch | toy_axi_cdcfifo_generator_top__parameterized2 | 143 | 51 | 92 | 0 | 369 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized2 | 143 | 51 | 92 | 0 | 369 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__18 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_14 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_18 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_20 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_15 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_16 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_17 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized2 | 92 | 0 | 92 | 0 | 270 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized2 | 0 | 0 | 0 | 0 | 135 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized2 | 92 | 0 | 92 | 0 | 135 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo | 16 | 16 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__18 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__13 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.axi_wach | toy_axi_cdcfifo_generator_top__xdcDup__1 | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__xdcDup__1 | 92 | 50 | 42 | 0 | 221 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__1 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__11 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__10 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_7 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_11 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_13 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_8 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_9 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_10 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory | 42 | 0 | 42 | 0 | 122 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem | 42 | 0 | 42 | 0 | 61 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__1 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__11 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__10 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 | toy_axi_cdcxpm_cdc_single__3 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch | toy_axi_cdcfifo_generator_top__parameterized0 | 148 | 50 | 98 | 0 | 389 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized0 | 148 | 50 | 98 | 0 | 389 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__2 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__13 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__12 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic_0 | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft_4 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr_6 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic_1 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as_2 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr_3 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized0 | 98 | 0 | 98 | 0 | 290 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized0 | 0 | 0 | 0 | 0 | 145 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized0 | 98 | 0 | 98 | 0 | 145 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__2 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__8 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__13 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__12 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__7 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 | toy_axi_cdcxpm_cdc_single__4 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch | toy_axi_cdcfifo_generator_top__parameterized1 | 54 | 50 | 4 | 0 | 111 | 0 | 0 | 0 | +| grf.rf | toy_axi_cdcfifo_generator_ramfifo__parameterized1 | 54 | 50 | 4 | 0 | 111 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gcx.clkx | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 12 | 12 | 0 | 0 | 40 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.gcx.clkx) | toy_axi_cdcclk_x_pntrs__xdcDup__3 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | +| rd_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__15 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| wr_pntr_cdc_inst | toy_axi_cdcxpm_cdc_gray__14 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | toy_axi_cdcrd_logic | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | toy_axi_cdcrd_fwft | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | +| gras.rsts | toy_axi_cdcrd_status_flags_as | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | toy_axi_cdcrd_bin_cntr | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | toy_axi_cdcwr_logic | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gwas.wsts | toy_axi_cdcwr_status_flags_as | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | toy_axi_cdcwr_bin_cntr | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | toy_axi_cdcmemory__parameterized1 | 4 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | toy_axi_cdcmemory__parameterized1 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | +| gdm.dm_gen.dm | toy_axi_cdcdmem__parameterized1 | 4 | 0 | 4 | 0 | 6 | 0 | 0 | 0 | +| rstblk | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 15 | 15 | 0 | 0 | 27 | 0 | 0 | 0 | +| (rstblk) | toy_axi_cdcreset_blk_ramfifo__xdcDup__3 | 15 | 15 | 0 | 0 | 13 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__10 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr | toy_axi_cdcxpm_cdc_single__parameterized1__15 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd | toy_axi_cdcxpm_cdc_single__parameterized1__14 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | toy_axi_cdcxpm_cdc_async_rst__9 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| platform | toy_a7_platform | 51966 | 48791 | 2950 | 225 | 28590 | 27 | 8 | 117 | +| chip | ToyLinuxChip | 50944 | 47881 | 2838 | 225 | 27538 | 27 | 8 | 117 | +| system | ToyLinuxSystem | 50944 | 47881 | 2838 | 225 | 27538 | 27 | 8 | 117 | +| (system) | ToyLinuxSystem | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bootrom_domain | bootromClockSinkDomain | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| bootrom | TLROM | 462 | 462 | 0 | 0 | 0 | 0 | 0 | 0 | +| cbus | PeripheryBus_cbus | 1023 | 869 | 154 | 0 | 364 | 0 | 0 | 0 | +| atomics | TLAtomicAutomata_cbus | 407 | 407 | 0 | 0 | 203 | 0 | 0 | 0 | +| buffer | TLBuffer_a28d64s3k1z4u | 263 | 133 | 130 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a28d64s3k1z4u | 111 | 57 | 54 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a28d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79_445 | 107 | 53 | 54 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a28d64s3k1z4u | 152 | 76 | 76 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a28d64s3k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x114 | 151 | 75 | 76 | 0 | 0 | 0 | 0 | 0 | +| coupler_to_bootrom | TLInterconnectCoupler_cbus_to_bootrom | 85 | 85 | 0 | 0 | 29 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_bootrom | 85 | 85 | 0 | 0 | 29 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_bootrom | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a17d64s3k1z3u | 84 | 84 | 0 | 0 | 20 | 0 | 0 | 0 | +| coupler_to_clint | TLInterconnectCoupler_cbus_to_clint | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_CLINT | 79 | 79 | 0 | 0 | 32 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_CLINT | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a26d64s3k1z3u | 79 | 79 | 0 | 0 | 23 | 0 | 0 | 0 | +| coupler_to_plic | TLInterconnectCoupler_cbus_to_plic | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| fragmenter | TLFragmenter_PLIC | 24 | 24 | 0 | 0 | 42 | 0 | 0 | 0 | +| (fragmenter) | TLFragmenter_PLIC | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | +| repeater | Repeater_TLBundleA_a28d64s3k1z3u | 21 | 21 | 0 | 0 | 33 | 0 | 0 | 0 | +| out_xbar | TLXbar_cbus_out_i1_o4_a28d64s3k1z4u | 83 | 83 | 0 | 0 | 17 | 0 | 0 | 0 | +| wrapped_error_device | ErrorDeviceWrapper | 82 | 58 | 24 | 0 | 35 | 0 | 0 | 0 | +| buffer | TLBuffer_a14d64s3k1z4u | 44 | 20 | 24 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a14d64s3k1z4u | 29 | 17 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a14d64s3k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x79 | 25 | 13 | 12 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a14d64s3k1z4u | 15 | 3 | 12 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a14d64s3k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x100 | 13 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | +| error | TLError | 38 | 38 | 0 | 0 | 29 | 0 | 0 | 0 | +| (error) | TLError | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | +| a_q | Queue1_TLBundleA_a14d64s3k1z4u | 31 | 31 | 0 | 0 | 11 | 0 | 0 | 0 | +| clint_domain | CLINTClockSinkDomain | 70 | 70 | 0 | 0 | 131 | 0 | 0 | 0 | +| clint | CLINT | 70 | 70 | 0 | 0 | 129 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w2_i0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| coh_wrapper | CoherenceManagerWrapper | 549 | 357 | 192 | 0 | 142 | 0 | 0 | 0 | +| broadcast_1 | TLBroadcast | 549 | 357 | 192 | 0 | 142 | 0 | 0 | 0 | +| (broadcast_1) | TLBroadcast | 17 | 17 | 0 | 0 | 44 | 0 | 0 | 0 | +| TLBroadcastTracker | TLBroadcastTracker | 384 | 288 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker) | TLBroadcastTracker | 20 | 20 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData_443 | 364 | 268 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData_443 | 102 | 102 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144_444 | 262 | 166 | 96 | 0 | 0 | 0 | 0 | 0 | +| TLBroadcastTracker_1 | TLBroadcastTracker_1 | 148 | 52 | 96 | 0 | 49 | 0 | 0 | 0 | +| (TLBroadcastTracker_1) | TLBroadcastTracker_1 | 32 | 32 | 0 | 0 | 44 | 0 | 0 | 0 | +| o_data_q | Queue4_TLBroadcastData | 116 | 20 | 96 | 0 | 5 | 0 | 0 | 0 | +| (o_data_q) | Queue4_TLBroadcastData | 15 | 15 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x144 | 101 | 5 | 96 | 0 | 0 | 0 | 0 | 0 | +| ibus_intsink | IntSyncAsyncCrossingSink_n1x1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| chain | SynchronizerShiftReg_w1_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| output_chain | NonSyncResetSynchronizerPrimitiveShiftReg_d3 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | +| ibus_intsource | IntSyncCrossingSource_n1x1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0__0 | AsyncResetRegVec_w1_i0_442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| mbus | MemoryBus | 745 | 489 | 256 | 0 | 330 | 0 | 0 | 0 | +| coupler_to_memory_controller_port_named_axi4 | TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 | 745 | 489 | 256 | 0 | 330 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker_1 | 439 | 183 | 256 | 0 | 96 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap_6 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap_6 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_441 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_6_380 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_6_380 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_440 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_10 | Queue2_BundleMap_6_381 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_10) | Queue2_BundleMap_6_381 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_439 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_11 | Queue2_BundleMap_6_382 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_11) | Queue2_BundleMap_6_382 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_438 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_12 | Queue2_BundleMap_6_383 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_12) | Queue2_BundleMap_6_383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_437 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_13 | Queue2_BundleMap_6_384 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_13) | Queue2_BundleMap_6_384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_436 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_14 | Queue2_BundleMap_6_385 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_14) | Queue2_BundleMap_6_385 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_435 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_15 | Queue2_BundleMap_6_386 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_15) | Queue2_BundleMap_6_386 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_434 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_16 | Queue2_BundleMap_6_387 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_16) | Queue2_BundleMap_6_387 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_433 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_17 | Queue2_BundleMap_6_388 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_17) | Queue2_BundleMap_6_388 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_432 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_18 | Queue2_BundleMap_6_389 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_18) | Queue2_BundleMap_6_389 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_431 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_19 | Queue2_BundleMap_6_390 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_19) | Queue2_BundleMap_6_390 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_430 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_6_391 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_6_391 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_429 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_20 | Queue2_BundleMap_6_392 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_20) | Queue2_BundleMap_6_392 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_428 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_21 | Queue2_BundleMap_6_393 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_21) | Queue2_BundleMap_6_393 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_427 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_22 | Queue2_BundleMap_6_394 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_22) | Queue2_BundleMap_6_394 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_426 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_23 | Queue2_BundleMap_6_395 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_23) | Queue2_BundleMap_6_395 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_425 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_24 | Queue2_BundleMap_6_396 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_24) | Queue2_BundleMap_6_396 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_424 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_25 | Queue2_BundleMap_6_397 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_25) | Queue2_BundleMap_6_397 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_423 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_26 | Queue2_BundleMap_6_398 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_26) | Queue2_BundleMap_6_398 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_422 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_27 | Queue2_BundleMap_6_399 | 43 | 35 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_27) | Queue2_BundleMap_6_399 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_421 | 42 | 34 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_28 | Queue2_BundleMap_6_400 | 12 | 4 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_28) | Queue2_BundleMap_6_400 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_420 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_29 | Queue2_BundleMap_6_401 | 9 | 1 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_29) | Queue2_BundleMap_6_401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_419 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_6_402 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_6_402 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_418 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_30 | Queue2_BundleMap_6_403 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_30) | Queue2_BundleMap_6_403 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_417 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_31 | Queue2_BundleMap_6_404 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_31) | Queue2_BundleMap_6_404 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_416 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_6_405 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_6_405 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_415 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_6_406 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_6_406 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_414 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_6 | Queue2_BundleMap_6_407 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_6) | Queue2_BundleMap_6_407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_413 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_7 | Queue2_BundleMap_6_408 | 19 | 11 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_7) | Queue2_BundleMap_6_408 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_412 | 18 | 10 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_8 | Queue2_BundleMap_6_409 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_8) | Queue2_BundleMap_6_409 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10_411 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_9 | Queue2_BundleMap_6_410 | 10 | 2 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_9) | Queue2_BundleMap_6_410 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x10 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4_1 | 306 | 306 | 0 | 0 | 234 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4_1 | 3 | 3 | 0 | 0 | 41 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW_1 | 83 | 83 | 0 | 0 | 146 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW_1 | 220 | 220 | 0 | 0 | 47 | 0 | 0 | 0 | +| plic_domain | PLICClockSinkDomain | 36 | 36 | 0 | 0 | 52 | 0 | 0 | 0 | +| intsource | IntSyncCrossingSource_n1x1_377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0_379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| intsource_1 | IntSyncCrossingSource_n1x1_378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| reg_0 | AsyncResetRegVec_w1_i0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| plic | TLPLIC | 36 | 36 | 0 | 0 | 50 | 0 | 0 | 0 | +| (plic) | TLPLIC | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| gateways_gateway | LevelGateway | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| out_back_front_q | Queue1_RegMapperInput_i23_m8 | 31 | 31 | 0 | 0 | 41 | 0 | 0 | 0 | +| sbus | SystemBus | 1457 | 1111 | 346 | 0 | 608 | 0 | 0 | 0 | +| coupler_to_bus_named_cbus | TLInterconnectCoupler_sbus_to_bus_named_cbus | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| widget | TLWidthWidget16 | 143 | 143 | 0 | 0 | 191 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16 | 64 | 64 | 0 | 0 | 68 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a28d128s3k1z4u | 79 | 79 | 0 | 0 | 123 | 0 | 0 | 0 | +| coupler_to_port_named_mmio_port_axi4 | TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4 | 804 | 458 | 346 | 0 | 353 | 0 | 0 | 0 | +| axi4buf | AXI4Buffer | 207 | 69 | 138 | 0 | 15 | 0 | 0 | 0 | +| nodeIn_b_deq_q | Queue2_AXI4BundleB | 18 | 14 | 4 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_deq_q) | Queue2_AXI4BundleB | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x4 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_r_deq_q | Queue2_AXI4BundleR | 42 | 6 | 36 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_r_deq_q) | Queue2_AXI4BundleR | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x69 | 39 | 3 | 36 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_ar_deq_q | Queue2_AXI4BundleAR | 61 | 29 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_ar_deq_q) | Queue2_AXI4BundleAR | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58_376 | 57 | 25 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_aw_deq_q | Queue2_AXI4BundleAW | 48 | 16 | 32 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_aw_deq_q) | Queue2_AXI4BundleAW | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x58 | 42 | 10 | 32 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue2_AXI4BundleW | 38 | 4 | 34 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_w_deq_q) | Queue2_AXI4BundleW | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x73 | 36 | 2 | 34 | 0 | 0 | 0 | 0 | 0 | +| axi4deint | AXI4Deinterleaver | 277 | 117 | 160 | 0 | 47 | 0 | 0 | 0 | +| (axi4deint) | AXI4Deinterleaver | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | +| qs_queue_0 | Queue8_AXI4BundleR | 51 | 11 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_0) | Queue8_AXI4BundleR | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_375 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_1 | Queue8_AXI4BundleR_370 | 73 | 33 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_1) | Queue8_AXI4BundleR_370 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_374 | 67 | 27 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_2 | Queue8_AXI4BundleR_371 | 49 | 9 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_2) | Queue8_AXI4BundleR_371 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77_373 | 43 | 3 | 40 | 0 | 0 | 0 | 0 | 0 | +| qs_queue_3 | Queue8_AXI4BundleR_372 | 104 | 64 | 40 | 0 | 7 | 0 | 0 | 0 | +| (qs_queue_3) | Queue8_AXI4BundleR_372 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x77 | 98 | 58 | 40 | 0 | 0 | 0 | 0 | 0 | +| axi4yank | AXI4UserYanker | 92 | 44 | 48 | 0 | 34 | 0 | 0 | 0 | +| Queue1_BundleMap | Queue1_BundleMap | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue1_BundleMap_1 | Queue1_BundleMap_359 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| Queue2_BundleMap | Queue2_BundleMap | 15 | 7 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap) | Queue2_BundleMap | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_369 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_1 | Queue2_BundleMap_360 | 13 | 5 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_1) | Queue2_BundleMap_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_368 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_2 | Queue2_BundleMap_361 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_2) | Queue2_BundleMap_361 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_367 | 11 | 3 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_3 | Queue2_BundleMap_362 | 14 | 6 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_3) | Queue2_BundleMap_362 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_366 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_4 | Queue2_BundleMap_363 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_4) | Queue2_BundleMap_363 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8_365 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| Queue2_BundleMap_5 | Queue2_BundleMap_364 | 11 | 3 | 8 | 0 | 3 | 0 | 0 | 0 | +| (Queue2_BundleMap_5) | Queue2_BundleMap_364 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x8 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| tl2axi4 | TLToAXI4 | 127 | 127 | 0 | 0 | 114 | 0 | 0 | 0 | +| (tl2axi4) | TLToAXI4 | 22 | 22 | 0 | 0 | 17 | 0 | 0 | 0 | +| nodeOut_w_deq_q | Queue1_AXI4BundleW | 57 | 57 | 0 | 0 | 50 | 0 | 0 | 0 | +| queue_arw_deq_q | Queue1_AXI4BundleARW | 48 | 48 | 0 | 0 | 47 | 0 | 0 | 0 | +| widget | TLWidthWidget16_2 | 101 | 101 | 0 | 0 | 143 | 0 | 0 | 0 | +| (widget) | TLWidthWidget16_2 | 45 | 45 | 0 | 0 | 48 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleA_a31d128s3k1z3u | 56 | 56 | 0 | 0 | 95 | 0 | 0 | 0 | +| system_bus_xbar | TLXbar_sbus_i2_o3_a32d128s3k1z4c | 510 | 510 | 0 | 0 | 64 | 0 | 0 | 0 | +| tile_prci_domain | TilePRCIDomain | 46597 | 44483 | 1890 | 224 | 25903 | 27 | 8 | 117 | +| buffer | TLBuffer_a32d128s2k1z4u_1 | 1214 | 628 | 586 | 0 | 21 | 0 | 0 | 0 | +| nodeIn_b_q | Queue2_TLBundleB_a32d128s2k1z4c | 28 | 4 | 24 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_b_q) | Queue2_TLBundleB_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x60 | 25 | 1 | 24 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d128s2k1z4u | 101 | 5 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d128s2k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142_358 | 97 | 1 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeIn_d_q_1 | Queue2_TLBundleD_a32d128s2k1z4c | 161 | 65 | 96 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q_1) | Queue2_TLBundleD_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x142 | 158 | 62 | 96 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d128s2k1z4u | 144 | 16 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d128s2k1z4u | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189_357 | 142 | 14 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q_1 | Queue2_TLBundleA_a32d128s2k1z4c | 646 | 518 | 128 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q_1) | Queue2_TLBundleA_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x189 | 643 | 515 | 128 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_c_q | Queue2_TLBundleC_a32d128s2k1z4c | 128 | 16 | 112 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_c_q) | Queue2_TLBundleC_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x173 | 125 | 13 | 112 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_e_q | Queue2_TLBundleE_a32d128s2k1z4c | 6 | 4 | 2 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_e_q) | Queue2_TLBundleE_a32d128s2k1z4c | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_sink_ext | ram_sink_2x1 | 3 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | +| element_reset_domain_bbtile | BBTile | 45383 | 43855 | 1304 | 224 | 25882 | 27 | 8 | 117 | +| (element_reset_domain_bbtile) | BBTile | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| accelerators_0 | BuckyballAccelerator | 24384 | 23650 | 510 | 224 | 15033 | 18 | 0 | 95 | +| ballDomain | BallDomain | 14446 | 14032 | 190 | 224 | 10879 | 0 | 0 | 93 | +| ballRs | BallReservationStation | 148 | 52 | 96 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_BallReservationStation_Anon | 148 | 52 | 96 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_BallReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x281 | 145 | 49 | 96 | 0 | 0 | 0 | 0 | 0 | +| bbus | BBus | 14298 | 13980 | 94 | 224 | 10874 | 0 | 0 | 93 | +| (bbus) | BBus | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | +| balls_0 | GemminiBall | 14298 | 13980 | 94 | 224 | 10864 | 0 | 0 | 93 | +| (balls_0) | GemminiBall | 1 | 1 | 0 | 0 | 470 | 0 | 0 | 0 | +| convUnroller | LoopConvUnroller | 521 | 521 | 0 | 0 | 375 | 0 | 0 | 20 | +| (convUnroller) | LoopConvUnroller | 40 | 40 | 0 | 0 | 375 | 0 | 0 | 0 | +| addrGen | LoopConvAddrGen | 487 | 487 | 0 | 0 | 0 | 0 | 0 | 20 | +| exCtrl | GemminiExCtrl | 13112 | 12794 | 94 | 224 | 9717 | 0 | 0 | 64 | +| (exCtrl) | GemminiExCtrl | 1428 | 1428 | 0 | 0 | 2444 | 0 | 0 | 0 | +| mesh | MeshWithDelays | 11288 | 11058 | 6 | 224 | 7259 | 0 | 0 | 64 | +| (mesh) | MeshWithDelays | 632 | 408 | 0 | 224 | 557 | 0 | 0 | 0 | +| mesh | Mesh | 9993 | 9993 | 0 | 0 | 6098 | 0 | 0 | 64 | +| (mesh) | Mesh | 225 | 225 | 0 | 0 | 3530 | 0 | 0 | 0 | +| mesh_0_0 | Tile | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_354 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_354 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_355 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_356 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_1 | Tile_104 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_351 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_351 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_352 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_353 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_2 | Tile_105 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_348 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_348 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_349 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_350 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_3 | Tile_106 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_345 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_345 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_346 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_347 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_4 | Tile_107 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_342 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_342 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_343 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_344 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_5 | Tile_108 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_339 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_339 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_340 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_341 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_6 | Tile_109 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_336 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_336 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_337 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_338 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_0_7 | Tile_110 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_333 | 154 | 154 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_333 | 96 | 96 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_334 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_335 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_0 | Tile_111 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_330 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_330 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_331 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_332 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_1 | Tile_112 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_327 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_327 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_328 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_329 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_2 | Tile_113 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_324 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_324 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_325 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_326 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_3 | Tile_114 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_321 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_321 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_322 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_323 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_4 | Tile_115 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_318 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_318 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_319 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_320 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_5 | Tile_116 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_315 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_315 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_316 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_317 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_6 | Tile_117 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_312 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_312 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_313 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_314 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_1_7 | Tile_118 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_309 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_309 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_310 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_311 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_0 | Tile_119 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_306 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_306 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_307 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_308 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_1 | Tile_120 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_303 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_303 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_304 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_305 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_2 | Tile_121 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_300 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_300 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_301 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_302 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_3 | Tile_122 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_297 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_297 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_298 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_299 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_4 | Tile_123 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_294 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_294 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_295 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_296 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_5 | Tile_124 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_291 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_291 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_292 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_293 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_6 | Tile_125 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_288 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_288 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_289 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_290 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_2_7 | Tile_126 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_285 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_285 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_286 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_287 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_0 | Tile_127 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_282 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_282 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_283 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_284 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_1 | Tile_128 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_279 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_279 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_280 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_281 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_2 | Tile_129 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_276 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_276 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_277 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_278 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_3 | Tile_130 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_273 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_273 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_274 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_275 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_4 | Tile_131 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_270 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_270 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_271 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_272 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_5 | Tile_132 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_267 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_267 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_268 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_269 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_6 | Tile_133 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_264 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_264 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_265 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_266 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_3_7 | Tile_134 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_261 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_261 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_262 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_263 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_0 | Tile_135 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_258 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_258 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_259 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_260 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_1 | Tile_136 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_255 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_255 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_256 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_257 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_2 | Tile_137 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_252 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_252 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_253 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_254 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_3 | Tile_138 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_249 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_249 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_250 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_251 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_4 | Tile_139 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_246 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_246 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_247 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_248 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_5 | Tile_140 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_243 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_243 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_244 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_245 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_6 | Tile_141 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_240 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_240 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_241 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_242 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_4_7 | Tile_142 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_237 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_237 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_238 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_239 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_0 | Tile_143 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_234 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_234 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_235 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_236 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_1 | Tile_144 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_231 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_231 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_232 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_233 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_2 | Tile_145 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_228 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_228 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_229 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_230 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_3 | Tile_146 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_225 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_225 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_226 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_227 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_4 | Tile_147 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_222 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_222 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_223 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_224 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_5 | Tile_148 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_219 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_219 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_220 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_221 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_6 | Tile_149 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_216 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_216 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_217 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_218 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_5_7 | Tile_150 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_213 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_213 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_214 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_215 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_0 | Tile_151 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_210 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_210 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_211 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_212 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_1 | Tile_152 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_207 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_207 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_208 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_209 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_2 | Tile_153 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_204 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_204 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_205 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_206 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_3 | Tile_154 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_201 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_201 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_202 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_203 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_4 | Tile_155 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_198 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_198 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_199 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_200 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_5 | Tile_156 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_195 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_195 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_196 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_197 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_6 | Tile_157 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_192 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_192 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_193 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_194 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_6_7 | Tile_158 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| tile_0_0 | PE_64_189 | 152 | 152 | 0 | 0 | 40 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_189 | 94 | 94 | 0 | 0 | 40 | 0 | 0 | 0 | +| mac_unit | MacUnit_190 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_191 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_0 | Tile_159 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_186 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_186 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_187 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_188 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_1 | Tile_160 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_183 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_183 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_184 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_185 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_2 | Tile_161 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_180 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_180 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_181 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_182 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_3 | Tile_162 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_177 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_177 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_178 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_179 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_4 | Tile_163 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_174 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_174 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_175 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_176 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_5 | Tile_164 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_171 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_171 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_172 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_173 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_6 | Tile_165 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_168 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_168 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit_169 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac_170 | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mesh_7_7 | Tile_166 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| tile_0_0 | PE_64_167 | 155 | 155 | 0 | 0 | 41 | 0 | 0 | 1 | +| (tile_0_0) | PE_64_167 | 97 | 97 | 0 | 0 | 41 | 0 | 0 | 0 | +| mac_unit | MacUnit | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| mac | FpgaDspMac | 58 | 58 | 0 | 0 | 0 | 0 | 0 | 1 | +| tagq | TagQueue | 117 | 117 | 0 | 0 | 75 | 0 | 0 | 0 | +| total_rows_q | Queue6_TagWithIdAndTotalRows | 32 | 26 | 6 | 0 | 7 | 0 | 0 | 0 | +| (total_rows_q) | Queue6_TagWithIdAndTotalRows | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_6x7 | 27 | 21 | 6 | 0 | 0 | 0 | 0 | 0 | +| transposer | AlwaysOutTransposer | 514 | 514 | 0 | 0 | 522 | 0 | 0 | 0 | +| (transposer) | AlwaysOutTransposer | 8 | 8 | 0 | 0 | 10 | 0 | 0 | 0 | +| pes_0_0 | PE | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_1 | PE_41 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_2 | PE_42 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_3 | PE_43 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_4 | PE_44 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_5 | PE_45 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_6 | PE_46 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_0_7 | PE_47 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_0 | PE_48 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_1 | PE_49 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_2 | PE_50 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_3 | PE_51 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_4 | PE_52 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_5 | PE_53 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_6 | PE_54 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_1_7 | PE_55 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_0 | PE_56 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_1 | PE_57 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_2 | PE_58 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_3 | PE_59 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_4 | PE_60 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_5 | PE_61 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_6 | PE_62 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_2_7 | PE_63 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_0 | PE_64 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_1 | PE_65 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_2 | PE_66 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_3 | PE_67 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_4 | PE_68 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_5 | PE_69 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_6 | PE_70 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_3_7 | PE_71 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_0 | PE_72 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_1 | PE_73 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_2 | PE_74 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_3 | PE_75 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_4 | PE_76 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_5 | PE_77 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_6 | PE_78 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_4_7 | PE_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_0 | PE_80 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_1 | PE_81 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_2 | PE_82 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_3 | PE_83 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_4 | PE_84 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_5 | PE_85 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_6 | PE_86 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_5_7 | PE_87 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_0 | PE_88 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_1 | PE_89 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_2 | PE_90 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_3 | PE_91 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_4 | PE_92 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_5 | PE_93 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_6 | PE_94 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_6_7 | PE_95 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_0 | PE_96 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_1 | PE_97 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_2 | PE_98 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_3 | PE_99 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_4 | PE_100 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_5 | PE_101 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_6 | PE_102 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| pes_7_7 | PE_103 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | +| rdQueue0 | Queue8_SramReadResp | 306 | 262 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue0) | Queue8_SramReadResp | 100 | 100 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64_40 | 206 | 162 | 44 | 0 | 0 | 0 | 0 | 0 | +| rdQueue1 | Queue8_SramReadResp_39 | 90 | 46 | 44 | 0 | 7 | 0 | 0 | 0 | +| (rdQueue1) | Queue8_SramReadResp_39 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_data_ext | ram_data_8x64 | 46 | 2 | 44 | 0 | 0 | 0 | 0 | 0 | +| matmulUnroller | LoopMatmulUnroller | 664 | 664 | 0 | 0 | 302 | 0 | 0 | 9 | +| cmdRouter | CmdRouter | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| bankReadReqQ_q | Queue8_BuckyballAccelerator_Anon | 33 | 17 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q) | Queue8_BuckyballAccelerator_Anon | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21_38 | 27 | 11 | 16 | 0 | 0 | 0 | 0 | 0 | +| bankReadReqQ_q_1 | Queue8_BuckyballAccelerator_Anon_10 | 37 | 21 | 16 | 0 | 7 | 0 | 0 | 0 | +| (bankReadReqQ_q_1) | Queue8_BuckyballAccelerator_Anon_10 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| ram_ext | ram_8x21 | 31 | 15 | 16 | 0 | 0 | 0 | 0 | 0 | +| frontend | Frontend_1 | 5269 | 5073 | 196 | 0 | 2205 | 2 | 0 | 0 | +| boot | BootRom | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | +| scheduler | GlobalScheduler | 5259 | 5063 | 196 | 0 | 2199 | 2 | 0 | 0 | +| (scheduler) | GlobalScheduler | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| completeQueue | Queue16_UInt4 | 34 | 30 | 4 | 0 | 9 | 0 | 0 | 0 | +| (completeQueue) | Queue16_UInt4 | 10 | 10 | 0 | 0 | 9 | 0 | 0 | 0 | +| ram_ext | ram_16x4 | 24 | 20 | 4 | 0 | 0 | 0 | 0 | 0 | +| rob | GlobalROB | 4660 | 4660 | 0 | 0 | 1668 | 2 | 0 | 0 | +| (rob) | GlobalROB | 1446 | 1446 | 0 | 0 | 1476 | 0 | 0 | 0 | +| bat | BankAliasTable | 1017 | 1017 | 0 | 0 | 176 | 0 | 0 | 0 | +| robOperands | robOperands | 1725 | 1725 | 0 | 0 | 0 | 2 | 0 | 0 | +| robOperands_ext | robOperands_ext | 1725 | 1725 | 0 | 0 | 0 | 2 | 0 | 0 | +| scoreboard | BankScoreboard | 472 | 472 | 0 | 0 | 16 | 0 | 0 | 0 | +| subRob | SubROB | 565 | 373 | 192 | 0 | 519 | 0 | 0 | 0 | +| (subRob) | SubROB | 370 | 370 | 0 | 0 | 273 | 0 | 0 | 0 | +| sram | sram | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| sram_ext | sram_ext | 195 | 3 | 192 | 0 | 246 | 0 | 0 | 0 | +| gpDomain | GpDomain | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| completeQ | Queue1_GlobalSchedComplete | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | +| memDomain | MemDomain | 4599 | 4507 | 92 | 0 | 1928 | 16 | 0 | 2 | +| backend | MemBackend | 2387 | 2387 | 0 | 0 | 472 | 16 | 0 | 0 | +| privateBackend | PrivateMemBackend | 2387 | 2387 | 0 | 0 | 472 | 16 | 0 | 0 | +| (privateBackend) | PrivateMemBackend | 203 | 203 | 0 | 0 | 243 | 0 | 0 | 0 | +| accPipes_0 | AccPipe | 350 | 350 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_1 | AccPipe_11 | 334 | 334 | 0 | 0 | 67 | 0 | 0 | 0 | +| accPipes_2 | AccPipe_12 | 59 | 59 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_3 | AccPipe_13 | 292 | 292 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_4 | AccPipe_14 | 333 | 333 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_5 | AccPipe_15 | 520 | 520 | 0 | 0 | 3 | 0 | 0 | 0 | +| accPipes_6 | AccPipe_16 | 296 | 296 | 0 | 0 | 67 | 0 | 0 | 0 | +| banks_0 | SramBank | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_0) | SramBank | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_36 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_37 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_1 | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_1) | SramBank_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_34 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_35 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_2 | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_2) | SramBank_18 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_32 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_33 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_3 | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_3) | SramBank_19 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_30 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_31 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_4 | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_4) | SramBank_20 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_28 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_29 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_5 | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_5) | SramBank_21 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_26 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_27 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_6 | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_6) | SramBank_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem_24 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext_25 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| banks_7 | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 2 | 0 | 0 | +| (banks_7) | SramBank_23 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| mem | mem | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| mem_ext | mem_ext | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| frontend | MemFrontend | 2172 | 2080 | 92 | 0 | 1446 | 0 | 0 | 2 | +| (frontend) | MemFrontend | 594 | 594 | 0 | 0 | 2 | 0 | 0 | 0 | +| configer | MemConfiger | 135 | 135 | 0 | 0 | 63 | 0 | 0 | 0 | +| (configer) | MemConfiger | 96 | 96 | 0 | 0 | 29 | 0 | 0 | 0 | +| zeroLines | ZeroLineGenerator | 39 | 39 | 0 | 0 | 34 | 0 | 0 | 0 | +| groupQuery | MemGroupQueryArbiter | 10 | 10 | 0 | 0 | 12 | 0 | 0 | 0 | +| (groupQuery) | MemGroupQueryArbiter | 10 | 10 | 0 | 0 | 11 | 0 | 0 | 0 | +| arbiter | RRArbiter_2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| memLoader | MemLoader | 240 | 240 | 0 | 0 | 242 | 0 | 0 | 0 | +| memRs | MemReservationStation | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| fifo | Queue4_MemReservationStation_Anon | 164 | 72 | 92 | 0 | 5 | 0 | 0 | 0 | +| (fifo) | Queue4_MemReservationStation_Anon | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | +| ram_ext | ram_4x158 | 161 | 69 | 92 | 0 | 0 | 0 | 0 | 0 | +| memStorer | MemStorer | 384 | 384 | 0 | 0 | 447 | 0 | 0 | 0 | +| reader | StreamReader | 548 | 548 | 0 | 0 | 304 | 0 | 0 | 2 | +| tlbCluster | BBTLBCluster | 151 | 151 | 0 | 0 | 261 | 0 | 0 | 0 | +| (tlbCluster) | BBTLBCluster | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| tlb | TLB | 151 | 151 | 0 | 0 | 259 | 0 | 0 | 0 | +| tlbArb | RRArbiter_1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| writer | StreamWriter | 5 | 5 | 0 | 0 | 110 | 0 | 0 | 0 | +| midend | MemMidend | 40 | 40 | 0 | 0 | 10 | 0 | 0 | 0 | +| barrierUnit | BarrierUnit | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| buffer | TLBuffer_a32d64s1k1z4u | 130 | 50 | 80 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u_7 | 94 | 42 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s1k1z4u_7 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x77 | 90 | 38 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u_8 | 36 | 8 | 28 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u_8 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116_9 | 33 | 5 | 28 | 0 | 0 | 0 | 0 | 0 | +| buffer_1 | TLBuffer_a32d64s1k1z4u_1 | 147 | 75 | 72 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s1k1z4u | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s1k1z4u | 143 | 71 | 72 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s1k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x116 | 140 | 68 | 72 | 0 | 0 | 0 | 0 | 0 | +| buffer_2 | TLBuffer_a32d64s2k1z4u | 241 | 109 | 132 | 0 | 6 | 0 | 0 | 0 | +| nodeIn_d_q | Queue2_TLBundleD_a32d64s2k1z4u | 57 | 5 | 52 | 0 | 3 | 0 | 0 | 0 | +| (nodeIn_d_q) | Queue2_TLBundleD_a32d64s2k1z4u | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x78 | 54 | 2 | 52 | 0 | 0 | 0 | 0 | 0 | +| nodeOut_a_q | Queue2_TLBundleA_a32d64s2k1z4u | 184 | 104 | 80 | 0 | 3 | 0 | 0 | 0 | +| (nodeOut_a_q) | Queue2_TLBundleA_a32d64s2k1z4u | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | +| ram_ext | ram_2x117 | 183 | 103 | 80 | 0 | 0 | 0 | 0 | 0 | +| cores_0 | RocketBB | 6198 | 6110 | 88 | 0 | 1898 | 0 | 0 | 13 | +| (cores_0) | RocketBB | 2423 | 2423 | 0 | 0 | 755 | 0 | 0 | 0 | +| csr | CSRFile | 1983 | 1983 | 0 | 0 | 870 | 0 | 0 | 0 | +| div | MulDiv | 1571 | 1571 | 0 | 0 | 214 | 0 | 0 | 13 | +| ibuf | IBuf | 102 | 102 | 0 | 0 | 59 | 0 | 0 | 0 | +| rf_ext | rf_31x64 | 119 | 31 | 88 | 0 | 0 | 0 | 0 | 0 | +| dcache | NonBlockingDCache | 3253 | 3161 | 92 | 0 | 3330 | 9 | 0 | 0 | +| (dcache) | NonBlockingDCache | 519 | 519 | 0 | 0 | 1150 | 0 | 0 | 0 | +| data | DataArray | 256 | 256 | 0 | 0 | 2 | 8 | 0 | 0 | +| (data) | DataArray | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| array_0_0 | array_0_0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_6 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_1 | array_0_1 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_5 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_0 | array_2_0 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext_4 | 64 | 64 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_2_1 | array_2_1 | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| array_0_0_ext | array_0_0_ext | 128 | 128 | 0 | 0 | 0 | 2 | 0 | 0 | +| dtlb | DTLB | 1277 | 1277 | 0 | 0 | 1692 | 0 | 0 | 0 | +| lfsr_prng | MaxPeriodFibonacciLFSR_3 | 13 | 13 | 0 | 0 | 16 | 0 | 0 | 0 | +| meta | L1MetadataArray | 129 | 37 | 92 | 0 | 98 | 0 | 0 | 0 | +| (meta) | L1MetadataArray | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | +| tag_array | tag_array | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| tag_array_ext | tag_array_ext | 126 | 34 | 92 | 0 | 92 | 0 | 0 | 0 | +| mshrs | MSHRFile | 693 | 693 | 0 | 0 | 292 | 1 | 0 | 0 | +| (mshrs) | MSHRFile | 2 | 2 | 0 | 0 | 26 | 0 | 0 | 0 | +| mmios_0 | IOMSHR | 297 | 297 | 0 | 0 | 180 | 0 | 0 | 0 | +| mshrs_0 | MSHR | 314 | 314 | 0 | 0 | 86 | 0 | 0 | 0 | +| (mshrs_0) | MSHR | 119 | 119 | 0 | 0 | 75 | 0 | 0 | 0 | +| grantackq | Queue1_TLBundleE_a32d128s1k1z4c | 78 | 78 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpq | Queue16_ReplayInternal | 117 | 117 | 0 | 0 | 9 | 0 | 0 | 0 | +| sdq_ext | sdq_17x64 | 80 | 80 | 0 | 0 | 0 | 1 | 0 | 0 | +| prober | ProbeUnit | 81 | 81 | 0 | 0 | 40 | 0 | 0 | 0 | +| wb | WritebackUnit | 285 | 285 | 0 | 0 | 40 | 0 | 0 | 0 | +| dcacheArb | HellaCacheArbiter | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | +| fpuOpts_0 | FPU | 8025 | 7761 | 264 | 0 | 2618 | 0 | 0 | 9 | +| (fpuOpts_0) | FPU | 28 | 28 | 0 | 0 | 193 | 0 | 0 | 0 | +| divSqrt | DivSqrtRecFM_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e5_s11 | 152 | 152 | 0 | 0 | 60 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e5_s11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie5_is13_oe5_os11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_1 | DivSqrtRecFM_small_e8_s24 | 345 | 345 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e8_s24 | 340 | 340 | 0 | 0 | 103 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e8_s24 | 340 | 340 | 0 | 0 | 103 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e8_s24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie8_is26_oe8_os24 | 5 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | +| divSqrt_2 | DivSqrtRecFM_small_e11_s53 | 858 | 858 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRecFNToRaw | DivSqrtRecFMToRaw_small_e11_s53 | 849 | 849 | 0 | 0 | 195 | 0 | 0 | 0 | +| divSqrtRawFN | DivSqrtRawFN_small_e11_s53 | 849 | 849 | 0 | 0 | 195 | 0 | 0 | 0 | +| roundRawFNToRecFN | RoundRawFNToRecFN_e11_s53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is55_oe11_os53 | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpiu | FPToInt | 1044 | 1044 | 0 | 0 | 140 | 0 | 0 | 0 | +| (fpiu) | FPToInt | 993 | 993 | 0 | 0 | 140 | 0 | 0 | 0 | +| dcmp | CompareRecFN | 51 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | +| fpmu | FPToFP | 436 | 436 | 0 | 0 | 208 | 0 | 0 | 0 | +| (fpmu) | FPToFP | 93 | 93 | 0 | 0 | 208 | 0 | 0 | 0 | +| narrower | RecFNToRecFN | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe5_os11 | 126 | 126 | 0 | 0 | 0 | 0 | 0 | 0 | +| narrower_1 | RecFNToRecFN_1 | 217 | 217 | 0 | 0 | 0 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie11_is53_oe8_os24 | 217 | 217 | 0 | 0 | 0 | 0 | 0 | 0 | +| ifpu | IntToFP | 1581 | 1581 | 0 | 0 | 695 | 0 | 0 | 0 | +| (ifpu) | IntToFP | 61 | 61 | 0 | 0 | 140 | 0 | 0 | 0 | +| i2f_0 | PipelinedINToRecFN | 799 | 799 | 0 | 0 | 281 | 0 | 0 | 0 | +| (i2f_0) | PipelinedINToRecFN | 772 | 772 | 0 | 0 | 281 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe5_os11 | 27 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_1 | PipelinedINToRecFN_1 | 361 | 361 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_1) | PipelinedINToRecFN_1 | 333 | 333 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe8_os24 | 28 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | +| i2f_2 | PipelinedINToRecFN_2 | 360 | 360 | 0 | 0 | 137 | 0 | 0 | 0 | +| (i2f_2) | PipelinedINToRecFN_2 | 319 | 319 | 0 | 0 | 137 | 0 | 0 | 0 | +| roundAnyRawFNToRecFN | RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 | 41 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | +| regfile_ext | regfile_32x65 | 1108 | 844 | 264 | 0 | 32 | 0 | 0 | 0 | +| sharedFma | FPUSharedFMAPipe | 2473 | 2473 | 0 | 0 | 992 | 0 | 0 | 9 | +| (sharedFma) | FPUSharedFMAPipe | 15 | 15 | 0 | 0 | 238 | 0 | 0 | 0 | +| fma | SharedMulAddRecFNPipe | 2458 | 2458 | 0 | 0 | 754 | 0 | 0 | 9 | +| frontend | Frontend | 2154 | 2112 | 42 | 0 | 2221 | 0 | 8 | 0 | +| (frontend) | Frontend | 3 | 3 | 0 | 0 | 90 | 0 | 0 | 0 | +| fq | ShiftQueue | 775 | 775 | 0 | 0 | 375 | 0 | 0 | 0 | +| icache | ICache | 550 | 508 | 42 | 0 | 294 | 0 | 8 | 0 | +| (icache) | ICache | 266 | 266 | 0 | 0 | 236 | 0 | 0 | 0 | +| bbtile_icache_data_arrays_0 | bbtile_icache_data_arrays_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_1 | bbtile_icache_data_arrays_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_1 | 43 | 43 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_2 | bbtile_icache_data_arrays_2 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext_0 | 2 | 2 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_3 | bbtile_icache_data_arrays_3 | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_data_arrays_0_ext | bbtile_icache_data_arrays_0_ext | 45 | 45 | 0 | 0 | 0 | 0 | 2 | 0 | +| bbtile_icache_tag_array | bbtile_icache_tag_array | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| bbtile_icache_tag_array_ext | bbtile_icache_tag_array_ext | 63 | 21 | 42 | 0 | 42 | 0 | 0 | 0 | +| repl_way_v0_prng | MaxPeriodFibonacciLFSR | 129 | 129 | 0 | 0 | 16 | 0 | 0 | 0 | +| tlb | ITLB | 826 | 826 | 0 | 0 | 1462 | 0 | 0 | 0 | +| ptw | PTW | 786 | 786 | 0 | 0 | 567 | 0 | 0 | 0 | +| roccMemIF | SimpleHellaCacheIF | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | +| (roccMemIF) | SimpleHellaCacheIF | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| replayq | SimpleHellaCacheIFReplayQueue | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| (replayq) | SimpleHellaCacheIFReplayQueue | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| nackq | Queue3_UInt2 | 8 | 8 | 0 | 0 | 5 | 0 | 0 | 0 | +| tlMasterXbar | TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c | 44 | 44 | 0 | 0 | 11 | 0 | 0 | 0 | +| widget_3 | TLWidthWidget8_4 | 85 | 85 | 0 | 0 | 160 | 0 | 0 | 0 | +| (widget_3) | TLWidthWidget8_4 | 1 | 1 | 0 | 0 | 81 | 0 | 0 | 0 | +| repeated_repeater | Repeater_TLBundleD_a32d128s2k1z4u | 84 | 84 | 0 | 0 | 79 | 0 | 0 | 0 | +| xbar | TLXbar_i2_o1_a32d64s2k1z4u | 65 | 65 | 0 | 0 | 13 | 0 | 0 | 0 | +| load_bridge | loader_axi | 41 | 41 | 0 | 0 | 306 | 0 | 0 | 0 | +| loader | ddr_uart_loader | 441 | 377 | 64 | 0 | 159 | 0 | 0 | 0 | +| normalizer | axi_fullwidth | 334 | 334 | 0 | 0 | 376 | 0 | 0 | 0 | +| peripherals | axi_scu | 152 | 104 | 48 | 0 | 162 | 0 | 0 | 0 | +| receiver | uart_rx | 39 | 39 | 0 | 0 | 31 | 0 | 0 | 0 | +| transmitter | uart_tx | 15 | 15 | 0 | 0 | 18 | 0 | 0 | 0 | ++----------------------------------------------------------------------------------------+-----------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-timing.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-timing.rpt new file mode 100644 index 0000000..d53b91f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-timing.rpt @@ -0,0 +1,4930 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:30:55 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_timing_summary -delay_type min_max -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synth-timing.rpt +| Design : toy_a7_top +| Device : 7a100t-csg324 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (3) +6. checking no_output_delay (6) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (3) +------------------------------ + There is 1 input port with no input delay specified. (HIGH) + + There are 2 input ports with no input delay but user has a false path constraint. (MEDIUM) + + +6. checking no_output_delay (6) +------------------------------- + There are 0 ports with no output delay specified. + + There are 6 ports with no output delay but user has a false path constraint (MEDIUM) + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 1.277 0.000 0 108329 -1.631 -26.741 55 108287 0.187 0.000 0 42005 + + +Timing constraints are not met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +board_clk {0.000 5.000} 10.000 100.000 + core_raw {0.000 20.000} 40.000 25.000 + fb {0.000 5.000} 10.000 100.000 + ref_raw {0.000 2.500} 5.000 200.000 + sys_raw {0.000 3.000} 6.000 166.667 + freq_refclk {0.000 0.750} 1.500 666.667 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv {0.000 6.000} 12.000 83.333 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {0.000 1.500} 3.000 333.333 + iserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + mem_refclk {0.000 1.500} 3.000 333.333 + oserdes_clk {0.000 1.500} 3.000 333.333 + oserdes_clkdiv {0.000 6.000} 12.000 83.333 + oserdes_clk_1 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_1 {0.000 6.000} 12.000 83.333 + oserdes_clk_2 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_2 {0.000 3.000} 6.000 166.667 + oserdes_clk_3 {0.000 1.500} 3.000 333.333 + oserdes_clkdiv_3 {0.000 3.000} 6.000 166.667 + pll_clk3_out {0.000 6.000} 12.000 83.333 + clk_div2_bufg_in {0.000 3.000} 6.000 166.667 + clk_pll_i {0.000 6.000} 12.000 83.333 + mmcm_ps_clk_bufg_in {0.000 12.000} 24.000 41.667 + pll_clkfbout {0.000 3.000} 6.000 166.667 + sync_pulse {1.312 4.313} 48.000 20.833 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +board_clk 3.000 0.000 0 1 + core_raw 14.939 0.000 0 92516 0.045 0.000 0 92516 18.750 0.000 0 35544 + fb 7.845 0.000 0 3 + ref_raw 2.263 0.000 0 130 0.045 0.000 0 130 0.264 0.000 0 69 + sys_raw 1.500 0.000 0 3 + freq_refclk 0.187 0.000 0 8 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv 9.972 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 1.333 0.000 0 16 + iserdes_clkdiv_1 9.955 0.000 0 33 0.071 0.000 0 33 3.850 0.000 0 9 + mem_refclk 1.810 0.000 0 1 0.375 0.000 0 1 0.875 0.000 0 8 + oserdes_clk 1.333 0.000 0 12 + oserdes_clkdiv 10.094 0.000 0 44 0.113 0.000 0 44 3.850 0.000 0 12 + oserdes_clk_1 1.333 0.000 0 12 + oserdes_clkdiv_1 10.595 0.000 0 48 0.119 0.000 0 48 3.850 0.000 0 13 + oserdes_clk_2 1.442 0.000 0 4 0.440 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_2 4.602 0.000 0 36 0.116 0.000 0 36 0.850 0.000 0 11 + oserdes_clk_3 1.458 0.000 0 4 0.432 0.000 0 4 1.333 0.000 0 12 + oserdes_clkdiv_3 4.618 0.000 0 36 0.109 0.000 0 36 0.850 0.000 0 11 + pll_clk3_out 3.000 0.000 0 3 + clk_div2_bufg_in 4.741 0.000 0 12 0.152 0.000 0 12 2.500 0.000 0 15 + clk_pll_i 5.851 0.000 0 15062 0.034 0.000 0 15062 3.850 0.000 0 6181 + mmcm_ps_clk_bufg_in 22.715 0.000 0 12 0.152 0.000 0 12 11.500 0.000 0 15 + pll_clkfbout 4.751 0.000 0 2 + sync_pulse 1.750 0.000 0 8 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +clk_pll_i core_raw 10.968 0.000 0 20 +clk_pll_i ref_raw 18.960 0.000 0 1 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk 12.367 0.000 0 8 44.683 0.000 0 8 +clk_pll_i u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk 12.374 0.000 0 8 44.679 0.000 0 8 +sync_pulse mem_refclk 1.277 0.000 0 1 0.910 0.000 0 1 +oserdes_clk oserdes_clkdiv 2.105 0.000 0 12 -0.247 -1.473 11 12 +oserdes_clk_1 oserdes_clkdiv_1 2.105 0.000 0 13 -0.268 -2.486 12 13 +oserdes_clk_2 oserdes_clkdiv_2 2.105 0.000 0 15 -0.274 -2.156 10 15 +oserdes_clk_3 oserdes_clkdiv_3 2.105 0.000 0 15 -0.197 -1.058 10 15 +core_raw clk_pll_i 38.968 0.000 0 20 +ref_raw clk_pll_i 19.759 0.000 0 12 -1.631 -19.568 12 12 + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- +**async_default** clk_pll_i clk_pll_i 9.663 0.000 0 113 0.295 0.000 0 113 +**async_default** core_raw core_raw 34.624 0.000 0 119 0.295 0.000 0 119 +**default** clk_pll_i 3.113 0.000 0 1 + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: board_clk + To Clock: board_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: board_clk +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { CLK100MHZ } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 clock_mmcm/CLKIN1 +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 clock_mmcm/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 clock_mmcm/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 clock_mmcm/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 14.939ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 14.939ns (required time - arrival time) + Source: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/CLK + (rising edge-triggered cell DSP48E1 clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/I + (rising edge-triggered cell RAMD32 clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 24.566ns (logic 19.514ns (79.434%) route 5.052ns (20.566%)) + Logic Levels: 12 (CARRY4=4 DSP48E1=5 LUT2=1 LUT4=1 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 37.762 - 40.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.111 -3.045 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.803 -2.242 core_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r core_buffer/O + net (fo=35560, unplaced) 0.584 -1.562 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/clk + DSP48E1 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/CLK + ------------------------------------------------------------------- ------------------- + DSP48E1 (Prop_dsp48e1_CLK_P[16]) + 4.009 2.447 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[16] + net (fo=1, unplaced) 0.803 3.250 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5_n_89 + DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47]) + 4.036 7.286 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/PCOUT[47] + net (fo=1, unplaced) 0.000 7.286 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0_n_106 + DSP48E1 (Prop_dsp48e1_PCIN[47]_P[19]) + 1.518 8.804 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[19] + net (fo=1, unplaced) 0.803 9.607 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1_n_86 + DSP48E1 (Prop_dsp48e1_C[36]_P[16]) + 1.820 11.427 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[16] + net (fo=1, unplaced) 0.803 12.229 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2_n_89 + DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47]) + 4.036 16.265 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/PCOUT[47] + net (fo=1, unplaced) 0.000 16.265 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1_n_106 + DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0]) + 1.518 17.783 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[0] + net (fo=1, unplaced) 0.803 18.586 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0_n_105 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.659 19.245 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__3_i_5/CO[3] + net (fo=1, unplaced) 0.000 19.245 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__3_i_5_n_0 + CARRY4 (Prop_carry4_CI_O[3]) + 0.331 19.576 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__4_i_5/O[3] + net (fo=1, unplaced) 0.448 20.024 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr0[23] + LUT2 (Prop_lut2_I1_O) 0.307 20.331 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_i_4/O + net (fo=1, unplaced) 0.000 20.331 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_i_4_n_0 + CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 20.844 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5/CO[3] + net (fo=1, unplaced) 0.000 20.844 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__5_n_0 + CARRY4 (Prop_carry4_CI_O[1]) + 0.337 21.181 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr_carry__6/O[1] + net (fo=1, unplaced) 0.611 21.792 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_addrGen_io_outputAddr[30] + LUT4 (Prop_lut4_I1_O) 0.306 22.098 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/lanes[0].ram_reg_0_7_234_239_i_8/O + net (fo=1, unplaced) 0.449 22.547 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_convUnroller_io_cmd_bits_slots_0_bits_dram_addr[26] + LUT6 (Prop_lut6_I5_O) 0.124 22.671 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/lanes[0].ram_reg_0_7_234_239_i_1/O + net (fo=1, unplaced) 0.333 23.004 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/DIA1 + RAMD32 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/I + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, unplaced) 0.439 41.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.381 36.470 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.763 37.232 core_raw + BUFG (Prop_bufg_I_O) 0.091 37.323 r core_buffer/O + net (fo=35560, unplaced) 0.439 37.762 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/WCLK + RAMD32 r platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1/CLK + clock pessimism 0.531 38.293 + clock uncertainty -0.091 38.202 + RAMD32 (Setup_ramd32_CLK_I) + -0.258 37.944 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/subRob/sram/sram_ext/lanes[0].ram_reg_0_7_234_239/RAMA_D1 + ------------------------------------------------------------------- + required time 37.944 + arrival time -23.004 + ------------------------------------------------------------------- + slack 14.939 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.045ns (arrival time - required time) + Source: btn_meta_reg/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: btn_sync_reg/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.228ns (logic 0.147ns (64.493%) route 0.081ns (35.507%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.777 -1.414 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.338 -1.075 core_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r core_buffer/O + net (fo=35560, unplaced) 0.114 -0.935 clk + FDRE r btn_meta_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 -0.788 r btn_meta_reg/Q + net (fo=1, unplaced) 0.081 -0.707 btn_meta + FDRE r btn_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.411 -1.715 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.356 -1.358 core_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r core_buffer/O + net (fo=35560, unplaced) 0.259 -1.070 clk + FDRE r btn_sync_reg/C + clock pessimism 0.280 -0.790 + FDRE (Hold_fdre_C_D) 0.038 -0.752 btn_sync_reg + ------------------------------------------------------------------- + required time 0.752 + arrival time -0.707 + ------------------------------------------------------------------- + slack 0.045 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: core_raw +Waveform(ns): { 0.000 20.000 } +Period(ns): 40.000 +Sources: { clock_mmcm/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a DSP48E1/CLK n/a 3.884 40.000 36.116 platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b_reg/CLK +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 clock_mmcm/CLKOUT0 +Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: fb + To Clock: fb + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: fb +Waveform(ns): { 0.000 5.000 } +Period(ns): 10.000 +Sources: { clock_mmcm/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 10.000 7.845 fb_buffer/I +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 clock_mmcm/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 2.263ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.263ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/R + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 5.000ns (ref_raw rise@5.000ns - ref_raw rise@0.000ns) + Data Path Delay: 1.968ns (logic 0.773ns (39.278%) route 1.195ns (60.722%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 2.762 - 5.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.113ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.111 -3.045 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.803 -2.242 ref_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r ref_buffer/O + net (fo=67, unplaced) 0.584 -1.562 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 -1.084 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2_reg/Q + net (fo=32, unplaced) 0.541 -0.543 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r2 + LUT2 (Prop_lut2_I0_O) 0.295 -0.248 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer[10]_i_1/O + net (fo=11, unplaced) 0.654 0.406 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer0__20 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/R + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 5.000 5.000 r + E3 0.000 5.000 r CLK100MHZ (IN) + net (fo=0) 0.000 5.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 6.411 r input_clock/O + net (fo=1, unplaced) 0.439 6.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.381 1.470 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.763 2.232 ref_raw + BUFG (Prop_bufg_I_O) 0.091 2.323 r ref_buffer/O + net (fo=67, unplaced) 0.439 2.762 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0]/C + clock pessimism 0.531 3.293 + clock uncertainty -0.067 3.226 + FDRE (Setup_fdre_C_R) -0.557 2.669 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.sample_timer_reg[0] + ------------------------------------------------------------------- + required time 2.669 + arrival time -0.406 + ------------------------------------------------------------------- + slack 2.263 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.045ns (arrival time - required time) + Source: btn_ref_meta_reg/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: btn_ref_sync_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (ref_raw rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.228ns (logic 0.147ns (64.493%) route 0.081ns (35.507%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -1.777 -1.414 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.338 -1.075 ref_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r ref_buffer/O + net (fo=67, unplaced) 0.114 -0.935 ref_clk + FDRE r btn_ref_meta_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 -0.788 r btn_ref_meta_reg/Q + net (fo=1, unplaced) 0.081 -0.707 btn_ref_meta + FDRE r btn_ref_sync_reg/D + ------------------------------------------------------------------- ------------------- + + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.411 -1.715 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.356 -1.358 ref_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r ref_buffer/O + net (fo=67, unplaced) 0.259 -1.070 ref_clk + FDRE r btn_ref_sync_reg/C + clock pessimism 0.280 -0.790 + FDRE (Hold_fdre_C_D) 0.038 -0.752 btn_ref_sync_reg + ------------------------------------------------------------------- + required time 0.752 + arrival time -0.707 + ------------------------------------------------------------------- + slack 0.045 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: ref_raw +Waveform(ns): { 0.000 2.500 } +Period(ns): 5.000 +Sources: { clock_mmcm/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a XADC/DCLK n/a 4.000 5.000 1.000 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.XADC_inst/DCLK +Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 ddr_controller/u_arty_ddr3_mig/u_iodelay_ctrl/u_idelayctrl_200/REFCLK +Low Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 btn_ref_meta_reg/C +High Pulse Width Slow FDRE/C n/a 0.500 2.500 2.000 btn_ref_meta_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: sys_raw + To Clock: sys_raw + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sys_raw +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { clock_mmcm/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 sys_buffer/I +Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 +High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 1.500 3.000 1.500 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: freq_refclk + To Clock: freq_refclk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 0.187ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: freq_refclk +Waveform(ns): { 0.000 0.750 } +Period(ns): 1.500 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 1.250 1.500 0.250 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Max Period n/a PHASER_OUT_PHY/FREQREFCLK n/a 2.500 1.500 1.000 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK +Low Pulse Width Slow PHASER_REF/CLKIN n/a 0.562 0.750 0.188 PHASER_REF_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i/CLKIN +High Pulse Width Slow PHASER_OUT_PHY/FREQREFCLK n/a 0.563 0.750 0.187 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/FREQREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv + To Clock: iserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 9.972ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.972ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv rise@12.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.956ns (logic 0.425ns (44.456%) route 0.531ns (55.544%)) + Logic Levels: 0 + Clock Path Skew: -0.450ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.533ns = ( 12.533 - 12.000 ) + Source Clock Delay (SCD): 1.637ns + Clock Pessimism Removal (CPR): 0.654ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.607 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.014 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.187 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.450 1.637 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y76 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y76 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.062 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, estimated) 0.531 2.593 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/if_d1[3] + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.577 10.746 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.370 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.533 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 12.533 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.654 13.187 + clock uncertainty -0.051 13.136 + IN_FIFO_X1Y6 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 12.565 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 12.565 + arrival time -2.593 + ------------------------------------------------------------------- + slack 9.972 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv rise@0.000ns - iserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.826ns + Source Clock Delay (SCD): 1.042ns + Clock Pessimism Removal (CPR): -0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.256 -0.405 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.952 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.042 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.100 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, estimated) 0.000 1.100 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_wr_enable + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.269 -0.651 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.730 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.826 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 0.826 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clkdiv + IN_FIFO_X1Y6 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.216 1.042 + IN_FIFO_X1Y6 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.029 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.029 + arrival time 1.100 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a ISERDESE2/CLK n/a 1.667 3.000 1.333 ILOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: iserdes_clkdiv_1 + To Clock: iserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 9.955ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.071ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.955ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + (rising edge-triggered cell ISERDESE2 clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (iserdes_clkdiv_1 rise@12.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.956ns (logic 0.425ns (44.456%) route 0.531ns (55.544%)) + Logic Levels: 0 + Clock Path Skew: -0.467ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.523ns = ( 12.523 - 12.000 ) + Source Clock Delay (SCD): 1.644ns + Clock Pessimism Removal (CPR): 0.654ns + Clock Uncertainty: 0.051ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.073ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.597 -0.658 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.662 1.004 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.173 1.177 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.467 1.644 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/iserdes_clkdiv + ILOGIC_X1Y88 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/CLKDIVP + ------------------------------------------------------------------- ------------------- + ILOGIC_X1Y88 ISERDESE2 (Prop_iserdese2_CLKDIVP_Q1) + 0.425 2.069 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.iserdesdq/Q1 + net (fo=1, estimated) 0.531 2.600 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/if_d1[3] + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/D1[3] + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.567 10.736 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 12.360 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.163 12.523 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 12.523 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.654 13.177 + clock uncertainty -0.051 13.126 + IN_FIFO_X1Y7 IN_FIFO (Setup_in_fifo_WRCLK_D1[3]) + -0.571 12.555 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time 12.555 + arrival time -2.600 + ------------------------------------------------------------------- + slack 9.955 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.071ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + (rising edge-triggered cell PHASER_IN_PHY clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + (rising edge-triggered cell IN_FIFO clocked by iserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: iserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (iserdes_clkdiv_1 rise@0.000ns - iserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.058ns (logic 0.058ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.821ns + Source Clock Delay (SCD): 1.037ns + Clock Pessimism Removal (CPR): -0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.252 -0.409 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.357 0.947 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.090 1.037 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + ------------------------------------------------------------------- ------------------- + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLKDIV_WRENABLE) + 0.058 1.095 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/WRENABLE + net (fo=1, estimated) 0.000 1.095 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_wr_enable + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WREN + ------------------------------------------------------------------- ------------------- + + (clock iserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.265 -0.655 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 0.725 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_ICLK_ICLKDIV) + 0.096 0.821 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV + net (fo=9, estimated) 0.000 0.821 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clkdiv + IN_FIFO_X1Y7 IN_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + clock pessimism 0.216 1.037 + IN_FIFO_X1Y7 IN_FIFO (Hold_in_fifo_WRCLK_WREN) + -0.013 1.024 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo + ------------------------------------------------------------------- + required time -1.024 + arrival time 1.095 + ------------------------------------------------------------------- + slack 0.071 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: iserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a IN_FIFO/WRCLK n/a 5.000 12.000 7.000 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +Low Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK +High Pulse Width Slow IN_FIFO/WRCLK n/a 2.150 6.000 3.850 IN_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mem_refclk + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.810ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.375ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.875ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.810ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (mem_refclk rise@3.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 1.093ns (logic 0.622ns (56.908%) route 0.471ns (43.092%)) + Logic Levels: 0 + Clock Path Skew: -0.031ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.241ns = ( 1.759 - 3.000 ) + Source Clock Delay (SCD): -0.634ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.621 -0.634 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.622 -0.012 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, estimated) 0.471 0.459 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.590 1.759 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.576 2.335 + clock uncertainty -0.054 2.280 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + -0.011 2.269 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 2.269 + arrival time -0.459 + ------------------------------------------------------------------- + slack 1.810 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.375ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mem_refclk rise@0.000ns - mem_refclk rise@0.000ns) + Data Path Delay: 0.512ns (logic 0.313ns (61.188%) route 0.199ns (38.812%)) + Logic Levels: 0 + Clock Path Skew: 0.014ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.645ns + Source Clock Delay (SCD): -0.399ns + Clock Pessimism Removal (CPR): -0.259ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.262 -0.399 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + ------------------------------------------------------------------- ------------------- + PHY_CONTROL_X1Y1 PHY_CONTROL (Prop_phy_control_MEMREFCLK_PHYCTLEMPTY) + 0.313 -0.086 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLEMPTY + net (fo=1, estimated) 0.199 0.112 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_n_1 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/PHYCTLMSTREMPTY + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.276 -0.645 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.259 -0.385 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_PHYCTLMSTREMPTY) + 0.123 -0.262 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.262 + arrival time 0.112 + ------------------------------------------------------------------- + slack 0.375 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mem_refclk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PHY_CONTROL/MEMREFCLK n/a 1.475 3.000 1.525 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 3.000 157.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 +Low Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK +High Pulse Width Slow PHY_CONTROL/MEMREFCLK n/a 0.625 1.500 0.875 PHY_CONTROL_X1Y1 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clk + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y51 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 10.094ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.113ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.094ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 1.662ns (logic 0.674ns (40.554%) route 0.988ns (59.446%)) + Logic Levels: 0 + Clock Path Skew: 0.435ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.706ns = ( 13.706 - 12.000 ) + Source Clock Delay (SCD): 1.950ns + Clock Pessimism Removal (CPR): 0.679ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.950 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 1.950 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[7]) + 0.674 2.624 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q6[7] + net (fo=1, estimated) 0.988 3.612 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[43] + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/D4 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 10.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.435 13.706 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y50 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.679 14.385 + clock uncertainty -0.054 14.330 + OLOGIC_X1Y50 OSERDESE2 (Setup_oserdese2_CLKDIV_D4) + -0.625 13.705 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[11].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 13.705 + arrival time -3.612 + ------------------------------------------------------------------- + slack 10.094 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.113ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clkdiv rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.203ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.773ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.773 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y4 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.911 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.109 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_dq[10] + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.203 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y53 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.976 + OLOGIC_X1Y53 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.995 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.995 + arrival time 2.109 + ------------------------------------------------------------------- + slack 0.113 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clk_1 + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_1 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y63 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[0].oserdes_dq_.sdr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 10.595ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.119ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.595ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.419ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.679ns = ( 13.679 - 12.000 ) + Source Clock Delay (SCD): 1.939ns + Clock Pessimism Removal (CPR): 0.678ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.939 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 1.939 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q5[4]) + 0.674 2.613 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q5[4] + net (fo=1, estimated) 0.470 3.083 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[40] + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 10.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.419 13.679 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y69 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.678 14.358 + clock uncertainty -0.054 14.303 + OLOGIC_X1Y69 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 13.678 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[10].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time 13.678 + arrival time -3.083 + ------------------------------------------------------------------- + slack 10.595 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.119ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clkdiv_1 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.197ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.773ns + Source Clock Delay (SCD): 1.768ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.768 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 1.768 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y5 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.104 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_dq[10] + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.197 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y65 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.966 + OLOGIC_X1Y65 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.985 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[2].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.985 + arrival time 2.104 + ------------------------------------------------------------------- + slack 0.119 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_1 +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y5 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clk_2 + +Setup : 0 Failing Endpoints, Worst Slack 1.442ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.440ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.442ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_2 rise@3.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 1.041ns (logic 0.562ns (53.987%) route 0.479ns (46.013%)) + Logic Levels: 0 + Clock Path Skew: 0.423ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.285ns = ( 5.285 - 3.000 ) + Source Clock Delay (SCD): 2.577ns + Clock Pessimism Removal (CPR): 0.715ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 2.577 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.139 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/CTSBUS[0] + net (fo=2, estimated) 0.479 3.618 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 1.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 4.862 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.423 5.285 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.715 6.000 + clock uncertainty -0.054 5.945 + OLOGIC_X1Y82 ODDR (Setup_oddr_C_D1) -0.885 5.060 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.060 + arrival time -3.618 + ------------------------------------------------------------------- + slack 1.442 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.440ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.346ns (63.590%) route 0.198ns (36.410%)) + Logic Levels: 0 + Clock Path Skew: 0.197ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.360ns + Source Clock Delay (SCD): 2.320ns + Clock Pessimism Removal (CPR): -0.158ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.320 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[0]) + 0.346 2.666 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/DQSBUS[0] + net (fo=1, estimated) 0.198 2.865 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/DQSBUS[0] + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.163 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.197 2.360 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y82 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.158 2.518 + OLOGIC_X1Y82 ODDR (Hold_oddr_C_D1) -0.093 2.425 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.425 + arrival time 2.865 + ------------------------------------------------------------------- + slack 0.440 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_2 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y76 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 4.602ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.116ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.602ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.426ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.696ns = ( 7.696 - 6.000 ) + Source Clock Delay (SCD): 1.950ns + Clock Pessimism Removal (CPR): 0.679ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 -0.641 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.950 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.950 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 2.624 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q6[0] + net (fo=1, estimated) 0.470 3.094 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y83 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 4.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.426 7.696 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y83 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.679 8.375 + clock uncertainty -0.054 8.321 + OLOGIC_X1Y83 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 7.696 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 7.696 + arrival time -3.094 + ------------------------------------------------------------------- + slack 4.602 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.116ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clkdiv_2 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.201ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.781ns + Source Clock Delay (SCD): 1.773ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.773 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y6 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.911 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.109 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.201 1.781 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.974 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.993 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.993 + arrival time 2.109 + ------------------------------------------------------------------- + slack 0.116 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_2 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y6 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clk_3 + +Setup : 0 Failing Endpoints, Worst Slack 1.458ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.432ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.333ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.458ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clk_3 rise@3.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 1.041ns (logic 0.562ns (53.987%) route 0.479ns (46.013%)) + Logic Levels: 0 + Clock Path Skew: 0.439ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.290ns = ( 5.290 - 3.000 ) + Source Clock Delay (SCD): 2.566ns + Clock Pessimism Removal (CPR): 0.714ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.784 2.566 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_CTSBUS[0]) + 0.562 3.128 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/CTSBUS[0] + net (fo=2, estimated) 0.479 3.607 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CTSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 4.411 r input_clock/O + net (fo=1, unplaced) 0.439 4.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -0.530 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 0.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 0.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 1.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 1.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 1.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 4.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.739 4.851 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.439 5.290 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts/C + clock pessimism 0.714 6.005 + clock uncertainty -0.054 5.950 + OLOGIC_X1Y94 ODDR (Setup_oddr_C_D1) -0.885 5.065 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts + ------------------------------------------------------------------- + required time 5.065 + arrival time -3.607 + ------------------------------------------------------------------- + slack 1.458 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.432ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + (rising edge-triggered cell ODDR clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: oserdes_clk_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clk_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.544ns (logic 0.346ns (63.590%) route 0.198ns (36.410%)) + Logic Levels: 0 + Clock Path Skew: 0.205ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 2.363ns + Source Clock Delay (SCD): 2.316ns + Clock Pessimism Removal (CPR): -0.158ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.630 2.316 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLKDELAYED_DQSBUS[0]) + 0.346 2.662 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/DQSBUS[0] + net (fo=1, estimated) 0.198 2.860 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/DQSBUS[0] + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDELAYED) + 0.670 2.158 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDELAYED + net (fo=2, estimated) 0.205 2.363 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clk_delayed + OLOGIC_X1Y94 ODDR r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs/C + clock pessimism 0.158 2.521 + OLOGIC_X1Y94 ODDR (Hold_oddr_C_D1) -0.093 2.428 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs + ------------------------------------------------------------------- + required time -2.428 + arrival time 2.860 + ------------------------------------------------------------------- + slack 0.432 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clk_3 +Waveform(ns): { 0.000 1.500 } +Period(ns): 3.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OSERDESE2/CLK n/a 1.667 3.000 1.333 OLOGIC_X1Y88 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clkdiv_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 4.618ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.109ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 0.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.618ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 1.144ns (logic 0.674ns (58.916%) route 0.470ns (41.084%)) + Logic Levels: 0 + Clock Path Skew: 0.442ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.702ns = ( 7.702 - 6.000 ) + Source Clock Delay (SCD): 1.939ns + Clock Pessimism Removal (CPR): 0.678ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.083ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 -0.652 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 1.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.157 1.939 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.939 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q6[0]) + 0.674 2.613 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q6[0] + net (fo=1, estimated) 0.470 3.083 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[20] + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/D1 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 4.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.442 7.702 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y95 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.678 8.381 + clock uncertainty -0.054 8.326 + OLOGIC_X1Y95 OSERDESE2 (Setup_oserdese2_CLKDIV_D1) + -0.625 7.701 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[6].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time 7.701 + arrival time -3.083 + ------------------------------------------------------------------- + slack 4.618 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.109ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clkdiv_3 rise@0.000ns) + Data Path Delay: 0.336ns (logic 0.138ns (41.109%) route 0.198ns (58.891%)) + Logic Levels: 0 + Clock Path Skew: 0.208ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.768ns + Clock Pessimism Removal (CPR): -0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.083 1.768 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 1.768 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + ------------------------------------------------------------------- ------------------- + OUT_FIFO_X1Y7 OUT_FIFO (Prop_out_fifo_RDCLK_Q2[2]) + 0.138 1.906 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/Q2[2] + net (fo=1, estimated) 0.198 2.104 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/of_dqbus[6] + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/D3 + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.208 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y89 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.192 1.976 + OLOGIC_X1Y89 OSERDESE2 (Hold_oserdese2_CLKDIV_D3) + 0.019 1.995 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -1.995 + arrival time 2.104 + ------------------------------------------------------------------- + slack 0.109 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: oserdes_clkdiv_3 +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/RDCLK n/a 5.000 6.000 1.000 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +Low Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK +High Pulse Width Slow OUT_FIFO/RDCLK n/a 2.150 3.000 0.850 OUT_FIFO_X1Y7 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clk3_out + To Clock: pll_clk3_out + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clk3_out +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFH/I n/a 2.155 12.000 9.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/I +Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 +High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 3.000 6.000 3.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKIN1 + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_div2_bufg_in + To Clock: clk_div2_bufg_in + +Setup : 0 Failing Endpoints, Worst Slack 4.741ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.152ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 2.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 4.741ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: clk_div2_bufg_in + Path Type: Setup (Max at Slow Process Corner) + Requirement: 6.000ns (clk_div2_bufg_in rise@6.000ns - clk_div2_bufg_in rise@0.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.872ns = ( 5.128 - 6.000 ) + Source Clock Delay (SCD): 0.040ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.149ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.584 0.040 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.518 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.334 0.852 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_div2_bufg_in rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 4.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 4.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 5.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.616 3.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.763 4.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.091 4.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.439 5.128 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + clock pessimism 0.767 5.895 + clock uncertainty -0.082 5.812 + FDPE (Setup_fdpe_C_D) -0.220 5.592 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg + ------------------------------------------------------------------- + required time 5.592 + arrival time -0.852 + ------------------------------------------------------------------- + slack 4.741 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.152ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by clk_div2_bufg_in {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: clk_div2_bufg_in + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_div2_bufg_in rise@0.000ns - clk_div2_bufg_in rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.147ns (51.079%) route 0.141ns (48.921%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.359ns + Source Clock Delay (SCD): -0.413ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.114 -0.413 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.266 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.141 -0.125 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_div2_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_div2_bufg_in + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/O + net (fo=13, unplaced) 0.259 -0.359 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + clock pessimism 0.091 -0.268 + FDPE (Hold_fdpe_C_D) -0.009 -0.277 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg + ------------------------------------------------------------------- + required time 0.277 + arrival time -0.125 + ------------------------------------------------------------------- + slack 0.152 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_div2_bufg_in +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 6.000 3.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_clk_div2/I +Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 6.000 207.360 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT1 +Low Pulse Width Slow FDPE/C n/a 0.500 3.000 2.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C +High Pulse Width Slow FDPE/C n/a 0.500 3.000 2.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv2_sync_r1_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 5.851ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.034ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 3.850ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 5.851ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 5.981ns (logic 1.393ns (23.290%) route 4.588ns (76.710%)) + Logic Levels: 6 (LUT5=1 LUT6=5) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.653ns = ( 11.347 - 12.000 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1_reg/Q + net (fo=12, unplaced) 1.013 1.750 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_done_r1 + LUT6 (Prop_lut6_I0_O) 0.295 2.045 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[3]_i_24/O + net (fo=3, unplaced) 0.982 3.027 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[3]_i_24_n_0 + LUT6 (Prop_lut6_I0_O) 0.124 3.151 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[4]_i_27/O + net (fo=2, unplaced) 0.460 3.611 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[4]_i_27_n_0 + LUT5 (Prop_lut5_I0_O) 0.124 3.735 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_16/O + net (fo=1, unplaced) 0.449 4.184 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_16_n_0 + LUT6 (Prop_lut6_I5_O) 0.124 4.308 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_5/O + net (fo=1, unplaced) 0.732 5.040 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_5_n_0 + LUT6 (Prop_lut6_I3_O) 0.124 5.164 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_1/O + net (fo=2, unplaced) 0.952 6.116 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/init_state_r[0]_i_1_n_0 + LUT6 (Prop_lut6_I0_O) 0.124 6.240 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_i_1/O + net (fo=1, unplaced) 0.000 6.240 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_i_1_n_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 10.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 11.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.616 9.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.763 10.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.091 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.658 11.347 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg/C + clock pessimism 0.767 12.114 + clock uncertainty -0.067 12.046 + FDRE (Setup_fdre_C_D) 0.044 12.090 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_final_chk_reg + ------------------------------------------------------------------- + required time 12.090 + arrival time -6.240 + ------------------------------------------------------------------- + slack 5.851 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.034ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/I + (rising edge-triggered cell RAMD32 clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.272ns (logic 0.131ns (48.199%) route 0.141ns (51.801%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 -0.316 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/cnt_read_reg[0] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.131 -0.185 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/u_axi_mc/axi_mc_b_channel_0/bid_t_reg[0]/Q + net (fo=1, unplaced) 0.141 -0.044 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/DIB0 + RAMD32 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.356 -0.262 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK + RAMD32 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK + clock pessimism 0.091 -0.171 + RAMD32 (Hold_ramd32_CLK_I) + 0.093 -0.078 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB + ------------------------------------------------------------------- + required time 0.078 + arrival time -0.044 + ------------------------------------------------------------------- + slack 0.034 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_pll_i +Waveform(ns): { 0.000 6.000 } +Period(ns): 12.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a OUT_FIFO/WRCLK n/a 5.000 12.000 7.000 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 12.000 88.000 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBIN +Low Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK +High Pulse Width Slow OUT_FIFO/WRCLK n/a 2.150 6.000 3.850 OUT_FIFO_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/WRCLK + + + +--------------------------------------------------------------------------------------------------- +From Clock: mmcm_ps_clk_bufg_in + To Clock: mmcm_ps_clk_bufg_in + +Setup : 0 Failing Endpoints, Worst Slack 22.715ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.152ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 11.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 22.715ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Path Group: mmcm_ps_clk_bufg_in + Path Type: Setup (Max at Slow Process Corner) + Requirement: 24.000ns (mmcm_ps_clk_bufg_in rise@24.000ns - mmcm_ps_clk_bufg_in rise@0.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.872ns = ( 23.128 - 24.000 ) + Source Clock Delay (SCD): 0.040ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.108ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.204ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.584 0.040 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.518 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.334 0.852 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock mmcm_ps_clk_bufg_in rise edge) + 24.000 24.000 r + E3 0.000 24.000 r CLK100MHZ (IN) + net (fo=0) 0.000 24.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 25.411 r input_clock/O + net (fo=1, unplaced) 0.439 25.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 20.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 21.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 21.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 22.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 22.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 22.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 22.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 23.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.616 21.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.763 22.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.091 22.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.439 23.128 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + clock pessimism 0.767 23.895 + clock uncertainty -0.108 23.787 + FDPE (Setup_fdpe_C_D) -0.220 23.567 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg + ------------------------------------------------------------------- + required time 23.567 + arrival time -0.852 + ------------------------------------------------------------------- + slack 22.715 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.152ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + (rising edge-triggered cell FDPE clocked by mmcm_ps_clk_bufg_in {rise@0.000ns fall@12.000ns period=24.000ns}) + Path Group: mmcm_ps_clk_bufg_in + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (mmcm_ps_clk_bufg_in rise@0.000ns - mmcm_ps_clk_bufg_in rise@0.000ns) + Data Path Delay: 0.288ns (logic 0.147ns (51.079%) route 0.141ns (48.921%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.359ns + Source Clock Delay (SCD): -0.413ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.114 -0.413 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.266 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r_reg[11]/Q + net (fo=1, unplaced) 0.141 -0.125 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r[11] + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/D + ------------------------------------------------------------------- ------------------- + + (clock mmcm_ps_clk_bufg_in rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_ps_clk_bufg_in + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/O + net (fo=13, unplaced) 0.259 -0.359 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk_n_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + clock pessimism 0.091 -0.268 + FDPE (Hold_fdpe_C_D) -0.009 -0.277 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg + ------------------------------------------------------------------- + required time 0.277 + arrival time -0.125 + ------------------------------------------------------------------- + slack 0.152 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: mmcm_ps_clk_bufg_in +Waveform(ns): { 0.000 12.000 } +Period(ns): 24.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 24.000 21.845 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.u_bufg_mmcm_ps_clk/I +Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 24.000 189.360 MMCME2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0 +Low Pulse Width Slow FDPE/C n/a 0.500 12.000 11.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C +High Pulse Width Slow FDPE/C n/a 0.500 12.000 11.500 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rst_sync_r1_reg/C + + + +--------------------------------------------------------------------------------------------------- +From Clock: pll_clkfbout + To Clock: pll_clkfbout + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 4.751ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: pll_clkfbout +Waveform(ns): { 0.000 3.000 } +Period(ns): 6.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 6.000 4.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBOUT +Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 6.000 46.633 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKFBIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: sync_pulse + +Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +PW : 0 Failing Endpoints, Worst Slack 1.750ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: sync_pulse +Waveform(ns): { 1.312 4.312 } +Period(ns): 48.000 +Sources: { ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 48.000 46.751 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 48.000 112.000 PLLE2_ADV_X1Y1 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 +High Pulse Width Slow PHASER_OUT_PHY/SYNCIN n/a 1.250 3.000 1.750 PHASER_OUT_PHY_X1Y4 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/SYNCIN + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 10.968ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 10.968ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: core_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 12.000ns (MaxDelay Path 12.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 12.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + FDRE (Prop_fdre_C_Q) 0.478 0.478 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, unplaced) 0.334 0.812 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 12.000 12.000 + FDRE (Setup_fdre_C_D) -0.220 11.780 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 11.780 + arrival time -0.812 + ------------------------------------------------------------------- + slack 10.968 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: ref_raw + +Setup : 0 Failing Endpoints, Worst Slack 18.960ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 18.960ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Path Group: ref_raw + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 1.084ns (logic 0.773ns (71.310%) route 0.311ns (28.690%)) + Logic Levels: 1 (LUT1=1) + Timing Exception: MaxDelay Path 20.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + FDPE (Prop_fdpe_C_Q) 0.478 0.478 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=1, unplaced) 0.311 0.789 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.084 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst/O + net (fo=50, unplaced) 0.000 1.084 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + FDRE (Setup_fdre_C_D) 0.044 20.044 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1_reg + ------------------------------------------------------------------- + required time 20.044 + arrival time -1.084 + ------------------------------------------------------------------- + slack 18.960 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 12.367ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 44.683ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 12.367ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 4.867ns (logic 4.064ns (83.504%) route 0.803ns (16.496%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.801ns = ( 2.301 - 1.500 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.803 1.539 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUFDISABLE + T3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.771 4.310 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 4.310 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y77 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 5.125 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 5.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, unplaced) 0.439 18.350 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 12.970 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 13.732 sys_raw + BUFG (Prop_bufg_I_O) 0.091 13.823 f sys_buffer/O + net (fo=1, unplaced) 0.763 14.586 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 14.669 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.577 15.246 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 16.870 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.431 17.301 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/CLKB0 + ILOGIC_X1Y77 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.576 17.877 + clock uncertainty -0.220 17.657 + ILOGIC_X1Y77 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.492 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.492 + arrival time -5.125 + ------------------------------------------------------------------- + slack 12.367 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 44.683ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.466ns (logic 1.128ns (76.922%) route 0.338ns (23.078%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.508ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.933ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.259ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, unplaced) 0.114 60.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 58.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 58.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 58.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 59.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 59.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 59.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 59.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 59.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 59.684 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 59.831 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.338 60.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq/IBUFDISABLE + U4 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.738 60.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 60.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/mem_dq_in[6] + IDELAY_X1Y84 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.151 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 61.151 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/data_in_dly_7 + ILOGIC_X1Y84 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, unplaced) 0.259 15.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 13.285 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 13.642 sys_raw + BUFG (Prop_bufg_I_O) 0.029 13.671 r sys_buffer/O + net (fo=1, unplaced) 0.356 14.027 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.080 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.269 14.349 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/freq_refclk + PHASER_IN_PHY_X1Y6 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.730 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.203 15.933 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y84 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.259 16.192 + clock uncertainty 0.220 16.412 + ILOGIC_X1Y84 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.468 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.468 + arrival time 61.151 + ------------------------------------------------------------------- + slack 44.683 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_pll_i + To Clock: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + +Setup : 0 Failing Endpoints, Worst Slack 12.374ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 44.679ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 12.374ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + (falling edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 16.500ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall@16.500ns - clk_pll_i rise@0.000ns) + Data Path Delay: 4.867ns (logic 4.064ns (83.504%) route 0.803ns (16.496%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.126ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.809ns = ( 2.309 - 1.500 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 0.737 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.803 1.539 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq/IBUFDISABLE + L4 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 2.771 4.310 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 4.310 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[1] + IDELAY_X1Y89 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.815 5.125 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 5.125 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_2 + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk fall edge) + 16.500 16.500 f + E3 0.000 16.500 f CLK100MHZ (IN) + net (fo=0) 0.000 16.500 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 17.911 f input_clock/O + net (fo=1, unplaced) 0.439 18.350 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 12.970 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 13.732 sys_raw + BUFG (Prop_bufg_I_O) 0.091 13.823 f sys_buffer/O + net (fo=1, unplaced) 0.763 14.586 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.083 14.669 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.567 15.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.624 16.860 f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.448 17.309 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/CLKB0_4 + ILOGIC_X1Y89 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq/CLKB (IS_INVERTED) + clock pessimism 0.576 17.884 + clock uncertainty -0.220 17.665 + ILOGIC_X1Y89 ISERDESE2 (Setup_iserdese2_CLKB_DDLY) + -0.165 17.500 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time 17.500 + arrival time -5.125 + ------------------------------------------------------------------- + slack 12.374 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 44.679ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + (rising edge-triggered cell ISERDESE2 clocked by u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: -45.000ns (u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise@15.000ns - clk_pll_i rise@60.000ns) + Data Path Delay: 1.466ns (logic 1.128ns (76.922%) route 0.338ns (23.078%)) + Logic Levels: 2 (IBUF_INTERMDISABLE=1 IDELAYE2=1) + Clock Path Skew: 1.512ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.937ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.259ns + Clock Uncertainty: 0.220ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.111ns + Phase Error (PE): 0.154ns + Timing Exception: MultiCycle Path Setup -end 6 Hold -start 5 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 60.000 60.000 r + E3 0.000 60.000 r CLK100MHZ (IN) + net (fo=0) 0.000 60.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 60.250 r input_clock/O + net (fo=1, unplaced) 0.114 60.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 58.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 58.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 58.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 59.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 59.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 59.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 59.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 59.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 59.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 59.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 59.684 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/last_master_r_reg[2] + FDRE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.147 59.831 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/mc0/mc_read_idle_r_reg/Q + net (fo=40, unplaced) 0.338 60.170 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq/IBUFDISABLE + K3 IBUF_INTERMDISABLE (Prop_ibuf_intermdisable_IBUFDISABLE_O) + 0.738 60.908 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq/IBUF/O + net (fo=2, estimated) 0.000 60.908 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/mem_dq_in[6] + IDELAY_X1Y96 IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT) + 0.243 61.151 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_dq.idelaye2/DATAOUT + net (fo=1, estimated) 0.000 61.151 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/data_in_dly_7 + ILOGIC_X1Y96 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/DDLY + ------------------------------------------------------------------- ------------------- + + (clock u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk rise edge) + 15.000 15.000 r + E3 0.000 15.000 r CLK100MHZ (IN) + net (fo=0) 0.000 15.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 15.438 r input_clock/O + net (fo=1, unplaced) 0.259 15.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 13.285 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 13.642 sys_raw + BUFG (Prop_bufg_I_O) 0.029 13.671 r sys_buffer/O + net (fo=1, unplaced) 0.356 14.027 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + 0.053 14.080 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT0 + net (fo=7, estimated) 0.265 14.345 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/freq_refclk + PHASER_IN_PHY_X1Y7 PHASER_IN_PHY (Prop_phaser_in_phy_FREQREFCLK_ICLK) + 1.381 15.725 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in/ICLK + net (fo=16, estimated) 0.211 15.937 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.iserdesdq_0 + ILOGIC_X1Y96 ISERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq/CLK + clock pessimism 0.259 16.196 + clock uncertainty 0.220 16.416 + ILOGIC_X1Y96 ISERDESE2 (Hold_iserdese2_CLK_DDLY) + 0.056 16.472 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.iserdesdq + ------------------------------------------------------------------- + required time -16.472 + arrival time 61.151 + ------------------------------------------------------------------- + slack 44.679 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: sync_pulse + To Clock: mem_refclk + +Setup : 0 Failing Endpoints, Worst Slack 1.277ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.910ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 1.277ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 1.687ns (mem_refclk rise@6.000ns - sync_pulse fall@4.312ns) + Data Path Delay: 0.621ns (logic 0.000ns (0.000%) route 0.621ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.590ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.241ns = ( 4.759 - 6.000 ) + Source Clock Delay (SCD): -1.255ns = ( 3.057 - 4.312 ) + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse fall edge) + 4.312 4.312 f + E3 0.000 4.312 f CLK100MHZ (IN) + net (fo=0) 0.000 4.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 5.794 f input_clock/O + net (fo=1, unplaced) 0.584 6.378 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 1.267 f clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 2.070 sys_raw + BUFG (Prop_bufg_I_O) 0.096 2.166 f sys_buffer/O + net (fo=1, unplaced) 0.803 2.969 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.088 3.057 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, estimated) 0.621 3.678 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.590 4.759 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism 0.576 5.335 + clock uncertainty -0.198 5.137 + PHY_CONTROL_X1Y1 PHY_CONTROL (Setup_phy_control_MEMREFCLK_SYNCIN) + -0.182 4.955 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 4.955 + arrival time -3.678 + ------------------------------------------------------------------- + slack 1.277 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.910ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + (clock source 'sync_pulse' {rise@1.312ns fall@4.312ns period=48.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + (rising edge-triggered cell PHY_CONTROL clocked by mem_refclk {rise@0.000ns fall@1.500ns period=3.000ns}) + Path Group: mem_refclk + Path Type: Hold (Min at Slow Process Corner) + Requirement: -1.312ns (mem_refclk rise@0.000ns - sync_pulse rise@1.312ns) + Data Path Delay: 0.590ns (logic 0.000ns (0.000%) route 0.590ns (100.000%)) + Logic Levels: 0 + Clock Path Skew: 0.621ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.634ns + Source Clock Delay (SCD): -1.831ns = ( -0.519 - 1.312 ) + Clock Pessimism Removal (CPR): 0.576ns + Clock Uncertainty: 0.198ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.139ns + Phase Error (PE): 0.120ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sync_pulse rise edge) + 1.312 1.312 r + E3 0.000 1.312 r CLK100MHZ (IN) + net (fo=0) 0.000 1.312 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 2.724 r input_clock/O + net (fo=1, unplaced) 0.439 3.163 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 -2.218 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 -1.455 sys_raw + BUFG (Prop_bufg_I_O) 0.091 -1.364 r sys_buffer/O + net (fo=1, unplaced) 0.763 -0.602 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) + 0.083 -0.519 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT2 + net (fo=7, estimated) 0.590 0.071 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/sync_pulse + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/SYNCIN + ------------------------------------------------------------------- ------------------- + + (clock mem_refclk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.621 -0.634 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/mem_refclk + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/MEMREFCLK + clock pessimism -0.576 -1.210 + clock uncertainty 0.198 -1.012 + PHY_CONTROL_X1Y1 PHY_CONTROL (Hold_phy_control_MEMREFCLK_SYNCIN) + 0.174 -0.838 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + ------------------------------------------------------------------- + required time 0.838 + arrival time 0.071 + ------------------------------------------------------------------- + slack 0.910 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk + To Clock: oserdes_clkdiv + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 11 Failing Endpoints, Worst Slack -0.247ns, Total Violation -1.473ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv rise@12.000ns - oserdes_clk rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.271ns = ( 13.271 - 12.000 ) + Source Clock Delay (SCD): 1.793ns = ( 10.793 - 9.000 ) + Clock Pessimism Removal (CPR): 0.670ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, unplaced) 0.584 11.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 5.955 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 6.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 6.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 7.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 7.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 8.359 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 10.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.131 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 11.131 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/po_rd_enable + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 10.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.000 13.271 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clkdiv + OUT_FIFO_X1Y4 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo/RDCLK + clock pessimism 0.670 13.941 + clock uncertainty -0.054 13.887 + OUT_FIFO_X1Y4 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo + ------------------------------------------------------------------- + required time 13.236 + arrival time -11.131 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.247ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv rise@0.000ns - oserdes_clk rise@0.000ns) + Data Path Delay: 0.602ns (logic 0.272ns (45.211%) route 0.330ns (54.789%)) + Logic Levels: 0 + Clock Path Skew: 0.289ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.782ns + Source Clock Delay (SCD): 1.690ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OSERDESRST + net (fo=11, estimated) 0.330 2.292 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y59 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/mem_refclk + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK + PHASER_OUT_PHY_X1Y4 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLKDIV + net (fo=12, estimated) 0.201 1.782 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y59 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.979 + OLOGIC_X1Y59 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.538 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.538 + arrival time 2.292 + ------------------------------------------------------------------- + slack -0.247 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_1 + To Clock: oserdes_clkdiv_1 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 12 Failing Endpoints, Worst Slack -0.268ns, Total Violation -2.486ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_1 rise@12.000ns - oserdes_clk_1 rise@9.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.260ns = ( 13.260 - 12.000 ) + Source Clock Delay (SCD): 1.782ns = ( 10.782 - 9.000 ) + Clock Pessimism Removal (CPR): 0.669ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 9.000 9.000 r + E3 0.000 9.000 r CLK100MHZ (IN) + net (fo=0) 0.000 9.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 10.482 r input_clock/O + net (fo=1, unplaced) 0.584 11.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 5.955 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 6.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 6.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 7.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 7.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 8.348 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 10.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 11.120 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 11.120 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/po_rd_enable + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 10.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 13.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 13.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.000 13.260 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clkdiv + OUT_FIFO_X1Y5 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/RDCLK + clock pessimism 0.669 13.930 + clock uncertainty -0.054 13.876 + OUT_FIFO_X1Y5 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 13.225 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo + ------------------------------------------------------------------- + required time 13.225 + arrival time -11.120 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.268ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_1 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_1 {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: oserdes_clkdiv_1 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_1 rise@0.000ns - oserdes_clk_1 rise@0.000ns) + Data Path Delay: 0.576ns (logic 0.272ns (47.195%) route 0.304ns (52.805%)) + Logic Levels: 0 + Clock Path Skew: 0.285ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.773ns + Source Clock Delay (SCD): 1.685ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.957 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OSERDESRST + net (fo=12, estimated) 0.304 2.262 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y73 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_1 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/mem_refclk + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLK + PHASER_OUT_PHY_X1Y5 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out/OCLKDIV + net (fo=13, estimated) 0.197 1.773 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y73 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.970 + OLOGIC_X1Y73 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.529 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/output_[8].oserdes_dq_.sdr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.529 + arrival time 2.262 + ------------------------------------------------------------------- + slack -0.268 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_2 + To Clock: oserdes_clkdiv_2 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 10 Failing Endpoints, Worst Slack -0.274ns, Total Violation -2.156ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_2 rise@6.000ns - oserdes_clk_2 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.271ns = ( 7.271 - 6.000 ) + Source Clock Delay (SCD): 1.793ns = ( 4.793 - 3.000 ) + Clock Pessimism Removal (CPR): 0.670ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, unplaced) 0.584 5.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -0.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 0.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 0.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 1.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 1.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.614 2.359 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 4.793 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.131 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 5.131 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/po_rd_enable + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.583 4.752 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.123 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.271 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 7.271 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clkdiv + OUT_FIFO_X1Y6 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo/RDCLK + clock pessimism 0.670 7.941 + clock uncertainty -0.054 7.887 + OUT_FIFO_X1Y6 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.236 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo + ------------------------------------------------------------------- + required time 7.236 + arrival time -5.131 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.274ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_2 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_2 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_2 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_2 rise@0.000ns - oserdes_clk_2 rise@0.000ns) + Data Path Delay: 0.574ns (logic 0.272ns (47.403%) route 0.302ns (52.597%)) + Logic Levels: 0 + Clock Path Skew: 0.289ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.781ns + Source Clock Delay (SCD): 1.690ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.259 -0.402 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.690 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.962 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OSERDESRST + net (fo=10, estimated) 0.302 2.264 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_2 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.272 -0.648 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_refclk + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.493 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLK + PHASER_OUT_PHY_X1Y6 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.581 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out/OCLKDIV + net (fo=11, estimated) 0.201 1.781 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y77 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.979 + OLOGIC_X1Y77 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.538 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/output_[2].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.538 + arrival time 2.264 + ------------------------------------------------------------------- + slack -0.274 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: oserdes_clk_3 + To Clock: oserdes_clkdiv_3 + +Setup : 0 Failing Endpoints, Worst Slack 2.105ns, Total Violation 0.000ns +Hold : 10 Failing Endpoints, Worst Slack -0.197ns, Total Violation -1.058ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 2.105ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + (rising edge-triggered cell OUT_FIFO clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 3.000ns (oserdes_clkdiv_3 rise@6.000ns - oserdes_clk_3 rise@3.000ns) + Data Path Delay: 0.338ns (logic 0.338ns (100.000%) route 0.000ns (0.000%)) + Logic Levels: 0 + Clock Path Skew: 0.148ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 1.260ns = ( 7.260 - 6.000 ) + Source Clock Delay (SCD): 1.782ns = ( 4.782 - 3.000 ) + Clock Pessimism Removal (CPR): 0.669ns + Clock Uncertainty: 0.054ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.081ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 3.000 3.000 r + E3 0.000 3.000 r CLK100MHZ (IN) + net (fo=0) 0.000 3.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 4.482 r input_clock/O + net (fo=1, unplaced) 0.584 5.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -0.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 0.758 sys_raw + BUFG (Prop_bufg_I_O) 0.096 0.854 r sys_buffer/O + net (fo=1, unplaced) 0.803 1.657 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.088 1.745 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.603 2.348 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.434 4.782 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_RDENABLE) + 0.338 5.120 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/RDENABLE + net (fo=1, estimated) 0.000 5.120 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/po_rd_enable + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDEN + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 6.000 6.000 r + E3 0.000 6.000 r CLK100MHZ (IN) + net (fo=0) 0.000 6.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 7.411 r input_clock/O + net (fo=1, unplaced) 0.439 7.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 2.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 3.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 3.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 4.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.083 4.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.573 4.742 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.371 7.112 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.148 7.260 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.000 7.260 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clkdiv + OUT_FIFO_X1Y7 OUT_FIFO r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo/RDCLK + clock pessimism 0.669 7.930 + clock uncertainty -0.054 7.876 + OUT_FIFO_X1Y7 OUT_FIFO (Setup_out_fifo_RDCLK_RDEN) + -0.651 7.225 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo + ------------------------------------------------------------------- + required time 7.225 + arrival time -5.120 + ------------------------------------------------------------------- + slack 2.105 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -0.197ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + (rising edge-triggered cell PHASER_OUT_PHY clocked by oserdes_clk_3 {rise@0.000ns fall@1.500ns period=3.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST + (rising edge-triggered cell OSERDESE2 clocked by oserdes_clkdiv_3 {rise@0.000ns fall@3.000ns period=6.000ns}) + Path Group: oserdes_clkdiv_3 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (oserdes_clkdiv_3 rise@0.000ns - oserdes_clk_3 rise@0.000ns) + Data Path Delay: 0.658ns (logic 0.272ns (41.330%) route 0.386ns (58.670%)) + Logic Levels: 0 + Clock Path Skew: 0.296ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.784ns + Source Clock Delay (SCD): 1.685ns + Clock Pessimism Removal (CPR): -0.197ns + Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1 + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock oserdes_clk_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.254 -0.407 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.092 1.685 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + ------------------------------------------------------------------- ------------------- + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OSERDESRST) + 0.272 1.957 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OSERDESRST + net (fo=10, estimated) 0.386 2.343 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/po_oserdes_rst + OLOGIC_X1Y88 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/RST + ------------------------------------------------------------------- ------------------- + + (clock oserdes_clkdiv_3 rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT1 + net (fo=7, estimated) 0.268 -0.653 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/mem_refclk + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_MEMREFCLK_OCLK) + 2.141 1.488 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLK + PHASER_OUT_PHY_X1Y7 PHASER_OUT_PHY (Prop_phaser_out_phy_OCLK_OCLKDIV) + 0.088 1.576 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out/OCLKDIV + net (fo=11, estimated) 0.208 1.784 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/oserdes_clkdiv + OLOGIC_X1Y88 OSERDESE2 r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i/CLKDIV + clock pessimism 0.197 1.981 + OLOGIC_X1Y88 OSERDESE2 (Hold_oserdese2_CLKDIV_RST) + 0.559 2.540 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/output_[1].oserdes_dq_.ddr.oserdes_dq_i + ------------------------------------------------------------------- + required time -2.540 + arrival time 2.343 + ------------------------------------------------------------------- + slack -0.197 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: core_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 38.968ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 38.968ns (required time - arrival time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Slow Process Corner) + Requirement: 40.000ns (MaxDelay Path 40.000ns) + Data Path Delay: 0.812ns (logic 0.478ns (58.867%) route 0.334ns (41.133%)) + Logic Levels: 0 + Timing Exception: MaxDelay Path 40.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + FDRE (Prop_fdre_C_Q) 0.478 0.478 r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, unplaced) 0.334 0.812 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + FDRE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + ------------------------------------------------------------------- ------------------- + + max delay 40.000 40.000 + FDRE (Setup_fdre_C_D) -0.220 39.780 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + ------------------------------------------------------------------- + required time 39.780 + arrival time -0.812 + ------------------------------------------------------------------- + slack 38.968 + + + + + +--------------------------------------------------------------------------------------------------- +From Clock: ref_raw + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 19.759ns, Total Violation 0.000ns +Hold : 12 Failing Endpoints, Worst Slack -1.631ns, Total Violation -19.568ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 19.759ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Setup (Max at Fast Process Corner) + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 0.331ns (logic 0.183ns (55.254%) route 0.148ns (44.746%)) + Logic Levels: 0 + Clock Path Skew: 0.454ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.316ns + Source Clock Delay (SCD): -1.070ns + Clock Pessimism Removal (CPR): -0.301ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -2.411 -1.715 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.356 -1.358 ref_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r ref_buffer/O + net (fo=67, unplaced) 0.259 -1.070 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.183 -0.887 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/Q + net (fo=1, unplaced) 0.148 -0.739 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[0] + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + E3 0.000 20.000 r CLK100MHZ (IN) + net (fo=0) 0.000 20.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 20.250 r input_clock/O + net (fo=1, unplaced) 0.114 20.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 18.586 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 18.925 sys_raw + BUFG (Prop_bufg_I_O) 0.026 18.951 r sys_buffer/O + net (fo=1, unplaced) 0.338 19.289 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 19.339 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 19.453 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 19.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 19.811 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 19.109 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 19.447 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 19.473 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 19.684 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/C + clock pessimism -0.301 19.383 + clock uncertainty -0.245 19.138 + FDRE (Setup_fdre_C_D) -0.119 19.019 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0] + ------------------------------------------------------------------- + required time 19.019 + arrival time 0.739 + ------------------------------------------------------------------- + slack 19.759 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (VIOLATED) : -1.631ns (arrival time - required time) + Source: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + (rising edge-triggered cell FDRE clocked by ref_raw {rise@0.000ns fall@2.500ns period=5.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + (rising edge-triggered cell FDRE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: clk_pll_i + Path Type: Hold (Min at Slow Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - ref_raw rise@0.000ns) + Data Path Delay: 0.702ns (logic 0.385ns (54.820%) route 0.317ns (45.180%)) + Logic Levels: 0 + Clock Path Skew: 2.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.259ns + Source Clock Delay (SCD): -2.238ns + Clock Pessimism Removal (CPR): 0.485ns + Clock Uncertainty: 0.245ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.178ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock ref_raw rise edge) 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r input_clock/O + net (fo=1, unplaced) 0.439 1.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2) + -5.381 -3.530 r clock_mmcm/CLKOUT2 + net (fo=1, unplaced) 0.763 -2.768 ref_raw + BUFG (Prop_bufg_I_O) 0.091 -2.677 r ref_buffer/O + net (fo=67, unplaced) 0.439 -2.238 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/clk_ref_i + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.385 -1.853 r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/xadc_supplied_temperature.temperature_reg[0]/Q + net (fo=1, unplaced) 0.317 -1.535 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_lcl[0] + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r5_reg[11]_0 + FDRE r ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0]/C + clock pessimism -0.485 -0.227 + clock uncertainty 0.245 0.018 + FDRE (Hold_fdre_C_D) 0.077 0.095 ddr_controller/u_arty_ddr3_mig/temp_mon_enabled.u_tempmon/device_temp_sync_r1_reg[0] + ------------------------------------------------------------------- + required time -0.095 + arrival time -1.535 + ------------------------------------------------------------------- + slack -1.631 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: clk_pll_i + To Clock: clk_pll_i + +Setup : 0 Failing Endpoints, Worst Slack 9.663ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.295ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 9.663ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + (recovery check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 12.000ns (clk_pll_i rise@12.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 1.773ns (logic 0.773ns (43.598%) route 1.000ns (56.402%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.653ns = ( 11.347 - 12.000 ) + Source Clock Delay (SCD): 0.259ns + Clock Pessimism Removal (CPR): 0.767ns + Clock Uncertainty: 0.067ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.114ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.111 -3.045 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.803 -2.242 sys_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r sys_buffer/O + net (fo=1, unplaced) 0.803 -1.343 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.088 -1.255 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.584 -0.671 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.127 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.702 -1.443 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.803 -0.640 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.096 -0.544 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.803 0.259 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0_0 + FDPE r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.478 0.737 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8/Q + net (fo=1, unplaced) 0.311 1.048 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep__8_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.343 f ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst_rep__7/O + net (fo=47, unplaced) 0.689 2.032 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_ctl_wren_reg_7 + FDCE f ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 12.000 12.000 r + E3 0.000 12.000 r CLK100MHZ (IN) + net (fo=0) 0.000 12.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 13.411 r input_clock/O + net (fo=1, unplaced) 0.439 13.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -5.381 8.470 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.763 9.232 sys_raw + BUFG (Prop_bufg_I_O) 0.091 9.323 r sys_buffer/O + net (fo=1, unplaced) 0.763 10.086 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.083 10.169 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.439 10.608 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.081 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.763 11.452 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -1.616 9.835 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.763 10.598 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.091 10.689 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.658 11.347 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14]_0 + FDCE r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg/C + clock pessimism 0.767 12.114 + clock uncertainty -0.067 12.046 + FDCE (Recov_fdce_C_CLR) -0.352 11.694 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/phy_reset_n_reg + ------------------------------------------------------------------- + required time 11.694 + arrival time -2.032 + ------------------------------------------------------------------- + slack 9.663 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.295ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (clk_pll_i rise@0.000ns - clk_pll_i rise@0.000ns) + Data Path Delay: 0.299ns (logic 0.147ns (49.136%) route 0.152ns (50.864%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.316ns + Clock Pessimism Removal (CPR): -0.091ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -1.777 -1.414 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.338 -1.075 sys_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r sys_buffer/O + net (fo=1, unplaced) 0.338 -0.711 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.050 -0.661 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.114 -0.547 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.020 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.338 -0.189 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.703 -0.891 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.338 -0.553 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.026 -0.527 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.211 -0.316 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.169 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, unplaced) 0.152 -0.017 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_pll_i rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1) + -2.411 -1.715 r clock_mmcm/CLKOUT1 + net (fo=1, unplaced) 0.356 -1.358 sys_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r sys_buffer/O + net (fo=1, unplaced) 0.356 -0.973 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/mmcm_clk + PLLE2_ADV_X1Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3) + 0.053 -0.920 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 + net (fo=1, unplaced) 0.259 -0.661 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out + BUFH (Prop_bufh_I_O) 0.043 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufh_pll_clk3/O + net (fo=1, unplaced) 0.356 -0.262 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3 + MMCME2_ADV_X1Y1 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) + -0.741 -1.003 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT + net (fo=1, unplaced) 0.356 -0.647 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/clk_pll_i + BUFG (Prop_bufg_I_O) 0.029 -0.618 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/u_bufg_clkdiv0/O + net (fo=6179, unplaced) 0.356 -0.262 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/m_aclk + FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.091 -0.171 + FDCE (Remov_fdce_C_CLR) -0.141 -0.312 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time 0.312 + arrival time -0.017 + ------------------------------------------------------------------- + slack 0.295 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **async_default** +From Clock: core_raw + To Clock: core_raw + +Setup : 0 Failing Endpoints, Worst Slack 34.624ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.295ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 34.624ns (required time - arrival time) + Source: reset_count_reg[10]/C + (rising edge-triggered cell FDRE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + (recovery check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 40.000ns (core_raw rise@40.000ns - core_raw rise@0.000ns) + Data Path Delay: 4.788ns (logic 1.269ns (26.504%) route 3.519ns (73.496%)) + Logic Levels: 5 (LUT2=1 LUT4=2 LUT5=1 LUT6=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.238ns = ( 37.762 - 40.000 ) + Source Clock Delay (SCD): -1.562ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.091ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.168ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r input_clock/O + net (fo=1, unplaced) 0.584 2.066 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.111 -3.045 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.803 -2.242 core_raw + BUFG (Prop_bufg_I_O) 0.096 -2.146 r core_buffer/O + net (fo=35560, unplaced) 0.584 -1.562 clk + FDRE r reset_count_reg[10]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 -1.084 r reset_count_reg[10]/Q + net (fo=2, unplaced) 0.774 -0.310 platform/normalizer/reset_count_reg[10] + LUT4 (Prop_lut4_I1_O) 0.295 -0.015 f platform/normalizer/reset_count[0]_i_7/O + net (fo=1, unplaced) 0.449 0.434 platform/normalizer/reset_count[0]_i_7_n_0 + LUT5 (Prop_lut5_I4_O) 0.124 0.558 f platform/normalizer/reset_count[0]_i_5/O + net (fo=1, unplaced) 0.449 1.007 platform/normalizer/reset_count[0]_i_5_n_0 + LUT6 (Prop_lut6_I5_O) 0.124 1.131 f platform/normalizer/reset_count[0]_i_2/O + net (fo=21, unplaced) 0.510 1.641 platform/normalizer/sel + LUT4 (Prop_lut4_I3_O) 0.124 1.765 f platform/normalizer/FSM_sequential_state[2]_i_1/O + net (fo=900, unplaced) 0.589 2.354 platform/loader/cpu_run_reg_inv_20 + LUT2 (Prop_lut2_I0_O) 0.124 2.478 f platform/loader/in_pipe_v_i_1__0/O + net (fo=3765, unplaced) 0.748 3.226 platform/chip/system/clint_domain/intsource/reg_0/cpu_reset + FDCE f platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 40.000 40.000 r + E3 0.000 40.000 r CLK100MHZ (IN) + net (fo=0) 0.000 40.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r input_clock/O + net (fo=1, unplaced) 0.439 41.850 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.381 36.470 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.763 37.232 core_raw + BUFG (Prop_bufg_I_O) 0.091 37.323 r core_buffer/O + net (fo=35560, unplaced) 0.439 37.762 platform/chip/system/clint_domain/intsource/reg_0/clk + FDCE r platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0]/C + clock pessimism 0.531 38.293 + clock uncertainty -0.091 38.202 + FDCE (Recov_fdce_C_CLR) -0.352 37.850 platform/chip/system/clint_domain/intsource/reg_0/reg_0_reg[0] + ------------------------------------------------------------------- + required time 37.850 + arrival time -3.226 + ------------------------------------------------------------------- + slack 34.624 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.295ns (arrival time - required time) + Source: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + (rising edge-triggered cell FDPE clocked by core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Destination: memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + (removal check against rising-edge clock core_raw {rise@0.000ns fall@20.000ns period=40.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (core_raw rise@0.000ns - core_raw rise@0.000ns) + Data Path Delay: 0.299ns (logic 0.147ns (49.136%) route 0.152ns (50.864%)) + Logic Levels: 0 + Clock Path Skew: 0.145ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -1.070ns + Source Clock Delay (SCD): -0.935ns + Clock Pessimism Removal (CPR): -0.280ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r input_clock/O + net (fo=1, unplaced) 0.114 0.364 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -1.777 -1.414 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.338 -1.075 core_raw + BUFG (Prop_bufg_I_O) 0.026 -1.049 r core_buffer/O + net (fo=35560, unplaced) 0.114 -0.935 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/dest_clk + FDPE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDPE (Prop_fdpe_C_Q) 0.147 -0.788 f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst/arststages_ff_reg[1]/Q + net (fo=3, unplaced) 0.152 -0.636 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 + FDCE f memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock core_raw rise edge) + 0.000 0.000 r + E3 0.000 0.000 r CLK100MHZ (IN) + net (fo=0) 0.000 0.000 CLK100MHZ + E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r input_clock/O + net (fo=1, unplaced) 0.259 0.697 clk_in + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -2.411 -1.715 r clock_mmcm/CLKOUT0 + net (fo=1, unplaced) 0.356 -1.358 core_raw + BUFG (Prop_bufg_I_O) 0.029 -1.329 r core_buffer/O + net (fo=35560, unplaced) 0.259 -1.070 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/s_aclk + FDCE r memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0]/C + clock pessimism 0.280 -0.790 + FDCE (Remov_fdce_C_CLR) -0.141 -0.931 memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.wr_rst_rd_ext_reg[0] + ------------------------------------------------------------------- + required time 0.931 + arrival time -0.636 + ------------------------------------------------------------------- + slack 0.295 + + + + + +--------------------------------------------------------------------------------------------------- +Path Group: **default** +From Clock: clk_pll_i + To Clock: + +Setup : 0 Failing Endpoints, Worst Slack 3.113ns, Total Violation 0.000ns +Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 3.113ns (required time - arrival time) + Source: ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + (rising edge-triggered cell FDPE clocked by clk_pll_i {rise@0.000ns fall@6.000ns period=12.000ns}) + Destination: ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + Path Group: **default** + Path Type: Max at Slow Process Corner + Requirement: 5.000ns (MaxDelay Path 5.000ns) + Data Path Delay: 1.887ns (logic 0.773ns (40.968%) route 1.114ns (59.032%)) + Logic Levels: 1 (LUT1=1) + Output Delay: 0.000ns + Timing Exception: MaxDelay Path 5.000ns -datapath_only + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + 0.000 0.000 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C + FDPE (Prop_fdpe_C_Q) 0.478 0.478 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/Q + net (fo=1, unplaced) 0.311 0.789 ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep_n_0 + LUT1 (Prop_lut1_I0_O) 0.295 1.084 r ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_inst/O + net (fo=50, unplaced) 0.803 1.887 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i_0 + PHY_CONTROL_X1Y1 PHY_CONTROL r ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i/RESET + ------------------------------------------------------------------- ------------------- + + max delay 5.000 5.000 + PHY_CONTROL_X1Y1 PHY_CONTROL 0.000 5.000 ddr_controller/u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i + output delay -0.000 5.000 + ------------------------------------------------------------------- + required time 5.000 + arrival time -1.887 + ------------------------------------------------------------------- + slack 3.113 + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-utilization.rpt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-utilization.rpt new file mode 100644 index 0000000..2cf4e01 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/synth-utilization.rpt @@ -0,0 +1,233 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024 +| Date : Mon Oct 12 20:30:48 2026 +| Host : amax running 64-bit Ubuntu 24.04 LTS +| Command : report_utilization -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synth-utilization.rpt +| Design : toy_a7_top +| Device : xc7a100tcsg324-1 +| Speed File : -1 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+-------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+-------+-------+------------+-----------+-------+ +| Slice LUTs* | 57555 | 0 | 0 | 63400 | 90.78 | +| LUT as Logic | 53496 | 0 | 0 | 63400 | 84.38 | +| LUT as Memory | 4059 | 0 | 0 | 19000 | 21.36 | +| LUT as Distributed RAM | 3680 | 0 | | | | +| LUT as Shift Register | 379 | 0 | | | | +| Slice Registers | 34174 | 0 | 0 | 126800 | 26.95 | +| Register as Flip Flop | 34174 | 0 | 0 | 126800 | 26.95 | +| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 | +| F7 Muxes | 689 | 0 | 0 | 31700 | 2.17 | +| F8 Muxes | 112 | 0 | 0 | 15850 | 0.71 | ++----------------------------+-------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 194 | Yes | - | Set | +| 140 | Yes | - | Reset | +| 580 | Yes | Set | - | +| 33260 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 31 | 0 | 0 | 135 | 22.96 | +| RAMB36/FIFO* | 27 | 0 | 0 | 135 | 20.00 | +| RAMB36E1 only | 27 | | | | | +| RAMB18 | 8 | 0 | 0 | 270 | 2.96 | +| RAMB18E1 only | 8 | | | | | ++-------------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| DSPs | 117 | 0 | 0 | 240 | 48.75 | +| DSP48E1 only | 117 | | | | | ++----------------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 61 | 61 | 0 | 210 | 29.05 | +| IOB Master Pads | 29 | | | | | +| IOB Slave Pads | 29 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 | +| PHY_CONTROL | 1 | 1 | 0 | 6 | 16.67 | +| PHASER_REF | 1 | 1 | 0 | 6 | 16.67 | +| OUT_FIFO | 4 | 4 | 0 | 24 | 16.67 | +| IN_FIFO | 2 | 2 | 0 | 24 | 8.33 | +| IDELAYCTRL | 1 | 0 | 0 | 6 | 16.67 | +| IBUFDS | 0 | 0 | 0 | 202 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 4 | 4 | 0 | 24 | 16.67 | +| PHASER_OUT_PHY only | 4 | 4 | | | | +| PHASER_IN/PHASER_IN_PHY | 2 | 2 | 0 | 24 | 8.33 | +| PHASER_IN_PHY only | 2 | 2 | | | | +| IDELAYE2/IDELAYE2_FINEDELAY | 16 | 16 | 0 | 300 | 5.33 | +| IDELAYE2 only | 16 | 16 | | | | +| ILOGIC | 16 | 16 | 0 | 210 | 7.62 | +| ISERDES | 16 | 16 | 0 | 210 | | +| OLOGIC | 46 | 46 | 0 | 210 | 21.90 | +| OUTFF_ODDR_Register | 3 | 3 | | | | +| TFF_ODDR_Register | 2 | 2 | | | | +| OSERDES | 43 | 43 | 0 | 210 | | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 7 | 0 | 0 | 32 | 21.88 | +| BUFIO | 0 | 0 | 0 | 24 | 0.00 | +| MMCME2_ADV | 2 | 1 | 0 | 6 | 33.33 | +| PLLE2_ADV | 1 | 1 | 0 | 6 | 16.67 | +| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 | +| BUFHCE | 1 | 0 | 0 | 96 | 1.04 | +| BUFR | 0 | 0 | 0 | 24 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+--------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+--------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 1 | 0 | 0 | 1 | 100.00 | ++-------------+------+-------+------------+-----------+--------+ + + +7. Primitives +------------- + ++--------------------------+-------+---------------------+ +| Ref Name | Used | Functional Category | ++--------------------------+-------+---------------------+ +| FDRE | 33260 | Flop & Latch | +| LUT6 | 19737 | LUT | +| LUT5 | 13793 | LUT | +| LUT3 | 13255 | LUT | +| LUT4 | 11100 | LUT | +| RAMD32 | 5124 | Distributed Memory | +| LUT2 | 4864 | LUT | +| CARRY4 | 2074 | CarryLogic | +| RAMS32 | 1782 | Distributed Memory | +| LUT1 | 1266 | LUT | +| MUXF7 | 689 | MuxFx | +| FDSE | 580 | Flop & Latch | +| SRL16E | 245 | Distributed Memory | +| FDPE | 194 | Flop & Latch | +| FDCE | 140 | Flop & Latch | +| SRLC32E | 134 | Distributed Memory | +| DSP48E1 | 117 | Block Arithmetic | +| RAMD64E | 112 | Distributed Memory | +| MUXF8 | 112 | MuxFx | +| OSERDESE2 | 43 | IO | +| RAMS64E | 42 | Distributed Memory | +| OBUF | 33 | IO | +| RAMB36E1 | 27 | Block Memory | +| OBUFT | 18 | IO | +| ISERDESE2 | 16 | IO | +| IDELAYE2 | 16 | IO | +| IBUF_INTERMDISABLE | 16 | IO | +| RAMB18E1 | 8 | Block Memory | +| BUFG | 7 | Clock | +| ODDR | 5 | IO | +| PHASER_OUT_PHY | 4 | IO | +| OUT_FIFO | 4 | IO | +| OBUFTDS | 4 | IO | +| IBUFDS_INTERMDISABLE_INT | 4 | IO | +| IBUF | 4 | IO | +| INV | 3 | LUT | +| PHASER_IN_PHY | 2 | IO | +| OBUFDS | 2 | IO | +| MMCME2_ADV | 2 | Clock | +| IN_FIFO | 2 | IO | +| XADC | 1 | Others | +| PLLE2_ADV | 1 | Clock | +| PHY_CONTROL | 1 | IO | +| PHASER_REF | 1 | IO | +| IDELAYCTRL | 1 | IO | +| BUFH | 1 | Clock | ++--------------------------+-------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++-------------+------+ +| Ref Name | Used | ++-------------+------+ +| toy_axi_cdc | 1 | +| arty_ddr3 | 1 | ++-------------+------+ + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.jou b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.jou new file mode 100644 index 0000000..61473e2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Mon Oct 12 20:13:53 2026 +# Process ID: 19966 +# Current directory: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31 +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl -log /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log -journal /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou -tclargs /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352 +# Log file: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log +# Journal file: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :800.000 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :661079 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.log new file mode 100644 index 0000000..bb9ec4d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/implementation/vivado.log @@ -0,0 +1,5919 @@ +#----------------------------------------------------------- +# Vivado v2024.1 (64-bit) +# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024 +# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024 +# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024 +# Start of session at: Mon Oct 12 20:13:53 2026 +# Process ID: 19966 +# Current directory: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31 +# Command line: vivado -mode batch -source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl -log /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log -journal /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou -tclargs /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352 +# Log file: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.log +# Journal file: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/vivado.jou +# Running On :amax +# Platform :Ubuntu +# Operating System :Ubuntu 24.04 LTS +# Processor Detail :INTEL(R) XEON(R) GOLD 6542Y +# CPU Frequency :800.000 MHz +# CPU Physical cores:48 +# CPU Logical cores :96 +# Host memory :540650 MB +# Swap memory :130443 MB +# Total Virtual :671094 MB +# Available Virtual :661079 MB +#----------------------------------------------------------- +source /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/build_board.tcl +# set root [file dirname [file dirname [file normalize [info script]]]] +# cd $root +# if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +# set flash 0 +# if {[llength $argv]==2} { +# if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} +# set flash 1 +# } +# set out [file normalize [lindex $argv 0]] +# file mkdir $out +# file mkdir $out/ip +# proc phase {name} { +# global out +# set f [open $out/phase.txt w];puts $f $name;close $f +# puts "BOARD_PHASE $name" +# } +# set_param general.maxThreads 8 +# phase CREATE_IP +BOARD_PHASE CREATE_IP +# create_project -in_memory -part xc7a100tcsg324-1 +# set_property target_language Verilog [current_project] +# create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +# set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +INFO: [IP_Flow 19-3484] Absolute path of file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/vendor/mig.prj' provided. It will be converted relative to IP Instance files '../../../../board/vendor/mig.prj' +INFO: [Device 21-403] Loading part xc7a100tcsg324-1 +INFO: [Device 21-9227] Part: xc7a100tcsg324-1 does not have CEAM library. +# create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +# set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +# generate_target all [get_ips] +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'arty_ddr3'... +INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'toy_axi_cdc'... +WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc' +INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'toy_axi_cdc'... +INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'toy_axi_cdc'... +generate_target: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2222.848 ; gain = 275.328 ; free physical = 491940 ; free virtual = 628327 +# report_ip_status -file $out/ip-status.rpt +# phase SYNTH_IP +BOARD_PHASE SYNTH_IP +# synth_ip [get_ips] +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top arty_ddr3 -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 20494 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2658.477 ; gain = 417.715 ; free physical = 491599 ; free virtual = 627992 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-10515] begin/end is required for generate-for in this mode of Verilog [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:253] +INFO: [Synth 8-11241] undeclared symbol 'dbg_sel_po_incdec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1223] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_inc', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1227] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_stg23_sel', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1228] +INFO: [Synth 8-11241] undeclared symbol 'dbg_po_f_dec', assumed default net type 'wire' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:1229] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3.v:70] +INFO: [Synth 8-6157] synthesizing module 'arty_ddr3_mig' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:75] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] + Parameter TCQ bound to: 100 - type: integer + Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string + Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer + Parameter tTEMPSAMPLE bound to: 10000000 - type: integer +INFO: [Synth 8-6157] synthesizing module 'XADC' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] + Parameter INIT_40 bound to: 16'b0001000000000000 + Parameter INIT_41 bound to: 16'b0010111111111111 + Parameter INIT_42 bound to: 16'b0000100000000000 + Parameter INIT_48 bound to: 16'b0000000100000001 + Parameter INIT_49 bound to: 16'b0000000000000000 + Parameter INIT_4A bound to: 16'b0000000100000000 + Parameter INIT_4B bound to: 16'b0000000000000000 + Parameter INIT_4C bound to: 16'b0000000000000000 + Parameter INIT_4D bound to: 16'b0000000000000000 + Parameter INIT_4E bound to: 16'b0000000000000000 + Parameter INIT_4F bound to: 16'b0000000000000000 + Parameter INIT_50 bound to: 16'b1011010111101101 + Parameter INIT_51 bound to: 16'b0101011111100100 + Parameter INIT_52 bound to: 16'b1010000101000111 + Parameter INIT_53 bound to: 16'b1100101000110011 + Parameter INIT_54 bound to: 16'b1010100100111010 + Parameter INIT_55 bound to: 16'b0101001011000110 + Parameter INIT_56 bound to: 16'b1001010101010101 + Parameter INIT_57 bound to: 16'b1010111001001110 + Parameter INIT_58 bound to: 16'b0101100110011001 + Parameter INIT_5C bound to: 16'b0101000100010001 + Parameter SIM_DEVICE bound to: 7SERIES - type: string +INFO: [Synth 8-6155] done synthesizing module 'XADC' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:143027] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] + Parameter TCQ bound to: 100 - type: integer + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter REFCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter SYS_RST_PORT bound to: FALSE - type: string + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: FALSE - type: string +INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75739] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter DIFF_TERM_SYSCLK bound to: TRUE - type: string +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] + Parameter TCQ bound to: 100 - type: integer + Parameter CLKIN_PERIOD bound to: 6000 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter SYSCLK_TYPE bound to: NO_BUFFER - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter MMCM_VCO bound to: 666 - type: integer + Parameter MMCM_MULT_F bound to: 8 - type: integer + Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter RST_ACT_LOW bound to: 1 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter MEM_TYPE bound to: DDR3 - type: string +INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] + Parameter BANDWIDTH bound to: HIGH - type: string + Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: double + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKIN1_PERIOD bound to: 12.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 16.000000 - type: double + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string + Parameter CLKOUT4_CASCADE bound to: FALSE - type: string + Parameter COMPENSATION bound to: BUF_IN - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.000000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82388] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] + Parameter BANDWIDTH bound to: OPTIMIZED - type: string + Parameter CLKFBOUT_MULT bound to: 8 - type: integer + Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 6.000000 - type: double + Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer + Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer + Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT2_DIVIDE bound to: 64 - type: integer + Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double + Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double + Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer + Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double + Parameter CLKOUT4_DIVIDE bound to: 8 - type: integer + Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double + Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double + Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double + Parameter COMPENSATION bound to: INTERNAL - type: string + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer + Parameter REF_JITTER1 bound to: 0.010000 - type: double + Parameter REF_JITTER2 bound to: 0.010000 - type: double + Parameter STARTUP_WAIT bound to: FALSE - type: string +INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114750] +INFO: [Synth 8-6157] synthesizing module 'BUFH' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'BUFH' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2199] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:71] + Parameter TCQ bound to: 100 - type: integer + Parameter DDR3_VDD_OP_VOLT bound to: 135 - type: string + Parameter PAYLOAD_WIDTH bound to: 16 - type: integer + Parameter ADDR_CMD_MODE bound to: 1T - type: string + Parameter AL bound to: 0 - type: string + Parameter BANK_WIDTH bound to: 3 - type: integer + Parameter BM_CNT_WIDTH bound to: 2 - type: integer + Parameter BURST_MODE bound to: 8 - type: string + Parameter BURST_TYPE bound to: SEQ - type: string + Parameter CA_MIRROR bound to: OFF - type: string + Parameter CK_WIDTH bound to: 1 - type: integer + Parameter CL bound to: 5 - type: integer + Parameter COL_WIDTH bound to: 10 - type: integer + Parameter CMD_PIPE_PLUS1 bound to: ON - type: string + Parameter CS_WIDTH bound to: 1 - type: integer + Parameter CKE_WIDTH bound to: 1 - type: integer + Parameter CWL bound to: 5 - type: integer + Parameter DATA_WIDTH bound to: 16 - type: integer + Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer + Parameter DM_WIDTH bound to: 2 - type: integer + Parameter DQ_CNT_WIDTH bound to: 4 - type: integer + Parameter DQ_WIDTH bound to: 16 - type: integer + Parameter DQS_CNT_WIDTH bound to: 1 - type: integer + Parameter DQS_WIDTH bound to: 2 - type: integer + Parameter DRAM_TYPE bound to: DDR3 - type: string + Parameter DRAM_WIDTH bound to: 8 - type: integer + Parameter ECC bound to: OFF - type: string + Parameter ECC_WIDTH bound to: 0 - type: integer + Parameter ECC_TEST bound to: OFF - type: string + Parameter MC_ERR_ADDR_WIDTH bound to: 28 - type: integer + Parameter MASTER_PHY_CTL bound to: 0 - type: integer + Parameter nAL bound to: 0 - type: integer + Parameter nBANK_MACHS bound to: 4 - type: integer + Parameter nCK_PER_CLK bound to: 4 - type: integer + Parameter nCS_PER_RANK bound to: 1 - type: integer + Parameter ORDERING bound to: NORM - type: string + Parameter IBUF_LPWR_MODE bound to: OFF - type: string + Parameter BANK_TYPE bound to: HR_IO - type: string + Parameter DATA_IO_PRIM_TYPE bound to: HR_LP - type: string + Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string + Parameter IODELAY_GRP0 bound to: ARTY_DDR3_IODELAY_MIG0 - type: string + Parameter IODELAY_GRP1 bound to: ARTY_DDR3_IODELAY_MIG1 - type: string + Parameter FPGA_SPEED_GRADE bound to: 1 - type: integer + Parameter OUTPUT_DRV bound to: LOW - type: string + Parameter REG_CTRL bound to: OFF - type: string + Parameter RTT_NOM bound to: 40 - type: string + Parameter RTT_WR bound to: OFF - type: string + Parameter STARVE_LIMIT bound to: 2 - type: integer + Parameter tCK bound to: 3000 - type: integer + Parameter tCKE bound to: 5625 - type: integer + Parameter tFAW bound to: 45000 - type: integer + Parameter tPRDI bound to: 1000000 - type: integer + Parameter tRAS bound to: 36000 - type: integer + Parameter tRCD bound to: 13500 - type: integer + Parameter tREFI bound to: 7800000 - type: integer + Parameter tRFC bound to: 160000 - type: integer + Parameter tRP bound to: 13500 - type: integer + Parameter tRRD bound to: 7500 - type: integer + Parameter tRTP bound to: 7500 - type: integer + Parameter tWTR bound to: 7500 - type: integer + Parameter tZQI bound to: 128000000 - type: integer + Parameter tZQCS bound to: 64 - type: integer + Parameter USER_REFRESH bound to: OFF - type: string + Parameter TEMP_MON_EN bound to: ON - type: string + Parameter WRLVL bound to: ON - type: string + Parameter DEBUG_PORT bound to: OFF - type: string + Parameter CAL_WIDTH bound to: HALF - type: string + Parameter RANK_WIDTH bound to: 1 - type: integer + Parameter RANKS bound to: 1 - type: integer + Parameter ODT_WIDTH bound to: 1 - type: integer + Parameter ROW_WIDTH bound to: 14 - type: integer + Parameter ADDR_WIDTH bound to: 28 - type: integer + Parameter APP_MASK_WIDTH bound to: 16 - type: integer + Parameter APP_DATA_WIDTH bound to: 128 - type: integer + Parameter BYTE_LANES_B0 bound to: 4'b1111 + Parameter BYTE_LANES_B1 bound to: 4'b0000 + Parameter BYTE_LANES_B2 bound to: 4'b0000 + Parameter BYTE_LANES_B3 bound to: 4'b0000 + Parameter BYTE_LANES_B4 bound to: 4'b0000 + Parameter DATA_CTL_B0 bound to: 4'b1100 + Parameter DATA_CTL_B1 bound to: 4'b0000 + Parameter DATA_CTL_B2 bound to: 4'b0000 + Parameter DATA_CTL_B3 bound to: 4'b0000 + Parameter DATA_CTL_B4 bound to: 4'b0000 + Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110111111111111101111111111 + Parameter PHY_1_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000 + Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter ADDR_MAP bound to: 192'b000000000000000000000000000000000000000000000010000000000100000000001001000000000111000000000001000000000101000000000110000000000011000000010000000000010010000000010100000000010001000000011010 + Parameter BANK_MAP bound to: 36'b000000011011000000010111000000010011 + Parameter CAS_MAP bound to: 12'b000000010101 + Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000 + Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 + Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 + Parameter CKE_ODT_AUX bound to: FALSE - type: string + Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011 + Parameter PARITY_MAP bound to: 12'b000000000000 + Parameter RAS_MAP bound to: 12'b000000010110 + Parameter WE_MAP bound to: 12'b000000011000 + Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000011 + Parameter DATA0_MAP bound to: 96'b000000110100000000110010000000111000000000110101000000110001000000110111000000110110000000110011 + Parameter DATA1_MAP bound to: 96'b000000100011000000100110000000100010000000101000000000100101000000100111000000100001000000100100 + Parameter DATA2_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA3_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001000000111001 + Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + Parameter SLOT_0_CONFIG bound to: 8'b00000001 + Parameter SLOT_1_CONFIG bound to: 8'b00000000 + Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string + Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000 + Parameter CALIB_COL_ADD bound to: 12'b000000000000 + Parameter CALIB_BA_ADD bound to: 3'b000 + Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string + Parameter REFCLK_FREQ bound to: 200.000000 - type: double + Parameter USE_CS_PORT bound to: 1 - type: integer + Parameter USE_DM_PORT bound to: 1 - type: integer + Parameter USE_ODT_PORT bound to: 1 - type: integer + Parameter IDELAY_ADJ bound to: OFF - type: string + Parameter FINE_PER_BIT bound to: OFF - type: string + Parameter CENTER_COMP_MODE bound to: OFF - type: string + Parameter PI_VAL_ADJ bound to: OFF - type: string + Parameter SKIP_CALIB bound to: FALSE - type: string + Parameter TAPSPERKCLK bound to: 112 - type: integer + Parameter C_S_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_S_AXI_ADDR_WIDTH bound to: 28 - type: integer + Parameter C_S_AXI_DATA_WIDTH bound to: 128 - type: integer + Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer + Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string + Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000 + Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer + Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer + Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer + Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer + Parameter FPGA_VOLT_TYPE bound to: N - type: string +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:137412] +WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72] +WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:129077] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'OBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96458] +INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96846] +INFO: [Synth 8-6157] synthesizing module 'IOBUF_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6155] done synthesizing module 'IOBUF_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:79002] +INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_INTERMDISABLE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_INTERMDISABLE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78516] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445] +WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76] +INFO: [Synth 8-6157] synthesizing module 'ODDR' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100102] +INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:96472] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68] +INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114436] +INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:78141] +INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114573] +INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100824] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:75752] +INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:80773] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:100709] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70] +INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:2224] +INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114664] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557] +INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:114648] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671] +WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679] +WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_rdlvl' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:79] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203] +WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_prbs_gen' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:92] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +INFO: [Synth 8-226] default block is never used [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_init' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:89] +WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrcal' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:77] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_tempmon' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:69] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_calib_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82] +WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (4) of module 'mig_7series_v4_2_ddr_calib_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mem_intfc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_cmd.v:70] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_wr_data' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_wr_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:131] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ui_rd_data' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403] +WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_rd_data' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:140] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ui_top' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_top.v:71] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc.v:90] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axic_register_slice__parameterized2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:61] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_axi_register_slice' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axi_register_slice.v:63] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_incr_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:64] +INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wrap_cmd' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:97] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_cmd_translator' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_cmd_translator.v:62] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_wr_cmd_fsm' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wr_cmd_fsm.v:76] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_aw_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_aw_channel.v:57] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_w_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:64] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_fifo' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_fifo.v:70] +INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_axi_mc_b_channel' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_b_channel.v:83] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315] +WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140] +WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141] +WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142] +WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143] +WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144] +WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181] +WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153] +WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145] +WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143] +WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680] +WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681] +WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390] +WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143] +WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144] +WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145] +WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92] +WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307] +WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147] +WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193] +WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195] +WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431] +WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198] +WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275] +WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276] +WARNING: [Synth 8-6014] Unused sequential element fine_delay_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:185] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269] +WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270] +WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737] +WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738] +WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739] +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790] +WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791] +WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792] +WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517] +WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628] +WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_max_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1116] +WARNING: [Synth 8-6014] Unused sequential element rank_final_loop[0].final_do_index_reg[0] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:1146] +WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:690] +WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal_hr does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v:131] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940] +WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941] +WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696] +WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697] +WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610] +WARNING: [Synth 8-6014] Unused sequential element sample_cnt_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:156] +WARNING: [Synth 8-6014] Unused sequential element reseed_prbs_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:157] +WARNING: [Synth 8-6014] Unused sequential element lfsr_q_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:174] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_cs1_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4271] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.phy_tmp_odt_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4273] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1421] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_rank_cntr_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1539] +WARNING: [Synth 8-6014] Unused sequential element cnt_pwron_cke_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1781] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1814] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_pre_wait_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1815] +WARNING: [Synth 8-6014] Unused sequential element rnk_ref_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1941] +WARNING: [Synth 8-6014] Unused sequential element read_calib_int_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2720] +WARNING: [Synth 8-6014] Unused sequential element read_calib_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2727] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_rank_done_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2778] +WARNING: [Synth 8-6014] Unused sequential element pi_dqs_found_all_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:2783] +WARNING: [Synth 8-6014] Unused sequential element complex_row0_rd_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3339] +WARNING: [Synth 8-6014] Unused sequential element rdlvl_wr_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3632] +WARNING: [Synth 8-6014] Unused sequential element extend_cal_pat_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3638] +WARNING: [Synth 8-6014] Unused sequential element cnt_init_data_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:3714] +WARNING: [Synth 8-6014] Unused sequential element victim_byte_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:818] +WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr2_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4265] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[1] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[2] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element gen_single_slot_odt.tmp_mr1_r_reg[3] was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4268] +WARNING: [Synth 8-6014] Unused sequential element prech_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1303] +WARNING: [Synth 8-6014] Unused sequential element calib_cmd_wren_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:4229] +WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:534] +WARNING: [Synth 8-6014] Unused sequential element rd_active_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:535] +WARNING: [Synth 8-6014] Unused sequential element pat1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1124] +WARNING: [Synth 8-6014] Unused sequential element early1_detect_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1125] +WARNING: [Synth 8-6014] Unused sequential element rd_mux_sel_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:438] +WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155] +WARNING: [Synth 8-6014] Unused sequential element calib_complete_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:182] +WARNING: [Synth 8-6014] Unused sequential element sample_en_cnt_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:188] +WARNING: [Synth 8-6014] Unused sequential element device_temp_capture_102_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_tempmon.v:290] +WARNING: [Synth 8-6014] Unused sequential element tempmon_sel_pi_incdec_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:883] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:898] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:899] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:900] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:901] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:902] +WARNING: [Synth 8-6014] Unused sequential element ck_addr_cmd_delay_done_r6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:903] +WARNING: [Synth 8-6014] Unused sequential element skip_calib_tap_off.skip_cal_tempmon_samp_en_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:2262] +WARNING: [Synth 8-6014] Unused sequential element wrlvl_final_mux_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:834] +WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673] +WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662] +WARNING: [Synth 8-3848] Net dbg_poc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:335] +WARNING: [Synth 8-3848] Net fine_delay_incdec_pb in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:341] +WARNING: [Synth 8-3848] Net fine_delay_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:342] +WARNING: [Synth 8-3848] Net lim_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:620] +WARNING: [Synth 8-3848] Net lim2init_write_request in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:619] +WARNING: [Synth 8-3848] Net complex_ocal_num_samples_done_r in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:533] +WARNING: [Synth 8-3848] Net complex_ocal_rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:534] +WARNING: [Synth 8-3848] Net complex_victim_inc in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:592] +WARNING: [Synth 8-3848] Net rd_victim_sel in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:588] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_start in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:597] +WARNING: [Synth 8-3848] Net oclk_center_write_resume in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:615] +WARNING: [Synth 8-3848] Net oclkdelay_center_calib_done in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:616] +WARNING: [Synth 8-6014] Unused sequential element app_wdf_rdy_r_copy4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:268] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:191] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_incr_cmd.v:220] +WARNING: [Synth 8-6014] Unused sequential element int_next_pending_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:221] +WARNING: [Synth 8-6014] Unused sequential element sel_first_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_wrap_cmd.v:239] +WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96] +WARNING: [Synth 8-6014] Unused sequential element rd_last_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:216] +WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555] +WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:754] +WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:756] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:758] +WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:760] +WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:763] +WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:766] +WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:768] +WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:771] +WARNING: [Synth 8-3848] Net device_temp_i in module/entity arty_ddr3_mig does not have driver. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/arty_ddr3_mig.v:784] +WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load +WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_multiple[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[1] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port ecc_single[0] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[7] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[6] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[5] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[4] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[3] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[2] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[1] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port app_raw_not_ecc[0] in module mig_7series_v4_2_ui_wr_data is either unconnected or has no load +WARNING: [Synth 8-7129] Port wr_data_addr[4] in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port accept in module mig_7series_v4_2_ui_top is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[11] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[10] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[9] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[8] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[7] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[6] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[5] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[4] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[3] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[2] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[1] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port calib_device_temp[0] in module mig_7series_v4_2_ddr_phy_tempmon is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[99] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[98] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[97] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[96] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[95] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[94] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[93] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[16] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[15] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[14] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[12] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[11] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +WARNING: [Synth 8-7129] Port dbg_phy_wrcal[10] in module mig_7series_v4_2_ddr_phy_wrcal is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491527 ; free virtual = 627929 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491535 ; free virtual = 627937 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2909.984 ; gain = 669.223 ; free physical = 491535 ; free virtual = 627937 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2909.984 ; gain = 0.000 ; free physical = 491540 ; free virtual = 627942 +INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:346] +WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:353] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/arty_ddr3_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/arty_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3019.828 ; gain = 0.000 ; free physical = 491553 ; free virtual = 627970 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 70 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 51 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3019.828 ; gain = 0.000 ; free physical = 491557 ; free virtual = 627975 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3019.828 ; gain = 779.066 ; free physical = 491702 ; free virtual = 628120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491702 ; free virtual = 628120 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc, line 28). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491707 ; free virtual = 628125 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + INIT_IDLE | 0001 | 000 + REQUEST_READ_TEMP | 1000 | 001 + WAIT_FOR_READ | 0100 | 010 + READ | 0010 | 011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + WL_IDLE | 01110 | 00000 + WL_INIT | 10010 | 00001 + WL_INIT_FINE_INC | 01100 | 00010 + WL_INIT_FINE_INC_WAIT1 | 01000 | 00011 + WL_INIT_FINE_INC_WAIT | 01001 | 00100 + WL_INIT_FINE_DEC | 11001 | 00101 + WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001 + WL_INIT_FINE_DEC_WAIT | 11000 | 00110 + WL_WAIT | 00110 | 01000 + WL_EDGE_CHECK | 11011 | 01001 + WL_DQS_CNT | 10100 | 01011 + WL_FINE_DEC | 00000 | 01110 + WL_FINE_DEC_WAIT1 | 00001 | 11010 + WL_FINE_DEC_WAIT | 10001 | 01111 + WL_CORSE_DEC | 10110 | 10100 + WL_CORSE_DEC_WAIT | 11010 | 10101 + WL_CORSE_DEC_WAIT1 | 10101 | 10110 + WL_2RANK_DQS_CNT | 00010 | 01101 + WL_DQS_CHECK | 00011 | 01010 + WL_FINE_INC | 01101 | 00111 + WL_FINE_INC_WAIT | 10011 | 10111 + WL_2RANK_FINAL_TAP | 01111 | 11000 + WL_CORSE_INC | 01011 | 10000 + WL_CORSE_INC_WAIT_TMP | 10000 | 11011 + WL_CORSE_INC_WAIT | 01010 | 10001 + WL_CORSE_INC_WAIT1 | 00111 | 10010 + WL_CORSE_INC_WAIT2 | 00101 | 10011 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + FINE_ADJ_IDLE | 0000 | 0000 + RST_WAIT | 0001 | 0011 + FINE_ADJ_DONE | 0010 | 1111 + RST_POSTWAIT | 0011 | 0001 + RST_POSTWAIT1 | 0100 | 0010 + FINE_ADJ_INIT | 0101 | 0100 + FINE_INC | 0110 | 0101 + FINE_INC_WAIT | 0111 | 0110 + FINE_INC_PREWAIT | 1000 | 0111 + DETECT_PREWAIT | 1001 | 1000 + DETECT_DQSFOUND | 1010 | 1001 + FINE_DEC | 1011 | 1011 + FINE_DEC_WAIT | 1100 | 1100 + FINE_DEC_PREWAIT | 1101 | 1101 + FINAL_WAIT | 1110 | 1110 + PRECH_WAIT | 1111 | 1010 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal_hr' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + CAL1_IDLE | 00000000000000000000000000010000000 | 000000 + CAL1_NEW_DQS_WAIT | 00000000000000000000010000000000000 | 000001 + CAL1_STORE_FIRST_WAIT | 00000000000000000010000000000000000 | 000010 + CAL1_PAT_DETECT | 00000000000000100000000000000000000 | 000011 + CAL1_DQ_IDEL_TAP_INC | 00000000000000000000000000000000100 | 000100 +CAL1_DQ_IDEL_TAP_INC_WAIT | 00000000000000000000000000000001000 | 000101 + CAL1_MPR_PAT_DETECT | 00000000000000000000000010000000000 | 011111 + CAL1_VALID_WAIT | 10000000000000000000000000000000000 | 011110 + CAL1_DETECT_EDGE | 00000000000001000000000000000000000 | 001000 + CAL1_CALC_IDEL | 00000100000000000000000000000000000 | 001011 + CAL1_CENTER_WAIT | 00000000000000000000000000000000001 | 100010 + CAL1_IDEL_DEC_CPT | 00000000000000000000000000000000010 | 001100 + CAL1_DQ_IDEL_TAP_DEC | 00000000000000000001000000000000000 | 000110 +CAL1_DQ_IDEL_TAP_DEC_WAIT | 00100000000000000000000000000000000 | 000111 + CAL1_NEXT_DQS | 00000000000000000000000000000010000 | 001110 + CAL1_REGL_LOAD | 00000000000000000000000000001000000 | 011011 + CAL1_DONE | 00000000000000000000000000000100000 | 001111 + CAL1_NEW_DQS_PREWAIT | 00000000000000000000000000100000000 | 100000 + CAL1_MPR_NEW_DQS_WAIT | 00000000000000000000000001000000000 | 011101 + CAL1_IDEL_DEC_CPT_WAIT | 00000000000000000000100000000000000 | 001101 + CAL1_RD_STOP_FOR_PI_INC | 00000000000000000000000100000000000 | 100001 + CAL1_IDEL_INC_CPT | 00000000000000000000001000000000000 | 001001 + CAL1_IDEL_INC_CPT_WAIT | 00010000000000000000000000000000000 | 001010 + CAL1_RDLVL_ERR | 00000000000010000000000000000000000 | 011100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 00000000001 | 00000000001 + INIT | 00000000010 | 00000000010 + NEUTRAL | 00001000000 | 00001000000 + ONE_DEC | 00010000000 | 00010000000 + TWO_DEC | 00100000000 | 00100000000 + THREE_DEC | 01000000000 | 01000000000 + FOUR_DEC | 10000000000 | 10000000000 + ONE_INC | 00000100000 | 00000100000 + TWO_INC | 00000010000 | 00000010000 + THREE_INC | 00000001000 | 00000001000 + FOUR_INC | 00000000100 | 00000000100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + ZERO | 11 | 10 + ONE | 01 | 11 + TWO | 00 | 01 + iSTATE | 10 | 00 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 3027.832 ; gain = 787.070 ; free physical = 491753 ; free virtual = 628175 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 4 Input 32 Bit Adders := 2 + 3 Input 32 Bit Adders := 1 + 2 Input 28 Bit Adders := 2 + 2 Input 13 Bit Adders := 1 + 2 Input 12 Bit Adders := 15 + 2 Input 11 Bit Adders := 1 + 2 Input 10 Bit Adders := 6 + 2 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 8 + 3 Input 7 Bit Adders := 2 + 2 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 30 + 3 Input 6 Bit Adders := 3 + 2 Input 5 Bit Adders := 37 + 2 Input 4 Bit Adders := 34 + 2 Input 3 Bit Adders := 20 + 3 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 51 + 3 Input 2 Bit Adders := 3 + 4 Input 2 Bit Adders := 5 + 5 Input 2 Bit Adders := 1 + 8 Input 2 Bit Adders := 1 + 2 Input 1 Bit Adders := 5 + 3 Input 1 Bit Adders := 1 + 4 Input 1 Bit Adders := 1 + 5 Input 1 Bit Adders := 1 + 6 Input 1 Bit Adders := 1 + 7 Input 1 Bit Adders := 1 + 8 Input 1 Bit Adders := 1 + 9 Input 1 Bit Adders := 1 ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 144 Bit Registers := 1 + 128 Bit Registers := 5 + 88 Bit Registers := 1 + 80 Bit Registers := 3 + 56 Bit Registers := 1 + 32 Bit Registers := 3 + 30 Bit Registers := 1 + 28 Bit Registers := 6 + 16 Bit Registers := 13 + 15 Bit Registers := 4 + 14 Bit Registers := 6 + 13 Bit Registers := 1 + 12 Bit Registers := 33 + 11 Bit Registers := 1 + 10 Bit Registers := 4 + 9 Bit Registers := 12 + 8 Bit Registers := 15 + 7 Bit Registers := 5 + 6 Bit Registers := 59 + 5 Bit Registers := 46 + 4 Bit Registers := 82 + 3 Bit Registers := 47 + 2 Bit Registers := 66 + 1 Bit Registers := 1542 ++---Muxes : + 2 Input 128 Bit Muxes := 10 + 4 Input 128 Bit Muxes := 1 + 2 Input 127 Bit Muxes := 1 + 2 Input 80 Bit Muxes := 6 + 2 Input 56 Bit Muxes := 1 + 24 Input 35 Bit Muxes := 1 + 2 Input 35 Bit Muxes := 22 + 2 Input 32 Bit Muxes := 1 + 2 Input 30 Bit Muxes := 12 + 4 Input 30 Bit Muxes := 4 + 2 Input 28 Bit Muxes := 11 + 2 Input 21 Bit Muxes := 8 + 2 Input 16 Bit Muxes := 8 + 3 Input 16 Bit Muxes := 1 + 3 Input 14 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 8 + 4 Input 14 Bit Muxes := 1 + 2 Input 12 Bit Muxes := 5 + 12 Input 11 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 1 + 2 Input 10 Bit Muxes := 7 + 4 Input 9 Bit Muxes := 6 + 2 Input 9 Bit Muxes := 18 + 2 Input 8 Bit Muxes := 61 + 5 Input 8 Bit Muxes := 1 + 2 Input 7 Bit Muxes := 64 + 3 Input 7 Bit Muxes := 1 + 4 Input 7 Bit Muxes := 1 + 5 Input 7 Bit Muxes := 2 + 2 Input 6 Bit Muxes := 81 + 4 Input 6 Bit Muxes := 8 + 27 Input 6 Bit Muxes := 4 + 5 Input 6 Bit Muxes := 2 + 16 Input 6 Bit Muxes := 1 + 24 Input 6 Bit Muxes := 5 + 3 Input 6 Bit Muxes := 2 + 2 Input 5 Bit Muxes := 35 + 8 Input 5 Bit Muxes := 2 + 27 Input 5 Bit Muxes := 1 + 58 Input 5 Bit Muxes := 1 + 24 Input 5 Bit Muxes := 1 + 4 Input 5 Bit Muxes := 2 + 3 Input 5 Bit Muxes := 4 + 2 Input 4 Bit Muxes := 67 + 32 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 1 + 7 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 69 + 27 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 1 + 4 Input 3 Bit Muxes := 3 + 8 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 101 + 4 Input 2 Bit Muxes := 7 + 3 Input 2 Bit Muxes := 9 + 8 Input 2 Bit Muxes := 4 + 27 Input 2 Bit Muxes := 1 + 24 Input 2 Bit Muxes := 2 + 5 Input 2 Bit Muxes := 1 + 10 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 491 + 3 Input 1 Bit Muxes := 12 + 8 Input 1 Bit Muxes := 4 + 4 Input 1 Bit Muxes := 204 + 27 Input 1 Bit Muxes := 27 + 5 Input 1 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 21 + 24 Input 1 Bit Muxes := 30 + 10 Input 1 Bit Muxes := 17 + 12 Input 1 Bit Muxes := 4 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731] +WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232] +WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230] +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[33]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:15 ; elapsed = 00:01:15 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 492131 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +ROM: Preliminary Mapping Report ++------------------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------------------+------------+---------------+----------------+ +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | +|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT | ++------------------------------+------------+---------------+----------------+ + + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 359 of /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc:359] +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491922 ; free virtual = 628371 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:19 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491872 ; free virtual = 628347 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ +|arty_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 | +|arty_ddr3 | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 | ++------------+---------------------------------------------------------------------------------------+-----------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491502 ; free virtual = 628069 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491390 ; free virtual = 628027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:01:24 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491389 ; free virtual = 628027 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491437 ; free virtual = 628074 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491436 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491436 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491435 ; free virtual = 628073 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.pat_data_match_valid_r_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +|arty_ddr3 | u_arty_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 | ++------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + + +Dynamic Shift Register Report: ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ +|dsrl | memory_reg[7] | 4 | 4 | 4 | 0 | 0 | 0 | 0 | +|dsrl__1 | memory_reg[31] | 129 | 129 | 0 | 129 | 0 | 0 | 0 | +|dsrl__2 | memory_reg[29] | 7 | 7 | 0 | 7 | 0 | 0 | 0 | ++------------+----------------+--------+------------+--------+---------+--------+--------+--------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+----------------------+------+ +| |Cell |Count | ++------+----------------------+------+ +|1 |BUFG | 3| +|2 |BUFH | 1| +|3 |BUFIO | 1| +|4 |CARRY4 | 124| +|5 |IDELAYCTRL | 1| +|6 |IDELAYE2 | 16| +|7 |IN_FIFO | 2| +|8 |ISERDESE2 | 16| +|9 |LUT1 | 375| +|10 |LUT2 | 438| +|11 |LUT3 | 1023| +|12 |LUT4 | 905| +|13 |LUT5 | 1361| +|14 |LUT6 | 1262| +|15 |MMCME2_ADV | 1| +|16 |MUXF7 | 28| +|17 |ODDR | 5| +|18 |OSERDESE2 | 43| +|21 |OUT_FIFO | 4| +|23 |PHASER_IN_PHY | 2| +|24 |PHASER_OUT_PHY | 4| +|26 |PHASER_REF | 1| +|27 |PHY_CONTROL | 1| +|28 |PLLE2_ADV | 1| +|29 |RAM32M | 112| +|30 |RAM32X1D | 2| +|31 |SRL16E | 20| +|32 |SRLC32E | 134| +|33 |XADC | 1| +|34 |FDCE | 2| +|35 |FDPE | 73| +|36 |FDRE | 3995| +|37 |FDSE | 123| +|38 |IOBUFDS_INTERMDISABLE | 2| +|39 |IOBUF_INTERMDISABLE | 16| +|40 |OBUF | 24| +|41 |OBUFDS | 1| +|42 |OBUFT | 2| ++------+----------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:01:25 ; elapsed = 00:01:25 . Memory (MB): peak = 3300.871 ; gain = 1060.109 ; free physical = 491435 ; free virtual = 628072 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:01:21 ; elapsed = 00:01:23 . Memory (MB): peak = 3300.871 ; gain = 950.266 ; free physical = 491411 ; free virtual = 628048 +Synthesis Optimization Complete : Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 3300.879 ; gain = 1060.109 ; free physical = 491410 ; free virtual = 628047 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3300.879 ; gain = 0.000 ; free physical = 491722 ; free virtual = 628364 +INFO: [Netlist 29-17] Analyzing 325 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3_ooc.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] +INFO: [Opt 31-138] Pushed 2 inverter(s) to 16 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3356.898 ; gain = 0.000 ; free physical = 491719 ; free virtual = 628364 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 133 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 112 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 2 instances + +Synth Design complete | Checksum: cc6d6f52 +INFO: [Common 17-83] Releasing license: Synthesis +249 Infos, 303 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:01:30 ; elapsed = 00:01:28 . Memory (MB): peak = 3356.898 ; gain = 1120.105 ; free physical = 491719 ; free virtual = 628364 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3059.030; main = 2758.349; forked = 445.011 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4342.461; main = 3356.902; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 88 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-2] Deriving generated clocks +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Wrote PlaceDB: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491865 ; free virtual = 628527 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +Write Physdb Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491869 ; free virtual = 628532 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' has been generated. +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data0/tools/Xilinx/Vivado/2024.1/data/ip'. +WARNING: [Vivado 12-13650] The IP file '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +Command: synth_design -top toy_axi_cdc -part xc7a100tcsg324-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3404.914 ; gain = 0.000 ; free physical = 491808 ; free virtual = 628479 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'toy_axi_cdc' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +INFO: [Synth 8-6157] synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single__parameterized1' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single__parameterized1' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:152] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:283] +INFO: [Synth 8-6155] done synthesizing module 'axi_clock_converter_v2_1_30_axi_clock_converter' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/hdl/axi_clock_converter_v2_1_vl_rfs.v:650] +INFO: [Synth 8-6155] done synthesizing module 'toy_axi_cdc' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/synth/toy_axi_cdc.v:53] +WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_RD_EN in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_as is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RAM_WR_EN in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[0] in module rd_logic is either unconnected or has no load +WARNING: [Synth 8-7129] Port WR_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port RD_RST in module clk_x_pntrs is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module dmem__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port FAB_REGOUT_EN in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SFT_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SRST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port SLEEP in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTDBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INJECTSBITERR in module memory__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port INT_CLK in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module input_blk__parameterized2 is either unconnected or has no load +WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module input_blk__parameterized2 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 3416.914 ; gain = 12.000 ; free physical = 491891 ; free virtual = 628560 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3416.914 ; gain = 0.000 ; free physical = 491893 ; free virtual = 628563 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/data0/tools/Xilinx/Vivado/2024.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_axi_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_axi_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3462.727 ; gain = 0.000 ; free physical = 491923 ; free virtual = 628592 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3462.727 ; gain = 0.000 ; free physical = 491923 ; free virtual = 628592 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491974 ; free virtual = 628643 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491974 ; free virtual = 628643 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.cdc_wr_rst_busy_ic_3.xpm_cdc_single_inst3 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.cdc_wr_rst_busy_ic_1.xpm_cdc_single_inst1 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.cdc_wr_rst_busy_ic_2.xpm_cdc_single_inst2 . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwach2.axi_wach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grach2.axi_rach /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi /inst_fifo_gen/\gaxi_full_lite.gread_ch.grdch2.axi_rdch /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491979 ; free virtual = 628648 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft' +INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + invalid | 00 | 00 + stage1_valid | 10 | 10 + both_stages_valid | 11 | 11 + stage2_valid | 01 | 01 +--------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491969 ; free virtual = 628639 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 10 ++---XORs : + 2 Input 4 Bit XORs := 10 + 2 Input 1 Bit XORs := 110 ++---Registers : + 145 Bit Registers := 2 + 135 Bit Registers := 2 + 61 Bit Registers := 4 + 6 Bit Registers := 2 + 5 Bit Registers := 10 + 4 Bit Registers := 83 + 2 Bit Registers := 15 + 1 Bit Registers := 88 ++---Muxes : + 4 Input 2 Bit Muxes := 5 + 2 Input 2 Bit Muxes := 50 + 5 Input 2 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 15 + 4 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 491967 ; free virtual = 628638 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492037 ; free virtual = 628707 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492041 ; free virtual = 628712 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 145 | RAM32M x 25 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 6 | RAM32M x 1 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 61 | RAM32M x 11 | +|inst/\gen_clock_conv.gen_async_conv.asyncfifo_axi | inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 135 | RAM32M x 23 | ++---------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492048 ; free virtual = 628719 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |LUT1 | 76| +|2 |LUT2 | 66| +|3 |LUT3 | 35| +|4 |LUT4 | 65| +|5 |LUT5 | 10| +|6 |LUT6 | 25| +|7 |RAM32M | 68| +|8 |RAM32X1D | 3| +|9 |FDCE | 130| +|10 |FDPE | 115| +|11 |FDRE | 1081| ++------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.727 ; gain = 57.812 ; free physical = 492084 ; free virtual = 628755 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 206 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 3462.727 ; gain = 12.000 ; free physical = 492086 ; free virtual = 628757 +Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 3462.734 ; gain = 57.812 ; free physical = 492086 ; free virtual = 628757 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3462.734 ; gain = 0.000 ; free physical = 492379 ; free virtual = 629050 +INFO: [Netlist 29-17] Analyzing 71 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado 12-180] No cells matched '*'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'inst' +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3462.734 ; gain = 0.000 ; free physical = 492413 ; free virtual = 629084 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 71 instances were transformed. + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 68 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 3 instances + +Synth Design complete | Checksum: ed94db3a +INFO: [Common 17-83] Releasing license: Synthesis +33 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 3462.734 ; gain = 57.820 ; free physical = 492415 ; free virtual = 629086 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 3101.122; main = 2799.306; forked = 445.645 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 4504.316; main = 3462.730; forked = 1041.586 +INFO: [Coretcl 2-1174] Renamed 101 cell refs. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 3470.730 ; gain = 0.000 ; free physical = 492418 ; free virtual = 629089 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' has been generated. +INFO: [Vivado 12-3441] generate_netlist_ip - operation complete +synth_ip: Time (s): cpu = 00:02:04 ; elapsed = 00:02:00 . Memory (MB): peak = 3470.730 ; gain = 1247.883 ; free physical = 492416 ; free virtual = 629088 +INFO: [Common 17-2834] synth_ip peak Physical Memory [PSS] (MB): overall = 3101.122; main = 2799.306; forked = 445.645 +INFO: [Common 17-2834] synth_ip peak Virtual Memory [VSS] (MB): overall = 4504.316; main = 3470.734; forked = 1041.586 +# phase SYNTH_BOARD +BOARD_PHASE SYNTH_BOARD +# if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { +# read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +# } +# read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +# foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +# set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +# read_xdc $root/board/arty_a7.xdc +# read_xdc $root/board/flash_boot.xdc +# synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +Command: synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=0 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 3470.852 ; gain = 0.000 ; free physical = 492075 ; free virtual = 628755 +--------------------------------------------------------------------------------- +WARNING: [Synth 8-6901] identifier 'reset' is used before its declaration [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:30] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_top' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:1] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'IBUF' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:73643] +INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] + Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double + Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double + Parameter CLKOUT0_DIVIDE_F bound to: 40.000000 - type: double + Parameter CLKOUT1_DIVIDE bound to: 6 - type: integer + Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer + Parameter DIVCLK_DIVIDE bound to: 1 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:82508] +WARNING: [Synth 8-7071] port 'CLKFBOUTB' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT0B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT1B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT2B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT3B' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7071] port 'CLKOUT6' of module 'MMCME2_BASE' is unconnected for instance 'clock_mmcm' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +WARNING: [Synth 8-7023] instance 'clock_mmcm' of module 'MMCME2_BASE' has 18 connections declared, but only 9 given [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_top.sv:13] +INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data0/tools/Xilinx/Vivado/2024.1/scripts/rt/data/unisim_comp.v:1951] +INFO: [Synth 8-6157] synthesizing module 'toy_a7_platform' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:2] + Parameter FLASH_BOOT bound to: 0 - type: integer +INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:3] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:3] +INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:1] + Parameter DIVISOR bound to: 25 - type: integer +INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:1] +INFO: [Synth 8-6157] synthesizing module 'ddr_uart_loader' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-155] case statement is not full and has no default [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:99] +INFO: [Synth 8-6155] done synthesizing module 'ddr_uart_loader' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:5] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxChip' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817] +INFO: [Synth 8-6157] synthesizing module 'ToyLinuxSystem' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569] +INFO: [Synth 8-6157] synthesizing module 'IntSyncAsyncCrossingSink_n1x1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'SynchronizerShiftReg_w1_d3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6157] synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'NonSyncResetSynchronizerPrimitiveShiftReg_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31] +INFO: [Synth 8-6155] done synthesizing module 'SynchronizerShiftReg_w1_d3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncAsyncCrossingSink_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61] +INFO: [Synth 8-6157] synthesizing module 'IntSyncCrossingSource_n1x1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'AsyncResetRegVec_w1_i0' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'AsyncResetRegVec_w1_i0' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74] +INFO: [Synth 8-6155] done synthesizing module 'IntSyncCrossingSource_n1x1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103] +INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3011] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139] +INFO: [Synth 8-6157] synthesizing module 'plusarg_reader' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301] + Parameter FORMAT bound to: tilelink_timeout=%d - type: string + Parameter WIDTH bound to: 32 - type: integer + Parameter DEFAULT bound to: 32'b00000000000000000000000000000000 +INFO: [Synth 8-6155] done synthesizing module 'plusarg_reader' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3033] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4310] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d128s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6157] synthesizing module 'AXI4Buffer' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'ram_2x58' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x58' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'ram_2x73' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x73' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleB' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'ram_2x4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleB' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleAR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleAR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729] +INFO: [Synth 8-6157] synthesizing module 'Queue2_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6157] synthesizing module 'ram_2x69' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x69' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Buffer' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'ram_2x8' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x8' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086] +INFO: [Synth 8-6157] synthesizing module 'Queue1_BundleMap' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_BundleMap' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178] +INFO: [Synth 8-6157] synthesizing module 'AXI4Deinterleaver' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'Queue8_AXI4BundleR' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6157] synthesizing module 'ram_8x77' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'ram_8x77' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540] +INFO: [Synth 8-6155] done synthesizing module 'Queue8_AXI4BundleR' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559] +INFO: [Synth 8-6155] done synthesizing module 'AXI4Deinterleaver' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7423] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_3' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_3' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148] +INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget16_2' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8551] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a31d128s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396] +INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget16_2' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623] +INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400] +INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050] +INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11207] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_5' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_5' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073] +INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o4_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12453] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_6' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'ram_2x114' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x114' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6157] synthesizing module 'ram_2x79' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x79' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a28d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399] +INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13829] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_7' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_7' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534] +INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449] +INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14907] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_8' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_8' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973] +INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799] +INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846] +INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16078] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_9' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_9' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'ram_2x100' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x100' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876] +INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955] +INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s3k1z4u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028] +INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17199] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_10' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_10' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18288] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_11' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_11' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19205] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_12' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19035] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_12' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425] +INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s3k1z3u' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040] +INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263] +INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330] +INFO: [Synth 8-6157] synthesizing module 'MemoryBus' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'ProbePicker' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20649] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_13' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_13' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882] +INFO: [Synth 8-6155] done synthesizing module 'ProbePicker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610] +INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6157] synthesizing module 'AXI4UserYanker_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'Queue2_BundleMap_6' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6157] synthesizing module 'ram_2x10' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'ram_2x10' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688] +INFO: [Synth 8-6155] done synthesizing module 'Queue2_BundleMap_6' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707] +INFO: [Synth 8-6155] done synthesizing module 'AXI4UserYanker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764] +INFO: [Synth 8-6157] synthesizing module 'AXI4IdIndexer_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6155] done synthesizing module 'AXI4IdIndexer_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713] +INFO: [Synth 8-6157] synthesizing module 'TLToAXI4_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23450] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_14' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_14' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleW_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587] +INFO: [Synth 8-6157] synthesizing module 'Queue1_AXI4BundleARW_1' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'Queue1_AXI4BundleARW_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621] +INFO: [Synth 8-6155] done synthesizing module 'TLToAXI4_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687] +INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555] +INFO: [Synth 8-6155] done synthesizing module 'MemoryBus' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031] +INFO: [Synth 8-6157] synthesizing module 'CoherenceManagerWrapper' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491] +INFO: [Synth 8-6157] synthesizing module 'TLBroadcast' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26482] +INFO: [Synth 8-6157] synthesizing module 'TLMonitor_15' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_15' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349] +INFO: [Synth 8-6157] synthesizing module 'BroadcastFilter' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-6155] done synthesizing module 'BroadcastFilter' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732] +INFO: [Synth 8-6155] done synthesizing module 'ram_4x144' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756] +INFO: [Synth 8-6155] done synthesizing module 'Queue4_TLBroadcastData' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcastTracker_1' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964] +INFO: [Synth 8-6155] done synthesizing module 'TLBroadcast' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27453] +INFO: [Synth 8-6155] done synthesizing module 'TLMonitor_16' (0#1) [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686] +INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29794] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29834] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43249] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43271] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44089] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44825] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45961] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47133] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68592] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68606] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68620] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82885] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82084] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86970] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85223] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85231] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90541] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90573] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90605] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90637] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90669] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90701] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90733] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98928] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98950] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99569] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99575] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99581] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100308] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101303] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102505] +WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101968] + Parameter FLASH_BOOT bound to: 0 - type: integer +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52403] +WARNING: [Synth 8-6014] Unused sequential element rmPost_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52405] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52416] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52418] +WARNING: [Synth 8-6014] Unused sequential element rm_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52420] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52422] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52424] +WARNING: [Synth 8-6014] Unused sequential element tag_pipe_pipe_pipe_v_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52426] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61288] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62163] +WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62183] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62375] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62376] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62378] +WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62379] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62390] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62391] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62393] +WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62394] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62497] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62498] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62499] +WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62500] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63220] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63221] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63222] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63223] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63224] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63225] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_6_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63226] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_7_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63227] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_8_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63228] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_9_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63229] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_10_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63230] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_11_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63231] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_12_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63232] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_13_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63233] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_14_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63234] +WARNING: [Synth 8-6014] Unused sequential element aliasInUse_15_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:63235] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76912] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76914] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76916] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76919] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76922] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76926] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76930] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76935] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76940] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76946] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76952] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76959] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_2_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76968] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76970] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76973] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76977] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76982] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_shift_r_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76988] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_84_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77024] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_85_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77026] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_87_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77029] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_90_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77033] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_94_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77038] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_99_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77044] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_105_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77052] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_106_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77054] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_108_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77057] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_111_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77061] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_115_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77066] +WARNING: [Synth 8-6014] Unused sequential element RegShifted_r_120_0_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77072] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76917] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76920] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76923] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76924] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76927] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_4_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76928] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76931] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76932] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76933] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76936] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76937] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_5_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76938] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76941] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76942] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76943] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76944] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76947] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76948] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76949] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_6_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76950] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76953] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76954] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76955] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76956] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_dataflow_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76957] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76960] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_2_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76961] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_3_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76962] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_4_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76963] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_7_0_propagate_r_5_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76964] +WARNING: [Synth 8-6014] Unused sequential element mesh_io_in_control_3_0_shift_r_1_reg was removed. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76971] +INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_tag_reg' and it is trimmed from '8' to '6' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93740] +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +WARNING: [Synth 8-7129] Port wdata[63] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[62] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[61] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[60] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[59] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[58] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[57] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[56] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[55] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[54] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[53] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[52] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[51] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[50] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[49] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[48] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[47] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[46] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[45] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[44] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[43] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[42] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[41] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[40] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[39] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[38] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[37] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[36] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[35] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[34] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[33] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wdata[32] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[7] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[6] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[5] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port wstrb[4] in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_miso in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port flash_recovery in module axi_scu is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[3] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[2] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[1] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port load_addr[0] in module loader_axi is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_opcode[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_param[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[16] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[15] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[14] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[13] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[12] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[11] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[10] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[9] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[8] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_address[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[7] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_mask[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_a_bits_corrupt in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_ready in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_valid in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_size[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[6] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[5] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[4] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[3] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[2] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[1] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port io_in_d_bits_source[0] in module TLMonitor_29 is either unconnected or has no load +WARNING: [Synth 8-7129] Port clock in module TLMonitor_28 is either unconnected or has no load +WARNING: [Synth 8-7129] Port reset in module TLMonitor_28 is either unconnected or has no load +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 3813.723 ; gain = 342.871 ; free physical = 491660 ; free virtual = 628352 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3828.566 ; gain = 357.715 ; free physical = 491683 ; free virtual = 628374 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 3828.566 ; gain = 357.715 ; free physical = 491683 ; free virtual = 628374 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3828.566 ; gain = 0.000 ; free physical = 491693 ; free virtual = 628384 +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc/toy_axi_cdc_in_context.xdc] for cell 'memory_cdc' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/toy_a7_top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/toy_a7_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +INFO: [Timing 38-2] Deriving generated clocks +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3996.254 ; gain = 0.000 ; free physical = 491625 ; free virtual = 628316 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1 instances were transformed. + MMCME2_BASE => MMCME2_ADV: 1 instance + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 4000.172 ; gain = 0.000 ; free physical = 491615 ; free virtual = 628306 +WARNING: [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'memory_cdc' at clock pin 'm_axi_aclk' is different from the actual clock period '12.000', this can lead to different synthesis results. +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 490374 ; free virtual = 627068 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a100tcsg324-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 490374 ; free virtual = 627068 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 2). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 3). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 4). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 5). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 6). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 7). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 8). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 9). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 10). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 11). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 12). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 13). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 14). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 15). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 16). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 17). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 18). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 19). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 20). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 21). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 22). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 23). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 24). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 25). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 26). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_addr[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 28). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_addr[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 29). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 30). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 31). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 32). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 33). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ba[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 34). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ba[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 35). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cas_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 36). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cas_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 37). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 38). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 39). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 40). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 41). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cke[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 42). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cke[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 43). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_cs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 44). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_cs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 45). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dm[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 46). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dm[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 47). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dm[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 48). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dm[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 49). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 50). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 51). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 52). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[10]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 53). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 54). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[11]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 55). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 56). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[12]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 57). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 58). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[13]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 59). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[14]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 60). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[14]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 61). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[15]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 62). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[15]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 63). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 64). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 65). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 66). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[2]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 67). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 68). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[3]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 69). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 70). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[4]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 71). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 72). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[5]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 73). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 74). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[6]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 75). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 76). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[7]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 77). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 78). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[8]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 79). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dq[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 80). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dq[9]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 81). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 82). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_n[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 83). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_n[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 84). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_n[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 85). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 86). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_p[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 87). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_dqs_p[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 88). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_dqs_p[1]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 89). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_odt[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 90). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_odt[0]. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 91). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ras_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 92). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_ras_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 93). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_reset_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 94). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_reset_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 95). +Applied set_property IO_BUFFER_TYPE = NONE for ddr3_we_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 96). +Applied set_property CLOCK_BUFFER_TYPE = NONE for ddr3_we_n. (constraint file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/arty_ddr3_in_context.xdc, line 97). +Applied set_property KEEP_HIERARCHY = SOFT for ddr_controller. (constraint file auto generated constraint). +Applied set_property KEEP_HIERARCHY = SOFT for memory_cdc. (constraint file auto generated constraint). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 490291 ; free virtual = 626985 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'uart_rx' +WARNING: [Synth 8-3936] Found unconnected internal register 'cam_a_0_bits_opcode_reg' and it is trimmed from '3' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13813] +WARNING: [Synth 8-3936] Found unconnected internal register 'ram_reg' and it is trimmed from '100' to '13' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14825] +WARNING: [Synth 8-3936] Found unconnected internal register 'req_addr_reg' and it is trimmed from '40' to '32' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30468] +WARNING: [Synth 8-3936] Found unconnected internal register 'r_raddr_reg' and it is trimmed from '11' to '4' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36089] +WARNING: [Synth 8-3936] Found unconnected internal register 'in_fmt_reg' and it is trimmed from '2' to '1' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50199] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_inst_reg' and it is trimmed from '32' to '12' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54509] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_inst_reg' and it is trimmed from '32' to '28' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54256] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mcounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55509] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_scounteren_reg' and it is trimmed from '32' to '3' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55511] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_mideleg_reg' and it is trimmed from '64' to '14' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55493] +WARNING: [Synth 8-3936] Found unconnected internal register 'reg_medeleg_reg' and it is trimmed from '64' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55497] +WARNING: [Synth 8-3936] Found unconnected internal register 'wb_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'mem_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62407] +WARNING: [Synth 8-3936] Found unconnected internal register 'ex_reg_raw_inst_reg' and it is trimmed from '32' to '16' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62438] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_reg_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84823] +WARNING: [Synth 8-3936] Found unconnected internal register 'iter_cmd_reg' and it is trimmed from '34' to '29' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84821] +WARNING: [Synth 8-3936] Found unconnected internal register 'reqReg_vaddr_reg' and it is trimmed from '64' to '39' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86206] +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'MemConfiger' +INFO: [Synth 8-802] inferred FSM for state register 'ws_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'rs_reg' in module 'axi_fullwidth' +INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'loader_axi' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000 | 000 + START | 001 | 001 + DATA | 010 | 010 + STOP | 011 | 011 + WAIT_HIGH | 100 | 100 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'uart_rx' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + iSTATE3 | 00000001 | 000 + iSTATE2 | 00000010 | 001 + iSTATE6 | 00000100 | 010 + iSTATE4 | 00010000 | 011 + iSTATE1 | 00100000 | 100 + iSTATE5 | 00001000 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'MemConfiger' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + P_D965DF20 | 00 | 00 + P_D965DC20 | 01 | 01 + P_D965E030 | 10 | 10 + P_D9611170 | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'ws_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + R_IDLE | 00 | 00 + R_SEND | 01 | 01 + R_RESP | 10 | 10 + R_RETURN | 11 | 11 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'rs_reg' using encoding 'sequential' in module 'axi_fullwidth' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- + IDLE | 000001 | 000 + SEND_W | 100000 | 001 + WAIT_B | 010000 | 010 + SEND_R | 001000 | 011 + WAIT_R | 000100 | 100 + RELEASE | 000010 | 101 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'loader_axi' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:42 . Memory (MB): peak = 4000.172 ; gain = 529.320 ; free physical = 486720 ; free virtual = 623434 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/system_bus_xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_bus_named_cbus/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/sbus/coupler_to_port_named_mmio_port_axi4/widget/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/out_xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/atomics/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/atomics/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/error/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/wrapped_error_device/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_clint/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_plic/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/cbus/coupler_to_bootrom/fragmenter/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/picker/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/picker/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/mbus/coupler_to_memory_controller_port_named_axi4/tl2axi4/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/broadcast_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/coh_wrapper/binder/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/tlMasterXbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/dtlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/mpu_ppn_barrier' (OptimizationBarrier_TLBEntryData) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/tlb/entries_barrier_12' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/xbar/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_1/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/widget_3/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/buffer_2/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader' (plusarg_reader) to 'platform/chip/system/tile_prci_domain/buffer/monitor_1/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'platform/chip/system/tile_prci_domain/intsource_2' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/clint_domain/clint/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/plic_domain/plic/monitor/plusarg_reader_1' +INFO: [Synth 8-223] decloning instance 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader' (plusarg_reader) to 'platform/chip/system/bootrom_domain/bootrom/monitor/plusarg_reader_1' +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 109 Bit Adders := 1 + 2 Input 107 Bit Adders := 1 + 2 Input 73 Bit Adders := 1 + 3 Input 65 Bit Adders := 1 + 2 Input 64 Bit Adders := 21 + 3 Input 64 Bit Adders := 2 + 3 Input 58 Bit Adders := 1 + 2 Input 58 Bit Adders := 2 + 2 Input 55 Bit Adders := 4 + 2 Input 48 Bit Adders := 1 + 2 Input 40 Bit Adders := 3 + 3 Input 39 Bit Adders := 5 + 2 Input 39 Bit Adders := 3 + 2 Input 37 Bit Adders := 1 + 2 Input 34 Bit Adders := 1 + 2 Input 33 Bit Adders := 3 + 2 Input 32 Bit Adders := 18 + 3 Input 32 Bit Adders := 1 + 2 Input 30 Bit Adders := 8 + 3 Input 29 Bit Adders := 1 + 2 Input 28 Bit Adders := 1 + 2 Input 26 Bit Adders := 4 + 2 Input 20 Bit Adders := 64 + 2 Input 19 Bit Adders := 2 + 2 Input 17 Bit Adders := 2 + 3 Input 16 Bit Adders := 1 + 2 Input 16 Bit Adders := 12 + 2 Input 15 Bit Adders := 4 + 2 Input 14 Bit Adders := 7 + 4 Input 14 Bit Adders := 1 + 2 Input 13 Bit Adders := 6 + 3 Input 13 Bit Adders := 2 + 2 Input 12 Bit Adders := 12 + 3 Input 12 Bit Adders := 1 + 2 Input 11 Bit Adders := 4 + 2 Input 10 Bit Adders := 7 + 4 Input 10 Bit Adders := 1 + 3 Input 10 Bit Adders := 1 + 2 Input 9 Bit Adders := 14 + 3 Input 9 Bit Adders := 4 + 2 Input 8 Bit Adders := 16 + 3 Input 8 Bit Adders := 8 + 2 Input 7 Bit Adders := 6 + 3 Input 7 Bit Adders := 1 + 2 Input 6 Bit Adders := 13 + 3 Input 6 Bit Adders := 2 + 2 Input 5 Bit Adders := 9 + 2 Input 4 Bit Adders := 60 + 5 Input 4 Bit Adders := 1 + 4 Input 4 Bit Adders := 4 + 2 Input 3 Bit Adders := 65 + 3 Input 3 Bit Adders := 7 + 2 Input 2 Bit Adders := 70 + 3 Input 2 Bit Adders := 5 + 4 Input 2 Bit Adders := 1 + 3 Input 1 Bit Adders := 3 + 2 Input 1 Bit Adders := 126 + 4 Input 1 Bit Adders := 39 ++---XORs : + 2 Input 65 Bit XORs := 1 + 2 Input 64 Bit XORs := 5 + 2 Input 32 Bit XORs := 8 + 2 Input 29 Bit XORs := 8 + 2 Input 27 Bit XORs := 6 + 2 Input 25 Bit XORs := 16 + 2 Input 20 Bit XORs := 8 + 2 Input 18 Bit XORs := 8 + 2 Input 16 Bit XORs := 18 + 2 Input 11 Bit XORs := 8 + 2 Input 10 Bit XORs := 3 + 2 Input 4 Bit XORs := 3 + 2 Input 3 Bit XORs := 11 + 2 Input 2 Bit XORs := 8 + 2 Input 1 Bit XORs := 14 + 3 Input 1 Bit XORs := 2 + 4 Input 1 Bit XORs := 2 ++---Registers : + 1269 Bit Registers := 1 + 145 Bit Registers := 1 + 130 Bit Registers := 1 + 128 Bit Registers := 9 + 107 Bit Registers := 1 + 106 Bit Registers := 3 + 105 Bit Registers := 1 + 73 Bit Registers := 1 + 72 Bit Registers := 1 + 67 Bit Registers := 1 + 65 Bit Registers := 14 + 64 Bit Registers := 184 + 62 Bit Registers := 2 + 58 Bit Registers := 2 + 56 Bit Registers := 1 + 55 Bit Registers := 5 + 53 Bit Registers := 3 + 44 Bit Registers := 5 + 42 Bit Registers := 74 + 40 Bit Registers := 21 + 39 Bit Registers := 19 + 34 Bit Registers := 2 + 32 Bit Registers := 115 + 31 Bit Registers := 2 + 30 Bit Registers := 8 + 29 Bit Registers := 2 + 28 Bit Registers := 5 + 27 Bit Registers := 34 + 26 Bit Registers := 4 + 24 Bit Registers := 1 + 23 Bit Registers := 4 + 21 Bit Registers := 8 + 20 Bit Registers := 293 + 19 Bit Registers := 2 + 17 Bit Registers := 2 + 16 Bit Registers := 54 + 14 Bit Registers := 1 + 13 Bit Registers := 8 + 12 Bit Registers := 1 + 11 Bit Registers := 1 + 10 Bit Registers := 140 + 9 Bit Registers := 12 + 8 Bit Registers := 434 + 7 Bit Registers := 27 + 6 Bit Registers := 11 + 5 Bit Registers := 113 + 4 Bit Registers := 193 + 3 Bit Registers := 234 + 2 Bit Registers := 127 + 1 Bit Registers := 1664 ++---Multipliers : + 53x53 Multipliers := 1 + 73x73 Multipliers := 1 + 16x32 Multipliers := 6 + 16x39 Multipliers := 2 + 16x37 Multipliers := 1 ++---RAMs : + 64K Bit (1024 X 64 bit) RAMs := 8 + 8K Bit (256 X 32 bit) RAMs := 8 + 8K Bit (128 X 64 bit) RAMs := 8 + 2K Bit (16 X 128 bit) RAMs := 1 ++---Muxes : + 2 Input 130 Bit Muxes := 4 + 2 Input 128 Bit Muxes := 34 + 4 Input 128 Bit Muxes := 1 + 2 Input 109 Bit Muxes := 1 + 2 Input 108 Bit Muxes := 1 + 2 Input 65 Bit Muxes := 33 + 4 Input 65 Bit Muxes := 4 + 2 Input 64 Bit Muxes := 303 + 3 Input 64 Bit Muxes := 2 + 4 Input 64 Bit Muxes := 26 + 8 Input 64 Bit Muxes := 3 + 2 Input 62 Bit Muxes := 1 + 2 Input 61 Bit Muxes := 2 + 2 Input 58 Bit Muxes := 2 + 2 Input 56 Bit Muxes := 9 + 2 Input 55 Bit Muxes := 11 + 2 Input 54 Bit Muxes := 3 + 2 Input 53 Bit Muxes := 2 + 2 Input 52 Bit Muxes := 10 + 2 Input 51 Bit Muxes := 2 + 2 Input 48 Bit Muxes := 2 + 4 Input 44 Bit Muxes := 1 + 2 Input 44 Bit Muxes := 6 + 4 Input 42 Bit Muxes := 16 + 2 Input 40 Bit Muxes := 25 + 2 Input 39 Bit Muxes := 19 + 5 Input 39 Bit Muxes := 1 + 3 Input 39 Bit Muxes := 1 + 2 Input 38 Bit Muxes := 1 + 2 Input 34 Bit Muxes := 57 + 2 Input 33 Bit Muxes := 1 + 2 Input 32 Bit Muxes := 129 + 3 Input 32 Bit Muxes := 2 + 4 Input 32 Bit Muxes := 4 + 13 Input 32 Bit Muxes := 2 + 10 Input 32 Bit Muxes := 1 + 8 Input 32 Bit Muxes := 1 + 2 Input 31 Bit Muxes := 4 + 2 Input 30 Bit Muxes := 8 + 2 Input 29 Bit Muxes := 5 + 2 Input 28 Bit Muxes := 13 + 2 Input 27 Bit Muxes := 5 + 2 Input 26 Bit Muxes := 15 + 2 Input 25 Bit Muxes := 6 + 2 Input 24 Bit Muxes := 2 + 2 Input 23 Bit Muxes := 11 + 2 Input 22 Bit Muxes := 388 + 2 Input 21 Bit Muxes := 6 + 2 Input 20 Bit Muxes := 621 + 2 Input 19 Bit Muxes := 11 + 4 Input 18 Bit Muxes := 1 + 2 Input 17 Bit Muxes := 1 + 4 Input 16 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 134 + 13 Input 16 Bit Muxes := 3 + 10 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 2 Input 14 Bit Muxes := 12 + 2 Input 13 Bit Muxes := 23 + 2 Input 12 Bit Muxes := 21 + 5 Input 12 Bit Muxes := 1 + 2 Input 11 Bit Muxes := 8 + 2 Input 10 Bit Muxes := 53 + 2 Input 9 Bit Muxes := 41 + 4 Input 9 Bit Muxes := 1 + 13 Input 9 Bit Muxes := 2 + 2 Input 8 Bit Muxes := 370 + 6 Input 8 Bit Muxes := 1 + 3 Input 8 Bit Muxes := 1 + 5 Input 8 Bit Muxes := 1 + 13 Input 8 Bit Muxes := 3 + 4 Input 8 Bit Muxes := 2 + 2 Input 7 Bit Muxes := 28 + 4 Input 7 Bit Muxes := 1 + 7 Input 7 Bit Muxes := 2 + 6 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 32 + 4 Input 6 Bit Muxes := 1 + 5 Input 6 Bit Muxes := 1 + 6 Input 6 Bit Muxes := 1 + 2 Input 5 Bit Muxes := 103 + 4 Input 5 Bit Muxes := 1 + 5 Input 5 Bit Muxes := 1 + 3 Input 5 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 10 + 2 Input 4 Bit Muxes := 198 + 3 Input 4 Bit Muxes := 5 + 5 Input 4 Bit Muxes := 1 + 8 Input 4 Bit Muxes := 4 + 6 Input 4 Bit Muxes := 1 + 13 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 225 + 8 Input 3 Bit Muxes := 6 + 3 Input 3 Bit Muxes := 7 + 4 Input 3 Bit Muxes := 11 + 5 Input 3 Bit Muxes := 5 + 6 Input 3 Bit Muxes := 2 + 2 Input 2 Bit Muxes := 257 + 4 Input 2 Bit Muxes := 16 + 3 Input 2 Bit Muxes := 9 + 5 Input 2 Bit Muxes := 2 + 16 Input 2 Bit Muxes := 5 + 2 Input 1 Bit Muxes := 1279 + 8 Input 1 Bit Muxes := 6 + 6 Input 1 Bit Muxes := 12 + 4 Input 1 Bit Muxes := 33 + 3 Input 1 Bit Muxes := 2 + 5 Input 1 Bit Muxes := 6 + 13 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 240 (col length:80) +BRAMs: 270 (col length: RAMB18 80 RAMB36 40) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3936] Found unconnected internal register 'subRob/sram/sram_ext/lanes[0].R0_data_reg' and it is trimmed from '1269' to '1262' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:103] +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +WARNING: [Synth 8-3917] design toy_a7_top has port flash_wp_n driven by constant 1 +WARNING: [Synth 8-3917] design toy_a7_top has port flash_hold_n driven by constant 1 +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 10 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52365] +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: PCIN+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b0, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: register product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b0. +DSP Report: Generating DSP product_pipe_b_reg, operation Mode is: (PCIN+A2*B2)'. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: register product_pipe_b_reg is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +DSP Report: operator product_pipe_b0 is absorbed into DSP product_pipe_b_reg. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: Generating DSP tile_0_0/mac_unit/mac/result, operation Mode is: C+A*B. +DSP Report: operator tile_0_0/mac_unit/mac/result is absorbed into DSP tile_0_0/mac_unit/mac/result. +DSP Report: operator tile_0_0/mac_unit/mac/result0 is absorbed into DSP tile_0_0/mac_unit/mac/result. +INFO: [Synth 8-4471] merging register 'cfg_max_j_reg[15:0]' into 'cfg_max_j_reg[15:0]' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79428] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79511] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79576] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79605] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79627] +DSP Report: Generating DSP _GEN_363, operation Mode is: A2*B2. +DSP Report: register cfg_max_j_reg is absorbed into DSP _GEN_363. +DSP Report: register cfg_max_i_reg is absorbed into DSP _GEN_363. +DSP Report: operator _GEN_363 is absorbed into DSP _GEN_363. +DSP Report: Generating DSP _GEN_362, operation Mode is: A*B2. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP _GEN_362, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: operator _GEN_362 is absorbed into DSP _GEN_362. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: A2*B2. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_0_bits_dram_addr5, operation Mode is: (PCIN>>17)+A2*B. +DSP Report: register io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: operator io_cmd_bits_slots_0_bits_dram_addr5 is absorbed into DSP io_cmd_bits_slots_0_bits_dram_addr5. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_1_bits_dram_addr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: operator io_cmd_bits_slots_1_bits_dram_addr4 is absorbed into DSP io_cmd_bits_slots_1_bits_dram_addr4. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: A2*B. +DSP Report: register io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: Generating DSP io_cmd_bits_slots_2_bits_dram_addr2, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +DSP Report: operator io_cmd_bits_slots_2_bits_dram_addr2 is absorbed into DSP io_cmd_bits_slots_2_bits_dram_addr2. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79673] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79677] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79681] +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 2 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79681] +DSP Report: Generating DSP _irow_T_7, operation Mode is: C+A*B. +DSP Report: operator _irow_T_7 is absorbed into DSP _irow_T_7. +DSP Report: operator _irow_T_71 is absorbed into DSP _irow_T_7. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr5, operation Mode is: A*B. +DSP Report: operator io_inputAddr5 is absorbed into DSP io_inputAddr5. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP io_inputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: operator io_inputAddr4 is absorbed into DSP io_inputAddr4. +DSP Report: Generating DSP _icol_T_7, operation Mode is: C+A*B. +DSP Report: operator _icol_T_7 is absorbed into DSP _icol_T_7. +DSP Report: operator _icol_T_71 is absorbed into DSP _icol_T_7. +DSP Report: Generating DSP io_inputAddr2, operation Mode is: PCIN+A:B+C. +DSP Report: operator io_inputAddr2 is absorbed into DSP io_inputAddr2. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_inputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: operator io_inputAddr1 is absorbed into DSP io_inputAddr1. +DSP Report: Generating DSP io_weightAddr4, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr4 is absorbed into DSP io_weightAddr4. +DSP Report: operator io_weightAddr5 is absorbed into DSP io_weightAddr4. +DSP Report: Generating DSP io_weightAddr2, operation Mode is: C+A*B. +DSP Report: operator io_weightAddr2 is absorbed into DSP io_weightAddr2. +DSP Report: operator io_weightAddr3 is absorbed into DSP io_weightAddr2. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_weightAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: operator io_weightAddr1 is absorbed into DSP io_weightAddr1. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr5, operation Mode is: A*B. +DSP Report: operator io_outputAddr5 is absorbed into DSP io_outputAddr5. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr4, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: operator io_outputAddr4 is absorbed into DSP io_outputAddr4. +DSP Report: Generating DSP io_outputAddr2, operation Mode is: PCIN+(A:0x0):B+C. +DSP Report: operator io_outputAddr2 is absorbed into DSP io_outputAddr2. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: Generating DSP io_outputAddr1, operation Mode is: (PCIN>>17)+A*B. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +DSP Report: operator io_outputAddr1 is absorbed into DSP io_outputAddr1. +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_input_stride_reg' and it is trimmed from '32' to '22' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79776] +WARNING: [Synth 8-3936] Found unconnected internal register 'cfg_output_stride_reg' and it is trimmed from '32' to '24' bits. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79780] +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_0_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_rd_bank_1_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_1_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_domain_id[2] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_funct[3] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[63] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[62] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[61] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[60] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[59] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_cmd_rs2Data[58] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_rd_bank_0_id[4] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[9] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[8] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[7] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[6] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[5] driven by constant 0 +WARNING: [Synth 8-3917] design GemminiBall__GC0 has port io_subRobReq_bits_slots_2_cmd_bankAccess_wr_bank_id[4] driven by constant 0 +INFO: [Synth 8-4471] merging register 'reqReg_pixel_bytes_reg[9:0]' into 'reqReg_pixel_bytes_reg[9:0]' [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86013] +DSP Report: Generating DSP rowSkip_reg, operation Mode is: (A*B)'. +DSP Report: register rowSkip_reg is absorbed into DSP rowSkip_reg. +DSP Report: operator rowSkip0 is absorbed into DSP rowSkip_reg. +DSP Report: Generating DSP readVaddr1, operation Mode is: A*B2. +DSP Report: register reqReg_pixel_bytes_reg is absorbed into DSP readVaddr1. +DSP Report: operator readVaddr1 is absorbed into DSP readVaddr1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-5845] Not enough pipeline registers after wide multiplier. Recommended levels of pipeline registers is 17 [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58083] +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: register remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +DSP Report: operator remainder1 is absorbed into DSP remainder1. +INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_1_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[7] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port io_requestor_2_resp_bits_tag[6] driven by constant 0 +WARNING: [Synth 8-3917] design BBTile__GCB2 has port auto_buffer_out_1_c_bits_source[1] driven by constant 0 +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +WARNING: [Synth 8-6430] The Block RAM "dcache/mshrs/sdq_ext/Memory_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision +RAM Pipeline Warning: Read Address Register Found For RAM sdq_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance. +--------------------------------------------------------------------------------- +Start Pre Area Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Iterative Area Optimization +--------------------------------------------------------------------------------- +INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] ) +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[1]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3886] merging instance 'wb_toint_exc_reg[2]' (FDE) to 'wb_toint_exc_reg[3]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\wb_toint_exc_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (sharedFma/\io_out_pipe_b_exc_reg[3] ) +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__0) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[47]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[46]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[45]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[44]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[43]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[42]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[41]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[40]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[39]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[38]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[37]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[36]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[35]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[34]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[33]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[32]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[31]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[30]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[29]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[28]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[27]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[26]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[25]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[24]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[23]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[22]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[21]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[20]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[19]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[18]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +WARNING: [Synth 8-3332] Sequential element (product_pipe_b_reg[17]__1) is unused and will be removed from module SharedMulAddRecFNPipe. +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[9]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[6]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[7]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_15_reg[8]' (FDRE) to 'bat/entNewAlias_15_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_15_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[9]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[6]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[7]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_14_reg[8]' (FDRE) to 'bat/entNewAlias_14_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_14_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[9]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[6]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[7]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_13_reg[8]' (FDRE) to 'bat/entNewAlias_13_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_13_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[9]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[6]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[7]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_12_reg[8]' (FDRE) to 'bat/entNewAlias_12_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_12_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[9]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[6]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[7]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_11_reg[8]' (FDRE) to 'bat/entNewAlias_11_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_11_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[9]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[6]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[7]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_10_reg[8]' (FDRE) to 'bat/entNewAlias_10_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_10_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[9]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[6]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[7]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_9_reg[8]' (FDRE) to 'bat/entNewAlias_9_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_9_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[9]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[6]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[7]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_8_reg[8]' (FDRE) to 'bat/entNewAlias_8_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_8_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[9]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[6]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[7]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_7_reg[8]' (FDRE) to 'bat/entNewAlias_7_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_7_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[9]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[6]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[7]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_6_reg[8]' (FDRE) to 'bat/entNewAlias_6_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_6_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[9]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[6]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[7]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_5_reg[8]' (FDRE) to 'bat/entNewAlias_5_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_5_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[9]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[6]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[7]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_4_reg[8]' (FDRE) to 'bat/entNewAlias_4_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_4_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[9]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[6]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[7]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_3_reg[8]' (FDRE) to 'bat/entNewAlias_3_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_3_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[9]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[6]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[7]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_2_reg[8]' (FDRE) to 'bat/entNewAlias_2_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_2_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[9]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[6]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[7]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_1_reg[8]' (FDRE) to 'bat/entNewAlias_1_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_1_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[9]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[6]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[7]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3886] merging instance 'bat/entNewAlias_0_reg[8]' (FDRE) to 'bat/entNewAlias_0_reg[5]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\entNewAlias_0_reg[5] ) +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[9]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[9]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[9]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[9]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[9]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[9]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[9]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[9]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[9]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[9]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[9]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[9]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[9]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[9]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[9]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[9]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[6]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[6]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_13_reg[6]' (FDRE) to 'bat/v2a_13_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_12_reg[6]' (FDRE) to 'bat/v2a_12_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_11_reg[6]' (FDRE) to 'bat/v2a_11_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_10_reg[6]' (FDRE) to 'bat/v2a_10_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_9_reg[6]' (FDRE) to 'bat/v2a_9_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_8_reg[6]' (FDRE) to 'bat/v2a_8_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_7_reg[6]' (FDRE) to 'bat/v2a_7_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_6_reg[6]' (FDRE) to 'bat/v2a_6_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_5_reg[6]' (FDRE) to 'bat/v2a_5_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_4_reg[6]' (FDRE) to 'bat/v2a_4_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_3_reg[6]' (FDRE) to 'bat/v2a_3_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_2_reg[6]' (FDRE) to 'bat/v2a_2_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_1_reg[6]' (FDRE) to 'bat/v2a_1_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_0_reg[6]' (FDRE) to 'bat/v2a_0_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_15_reg[7]' (FDRE) to 'bat/v2a_15_reg[8]' +INFO: [Synth 8-3886] merging instance 'bat/v2a_14_reg[7]' (FDRE) to 'bat/v2a_14_reg[8]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_15_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_14_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_13_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_12_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_11_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_10_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_9_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_8_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_5_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_4_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_3_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_2_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (bat/\v2a_0_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_cmd_domain_id_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_15_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_0_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_1_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_2_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_3_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_4_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_5_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_6_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_7_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_8_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_9_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_10_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_11_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_12_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_13_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\robEntries_14_renamedBankAccess_rd_bank_1_id_reg[9] ) +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[7]) is unused and will be removed from module MemConfiger. +WARNING: [Synth 8-3332] Sequential element (FSM_onehot_state_reg[6]) is unused and will be removed from module MemConfiger. +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/s1_req_tag_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/\ex_reg_cause_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mie_reg[38] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_mcountinhibit_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (\roccMemIF/io_cache_s1_data_r_data_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/reg_singleStepped_reg) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_satp_mode_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[40] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[41] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[42] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[43] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[44] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[45] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[46] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[47] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[48] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[49] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[50] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[51] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[52] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[53] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[54] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[55] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[56] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[57] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[58] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[59] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[60] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[61] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[62] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (cores_0/csr/\reg_misa_reg[63] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (cores_0/csr/\reg_misa_reg[10] ) +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_108_113 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_102_107 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_96_101 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_90_95 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_84_89 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_78_83 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_72_77 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_66_71 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_60_65 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_54_59 from module BBTile__GCB1 due to constant propagation +INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-7067] Removed DRAM instance i_11/buffer/nodeOut_a_q/ram_ext/Memory_reg_0_1_114_115 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance cbus/i_6/wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_72_77 from module PeripheryBus_cbus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance i_10/buffer_1/nodeOut_a_q/ram_ext/Memory_reg_0_1_6_11 from module BBTile__GCB1 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_4/coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg_0_1_48_53 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_13/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_14/i_0/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg_0_7_60_65 from module extram__61 due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_11/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg_0_7_54_59 from module SystemBus due to constant propagation +INFO: [Synth 8-7067] Removed DRAM instance sbus/i_12/coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg_0_7_60_65 from module SystemBus due to constant propagation +--------------------------------------------------------------------------------- +Start Post Area Optimization : Time (s): cpu = 00:12:02 ; elapsed = 00:12:36 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 468157 ; free virtual = 608469 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:12:08 ; elapsed = 00:12:42 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 467930 ; free virtual = 608253 +--------------------------------------------------------------------------------- + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_0 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_10 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_11 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_12 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_13 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_14 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_15 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_16 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_17 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_18 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_19 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_1f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_20 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_21 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_22 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_23 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_24 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_25 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_26 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_27 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_28 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_29 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_2f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_3 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_30 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_4 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_5 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_6 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_7 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_8 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_9 : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_a : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_b : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_c : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_d : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_e : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB1 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is Mesh__GB0 tile_0_0/mac_unit/mac/result_f : 0 0 : 519 519 : Used 1 time 100 + Sort Area is BBTile__GCB0 remainder1_8 : 0 0 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 1 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 2 : 3475 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_8 : 0 3 : 3494 13938 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 0 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 1 : 3475 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 2 : 3494 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_6 : 0 3 : 3137 13243 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 0 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 1 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 2 : 3494 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_4 : 0 3 : 3137 12905 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 0 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 1 : 3274 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_8 : 0 2 : 3341 9889 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 0 : 3274 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 1 : 3137 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_4 : 0 2 : 3322 9733 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 0 : 3137 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 1 : 3156 9478 : Used 1 time 0 + Sort Area is FPU__GB0 product_pipe_b0_0 : 0 2 : 3185 9478 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr1_15 : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 0 : 2588 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr1_1b : 0 1 : 3341 5929 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 0 : 2588 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr1_20 : 0 1 : 3219 5807 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 0 : 3052 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_0_bits_dram_addr5_5 : 0 1 : 2738 5790 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 0 : 3034 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_362_2 : 0 1 : 2738 5772 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_1_bits_dram_addr4_7 : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 0 : 3035 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_cmd_bits_slots_2_bits_dram_addr2_a : 0 1 : 2721 5756 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_f : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 0 : 2588 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1d : 0 1 : 2721 5309 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 0 : 2722 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr4_12 : 0 1 : 265 2987 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr2_19 : 0 0 : 2838 2838 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 0 : 1946 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr4_1e : 0 1 : 222 2168 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _GEN_363_0 : 0 0 : 1978 1978 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_inputAddr5_d : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_outputAddr5_1c : 0 0 : 1946 1946 : Used 1 time 0 + Sort Area is BBTile__GCB0 remainder1_a : 0 0 : 1207 1207 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _icol_T_7_b : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 _irow_T_7_11 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is GemminiBall__GC0 io_weightAddr4_17 : 0 0 : 949 949 : Used 1 time 0 + Sort Area is MemFrontend rowSkip_reg_0 : 0 0 : 768 768 : Used 1 time 0 + Sort Area is MemFrontend readVaddr1_2 : 0 0 : 733 733 : Used 1 time 0 +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Preliminary Mapping Report (see note below) ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + +Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. + +Distributed RAM: Preliminary Mapping Report (see note below) ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. + +DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 20 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A2*B2)' | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 1 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A*B | 8 | 8 | 20 | - | 20 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 16 | 16 | - | - | 32 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B2 | 18 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B2 | 18 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A2*B | 17 | 16 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A2*B | 18 | 17 | - | - | 48 | 1 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 24 | 16 | - | - | 40 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 24 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | 39 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 16 | 8 | 16 | - | 24 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | C+A*B | 24 | 16 | 16 | - | 39 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 23 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 17 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+(A:0x0):B+C | 30 | 16 | 37 | - | -1 | 0 | 0 | 0 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B | 18 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | (PCIN>>17)+A*B | 21 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 | +|StreamReader | (A*B)' | 19 | 6 | - | - | 25 | 0 | 0 | - | - | - | 1 | 0 | +|StreamReader | A*B2 | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 6 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 23 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | ++----------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + +Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:12:14 ; elapsed = 00:12:49 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 466997 ; free virtual = 607433 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:12:27 ; elapsed = 00:13:02 . Memory (MB): peak = 6506.113 ; gain = 3035.262 ; free physical = 466864 ; free virtual = 607304 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Block RAM: Final Mapping Report ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ +|GlobalROB__GB1 | robOperands/robOperands_ext/lanes[0].ram_reg | 16 x 128(READ_FIRST) | W | | 16 x 128(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_0 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_1 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_2 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_3 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_4 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_5 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_6 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|\backend/privateBackend /banks_7 | mem/mem_ext/ram_reg | 1 K x 64(READ_FIRST) | W | | 1 K x 64(WRITE_FIRST) | | R | Port A and B | 0 | 2 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg | 256 x 32(READ_FIRST) | W | | 256 x 32(WRITE_FIRST) | | R | Port A and B | 1 | 0 | +|dcache/mshrs | sdq_ext/Memory_reg | 17 x 64(READ_FIRST) | W | | 17 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_0_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_0/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[0].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | +|dcache/data | array_2_1/array_0_0_ext/lanes[1].ram_reg | 128 x 64(READ_FIRST) | W | | 128 x 64(WRITE_FIRST) | | R | Port A and B | 0 | 1 | ++---------------------------------+----------------------------------------------------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ + + +Distributed RAM: Final Mapping Report ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ +|regfile_ext | bank0_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|regfile_ext | bank1_reg | User Attribute | 32 x 65 | RAM32M x 33 | +|toy_a7_top | total_rows_q/ram_ext/Memory_reg | Implied | 8 x 7 | RAM32M x 2 | +|GemminiExCtrl__GC0 | rdQueue0/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|GemminiExCtrl__GC0 | rdQueue1/ram_data_ext/Memory_reg | Implied | 8 x 64 | RAM32M x 11 | +|toy_a7_top | ballRs/fifo/ram_ext/Memory_reg | Implied | 4 x 281 | RAM32M x 47 | +|memRs | fifo/ram_ext/Memory_reg | Implied | 4 x 158 | RAM32M x 27 | +|toy_a7_top | bankReadReqQ_q/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | bankReadReqQ_q_1/ram_ext/Memory_reg | Implied | 8 x 21 | RAM32M x 4 | +|toy_a7_top | completeQueue/ram_ext/Memory_reg | Implied | 16 x 4 | RAM32M x 1 | +|toy_a7_top | subRob/sram/sram_ext/lanes[0].ram_reg | User Attribute | 8 x 1262 | RAM32M x 211 | +|cores_0 | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 | +|BBTile__GCB0 | buffer_2/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 117 | RAM32M x 20 | +|BBTile__GCB0 | buffer_2/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[0].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | frontend/icache/bbtile_icache_tag_array/bbtile_icache_tag_array_ext/lanes[1].ram_reg | User Attribute | 64 x 21 | RAM64X1S x 21 | +|BBTile__GCB1 | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 116 | RAM32M x 20 | +|BBTile__GCB1 | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 76 | RAM32M x 13 | +|dcache/mshrs | mshrs_0/rpq/ram_ext/Memory_reg | Implied | 16 x 64 | RAM32M x 11 | +|dcache/meta | tag_array/tag_array_ext/lanes[0].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[1].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[2].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|dcache/meta | tag_array/tag_array_ext/lanes[3].ram_reg | User Attribute | 32 x 23 | RAM32X1S x 23 | +|toy_a7_top | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 189 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeOut_a_q_1/ram_ext/Memory_reg | Implied | 2 x 188 | RAM32M x 32 | +|toy_a7_top | buffer/nodeIn_d_q_1/ram_ext/Memory_reg | Implied | 2 x 142 | RAM32M x 24 | +|toy_a7_top | buffer/nodeIn_b_q/ram_ext/Memory_reg | Implied | 2 x 60 | RAM32M x 10 | +|toy_a7_top | buffer/nodeOut_c_q/ram_ext/Memory_reg | Implied | 2 x 172 | RAM32M x 29 | +|toy_a7_top | buffer/nodeOut_e_q/ram_sink_ext/Memory_reg | Implied | 2 x 1 | RAM16X1D x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_aw_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_w_deq_q/ram_ext/Memory_reg | Implied | 2 x 73 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_b_deq_q/ram_ext/Memory_reg | Implied | 2 x 4 | RAM32M x 1 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeOut_ar_deq_q/ram_ext/Memory_reg | Implied | 2 x 58 | RAM32M x 10 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4buf/nodeIn_r_deq_q/ram_ext/Memory_reg | Implied | 2 x 69 | RAM32M x 12 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 8 | RAM32M x 2 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_0/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_1/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_2/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|sbus | coupler_to_port_named_mmio_port_axi4/axi4deint/qs_queue_3/ram_ext/Memory_reg | Implied | 8 x 77 | RAM32M x 13 | +|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 114 | RAM32M x 19 | +|cbus | wrapped_error_device/buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 100 | RAM32M x 17 | +|cbus | wrapped_error_device/buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 79 | RAM32M x 14 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_1/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_2/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_3/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_4/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_5/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_6/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_7/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_8/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_9/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_10/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_11/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_12/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_13/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_14/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_15/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_16/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_17/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_18/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_19/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_20/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_21/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_22/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_23/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_24/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_25/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_26/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_27/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_28/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_29/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_30/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|mbus | coupler_to_memory_controller_port_named_axi4/axi4yank/Queue2_BundleMap_31/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 | +|coh_wrapper | broadcast_1/TLBroadcastTracker/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|coh_wrapper | broadcast_1/TLBroadcastTracker_1/o_data_q/ram_ext/Memory_reg | Implied | 4 x 144 | RAM32M x 24 | +|platformi_21/loader | payload_reg | User Attribute | 256 x 8 | RAM128X1D x 16 | +|platformi_21/peripherals | fifo_reg | User Attribute | 256 x 8 | RAM64M x 12 | ++-------------------------+----------------------------------------------------------------------------------------------+----------------+----------------------+-----------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance memDomaini_14/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_17/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance element_reset_domain_bbtilei_18/platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:12:46 ; elapsed = 00:13:20 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466890 ; free virtual = 607336 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_0/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_1/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_2/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_3/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_4/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_5/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_6/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/banks_7/mem/mem_ext/ram_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_0/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_1/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_2/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/frontend/icache/bbtile_icache_data_arrays_3/bbtile_icache_data_arrays_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/mshrs/sdq_ext/Memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_0_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_0/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[0].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-7052] The timing for the instance platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/dcache/data/array_2_1/array_0_0_ext/lanes[1].ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceComp of module ITraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceIssue of module ITraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/frontend/scheduler/rob/itraceAlloc of module ITraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/pmc/pmcTraces_0 of module PMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/ldPmcTrace of module MemPMCTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/pmc/stPmcTrace of module MemPMCTraceDPI having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_0 of module MTraceDPI__1 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_1 of module MTraceDPI__2 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_2 of module MTraceDPI__3 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_3 of module MTraceDPI__4 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_4 of module MTraceDPI__5 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_5 of module MTraceDPI__6 having unconnected or no output ports +INFO: [Synth 8-4649] Removing BlackBox instance \platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/backend/privateBackend/mtraces_6 of module MTraceDPI having unconnected or no output ports +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:12:55 ; elapsed = 00:13:30 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466689 ; free virtual = 607217 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:12:55 ; elapsed = 00:13:30 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466688 ; free virtual = 607216 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:13:08 ; elapsed = 00:13:43 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466720 ; free virtual = 607249 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:13:08 ; elapsed = 00:13:43 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466720 ; free virtual = 607249 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466713 ; free virtual = 607242 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466706 ; free virtual = 607235 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_matmul_id_RegShifted_0_0_reg[2] | 16 | 3 | NO | NO | YES | 3 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_0_0_reg[19] | 7 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_1_6_0_reg[19] | 6 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_2_6_0_reg[19] | 5 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_6_0_reg[19] | 4 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_6_0_reg[19] | 3 | 20 | NO | NO | YES | 20 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/out_last_RegShifted_0_0_reg | 16 | 1 | NO | NO | YES | 1 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_0_reg[7] | 3 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_0_reg[7] | 4 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_0_reg[7] | 5 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_0_reg[7] | 6 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_0_reg[7] | 7 | 8 | NO | NO | YES | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_1_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_1_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_1_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_1_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_1_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_3_2_0_reg[7] | 3 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_4_2_0_reg[7] | 4 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_5_2_0_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_6_2_0_reg[7] | 6 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/RegShifted_7_2_0_reg[7] | 7 | 8 | NO | NO | NO | 8 | 0 | +|toy_a7_top | platform/chip/system/ibus_intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 | ++------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +DSP Final Report (the ' indicates corresponding REG is set) ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 24 | 16 | - | - | 40 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 24 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B+C | 6 | 18 | - | - | 39 | 0 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A'*B'' | 16 | 8 | 16 | - | 24 | 1 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | C'+A*B'' | 24 | 16 | 16 | - | 39 | 0 | 2 | 2 | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 22 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A'*B'' | 16 | 16 | - | - | 32 | 1 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN+A:B'+C | 0 | 16 | - | - | 37 | 0 | 1 | - | - | - | 0 | 0 | +|LoopConvAddrGen | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopConvAddrGen | PCIN>>17+A*B'' | 20 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|FpgaDspMac | C+A'*B | 30 | 18 | 48 | - | 20 | 1 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|FpgaDspMac | C+A''*B | 30 | 18 | 48 | - | 20 | 2 | 0 | 0 | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B'' | 16 | 16 | - | - | 32 | 2 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A*B'' | 17 | 16 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A''*B | 16 | 15 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B' | 17 | 16 | - | - | 48 | 2 | 1 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A'*B'' | 16 | 15 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | A''*B | 17 | 16 | - | - | 48 | 2 | 0 | - | - | - | 0 | 0 | +|LoopMatmulUnroller | PCIN>>17+A*B'' | 16 | 15 | - | - | 48 | 0 | 2 | - | - | - | 0 | 0 | +|StreamReader | (A*B')' | 19 | 4 | - | - | 25 | 0 | 1 | - | - | - | 0 | 1 | +|StreamReader | A*B' | 10 | 10 | - | - | 20 | 0 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 22 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 22 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN>>17+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B' | 19 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 19 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | +|SharedMulAddRecFNPipe | A'*B'' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | PCIN>>17+A'*B'' | 17 | 17 | - | - | 0 | 1 | 2 | - | - | - | 0 | 0 | +|SharedMulAddRecFNPipe | (PCIN+A'*B'')' | 17 | 17 | - | - | 48 | 1 | 2 | - | - | - | 0 | 1 | ++----------------------+--------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ + + +Report BlackBoxes: ++------+--------------+----------+ +| |BlackBox name |Instances | ++------+--------------+----------+ +|1 |toy_axi_cdc | 1| +|2 |arty_ddr3 | 1| ++------+--------------+----------+ + +Report Cell Usage: ++------+------------+------+ +| |Cell |Count | ++------+------------+------+ +|1 |arty_ddr3 | 1| +|2 |toy_axi_cdc | 1| +|3 |BUFG | 4| +|4 |CARRY4 | 1950| +|5 |DSP48E1 | 117| +|18 |LUT1 | 817| +|19 |LUT2 | 4360| +|20 |LUT3 | 12197| +|21 |LUT4 | 10130| +|22 |LUT5 | 12422| +|23 |LUT6 | 18450| +|24 |MMCME2_BASE | 1| +|25 |MUXF7 | 629| +|26 |MUXF8 | 112| +|27 |RAM128X1D | 16| +|28 |RAM16X1D | 1| +|29 |RAM32M | 665| +|30 |RAM32X1D | 21| +|31 |RAM32X1S | 92| +|32 |RAM64M | 12| +|33 |RAM64X1S | 42| +|34 |RAMB18E1 | 8| +|35 |RAMB36E1 | 27| +|38 |SRL16E | 225| +|39 |FDCE | 8| +|40 |FDPE | 6| +|41 |FDRE | 28184| +|42 |FDSE | 457| +|43 |IBUF | 4| +|44 |OBUF | 9| ++------+------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:13:10 ; elapsed = 00:13:45 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 466706 ; free virtual = 607235 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 571 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:12:56 ; elapsed = 00:13:37 . Memory (MB): peak = 6518.039 ; gain = 2875.582 ; free physical = 474549 ; free virtual = 615080 +Synthesis Optimization Complete : Time (s): cpu = 00:13:13 ; elapsed = 00:13:48 . Memory (MB): peak = 6518.039 ; gain = 3047.188 ; free physical = 474565 ; free virtual = 615078 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' for cell 'memory_cdc' +INFO: [Project 1-454] Reading design checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' for cell 'ddr_controller' +Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474568 ; free virtual = 615080 +INFO: [Netlist 29-17] Analyzing 4089 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2024.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3/user_design/constraints/arty_ddr3.xdc] for cell 'ddr_controller' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/arty_a7.xdc] +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:11] +CRITICAL WARNING: [Designutils 20-1307] Command 'if' is not supported in the xdc constraint file. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc:15] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/flash_boot.xdc] +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/arty_ddr3/arty_ddr3.dcp' +INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc.dcp' +Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +INFO: [Timing 38-2] Deriving generated clocks [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:16] +all_fanout: Time (s): cpu = 00:00:14 ; elapsed = 00:00:06 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474581 ; free virtual = 615093 +WARNING: [Vivado_Tcl 4-2057] Waiver ID 'LUTAR-1' object list specifies likely unusable hierarchical instance 'memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi'. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:30] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:35] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:39] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:42] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:45] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-10' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:49] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:52] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:56] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:60] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:63] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-1' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:66] +WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-2' -to list should not be empty. [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc:70] +Finished Parsing XDC File [/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/ip/toy_axi_cdc/toy_axi_cdc_clocks.xdc] for cell 'memory_cdc/inst' +INFO: [Project 1-1714] 33 XPM XDC files have been applied to the design. +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-1687] 16 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6518.039 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615073 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 1054 instances were transformed. + IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT(x2), INV, OBUFTDS(x2)): 2 instances + IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances + MMCME2_BASE => MMCME2_ADV: 1 instance + OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance + RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 16 instances + RAM16X1D => RAM32X1D (RAMD32(x2)): 1 instance + RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 845 instances + RAM32X1D => RAM32X1D (RAMD32(x2)): 26 instances + RAM32X1S => RAM32X1S (RAMS32): 92 instances + RAM64M => RAM64M (RAMD64E(x4)): 12 instances + RAM64X1S => RAM64X1S (RAMS64E): 42 instances + +Synth Design complete | Checksum: 2dfdb574 +INFO: [Common 17-83] Releasing license: Synthesis +608 Infos, 466 Warnings, 4 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:13:44 ; elapsed = 00:14:10 . Memory (MB): peak = 6518.039 ; gain = 3047.309 ; free physical = 474561 ; free virtual = 615074 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 13700.579; main = 5845.433; forked = 8252.530 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19180.555; main = 6514.125; forked = 12666.434 +# write_checkpoint -force $out/synthesized.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474561 ; free virtual = 615074 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615074 +Write Physdb Complete: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474560 ; free virtual = 615074 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474553 ; free virtual = 615074 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/synthesized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 6538.129 ; gain = 20.090 ; free physical = 474489 ; free virtual = 615068 +# report_utilization -file $out/synth-utilization.rpt +# report_utilization -hierarchical -file $out/synth-hierarchy.rpt +# report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 6538.129 ; gain = 0.000 ; free physical = 474378 ; free virtual = 614957 +# set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +# if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +# phase OPTIMIZE +BOARD_PHASE OPTIMIZE +# opt_design -directive ExploreArea +Command: opt_design -directive ExploreArea +INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: ExploreArea +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.74 . Memory (MB): peak = 6570.145 ; gain = 32.016 ; free physical = 474363 ; free virtual = 614942 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474154 ; free virtual = 614733 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474146 ; free virtual = 614725 +Phase 1 Initialization | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 474146 ; free virtual = 614725 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473991 ; free virtual = 614570 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473983 ; free virtual = 614562 +Phase 2 Timer Update And Timing Data Collection | Checksum: 24b21dee2 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473983 ; free virtual = 614562 + +Phase 3 Retarget +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-1566] Pulled 311 inverters resulting in an inversion of 2868 pins +INFO: [Opt 31-138] Pushed 8 inverter(s) to 9 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 21a22d777 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473922 ; free virtual = 614502 +Retarget | Checksum: 21a22d777 +INFO: [Opt 31-389] Phase Retarget created 97 cells and removed 603 cells +INFO: [Opt 31-1021] In phase Retarget, 52 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 2d2bd90bb + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473896 ; free virtual = 614496 +Constant propagation | Checksum: 2d2bd90bb +INFO: [Opt 31-389] Phase Constant propagation created 12 cells and removed 19 cells +INFO: [Opt 31-1021] In phase Constant propagation, 30 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 5 Sweep +Phase 5 Sweep | Checksum: 2d6232e06 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473899 ; free virtual = 614500 +Sweep | Checksum: 2d6232e06 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 333 cells +INFO: [Opt 31-1021] In phase Sweep, 150 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 264ce99c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473900 ; free virtual = 614501 +BUFG optimization | Checksum: 264ce99c3 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 264ce99c3 + +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 473900 ; free virtual = 614500 +Shift Register Optimization | Checksum: 264ce99c3 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells +INFO: [Opt 31-1555] control_set_opt supports Versal devices only, and device 7a100t is unsupported + +Phase 8 Resynthesis +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Opt 31-74] Optimized 105 modules. +INFO: [Opt 31-75] Optimized module 'AccPipe'. +INFO: [Opt 31-75] Optimized module 'AccPipe_11'. +INFO: [Opt 31-75] Optimized module 'AccPipe_12'. +INFO: [Opt 31-75] Optimized module 'AccPipe_13'. +INFO: [Opt 31-75] Optimized module 'AccPipe_14'. +INFO: [Opt 31-75] Optimized module 'AccPipe_15'. +INFO: [Opt 31-75] Optimized module 'AccPipe_16'. +INFO: [Opt 31-75] Optimized module 'BankScoreboard'. +INFO: [Opt 31-75] Optimized module 'DTLB'. +INFO: [Opt 31-75] Optimized module 'DivSqrtRawFN_small_e8_s24'. +INFO: [Opt 31-75] Optimized module 'FPToInt'. +INFO: [Opt 31-75] Optimized module 'GemminiExCtrl'. +INFO: [Opt 31-75] Optimized module 'IBuf'. +INFO: [Opt 31-75] Optimized module 'ICache'. +INFO: [Opt 31-75] Optimized module 'ITLB'. +INFO: [Opt 31-75] Optimized module 'LoopConvUnroller'. +INFO: [Opt 31-75] Optimized module 'MaxPeriodFibonacciLFSR_3'. +INFO: [Opt 31-75] Optimized module 'MemConfiger'. +INFO: [Opt 31-75] Optimized module 'MemMidend'. +INFO: [Opt 31-75] Optimized module 'MeshWithDelays'. +INFO: [Opt 31-75] Optimized module 'NonBlockingDCache'. +INFO: [Opt 31-75] Optimized module 'PE_64_186'. +INFO: [Opt 31-75] Optimized module 'PE_64_189'. +INFO: [Opt 31-75] Optimized module 'PE_64_192'. +INFO: [Opt 31-75] Optimized module 'PE_64_195'. +INFO: [Opt 31-75] Optimized module 'PE_64_198'. +INFO: [Opt 31-75] Optimized module 'PE_64_201'. +INFO: [Opt 31-75] Optimized module 'PE_64_204'. +INFO: [Opt 31-75] Optimized module 'PE_64_207'. +INFO: [Opt 31-75] Optimized module 'PE_64_210'. +INFO: [Opt 31-75] Optimized module 'PE_64_213'. +INFO: [Opt 31-75] Optimized module 'PE_64_216'. +INFO: [Opt 31-75] Optimized module 'PE_64_219'. +INFO: [Opt 31-75] Optimized module 'PE_64_222'. +INFO: [Opt 31-75] Optimized module 'PE_64_225'. +INFO: [Opt 31-75] Optimized module 'PE_64_228'. +INFO: [Opt 31-75] Optimized module 'PE_64_231'. +INFO: [Opt 31-75] Optimized module 'PE_64_234'. +INFO: [Opt 31-75] Optimized module 'PE_64_237'. +INFO: [Opt 31-75] Optimized module 'PE_64_240'. +INFO: [Opt 31-75] Optimized module 'PE_64_243'. +INFO: [Opt 31-75] Optimized module 'PE_64_246'. +INFO: [Opt 31-75] Optimized module 'PE_64_249'. +INFO: [Opt 31-75] Optimized module 'PE_64_252'. +INFO: [Opt 31-75] Optimized module 'PE_64_255'. +INFO: [Opt 31-75] Optimized module 'PE_64_258'. +INFO: [Opt 31-75] Optimized module 'PE_64_261'. +INFO: [Opt 31-75] Optimized module 'PE_64_264'. +INFO: [Opt 31-75] Optimized module 'PE_64_267'. +INFO: [Opt 31-75] Optimized module 'PE_64_270'. +INFO: [Opt 31-75] Optimized module 'PE_64_273'. +INFO: [Opt 31-75] Optimized module 'PE_64_276'. +INFO: [Opt 31-75] Optimized module 'PE_64_279'. +INFO: [Opt 31-75] Optimized module 'PE_64_282'. +INFO: [Opt 31-75] Optimized module 'PE_64_285'. +INFO: [Opt 31-75] Optimized module 'PE_64_288'. +INFO: [Opt 31-75] Optimized module 'PE_64_291'. +INFO: [Opt 31-75] Optimized module 'PE_64_294'. +INFO: [Opt 31-75] Optimized module 'PE_64_297'. +INFO: [Opt 31-75] Optimized module 'PE_64_300'. +INFO: [Opt 31-75] Optimized module 'PE_64_303'. +INFO: [Opt 31-75] Optimized module 'PE_64_306'. +INFO: [Opt 31-75] Optimized module 'PE_64_309'. +INFO: [Opt 31-75] Optimized module 'PE_64_312'. +INFO: [Opt 31-75] Optimized module 'PE_64_315'. +INFO: [Opt 31-75] Optimized module 'PE_64_318'. +INFO: [Opt 31-75] Optimized module 'PE_64_321'. +INFO: [Opt 31-75] Optimized module 'PE_64_324'. +INFO: [Opt 31-75] Optimized module 'PE_64_327'. +INFO: [Opt 31-75] Optimized module 'PE_64_330'. +INFO: [Opt 31-75] Optimized module 'PE_64_333'. +INFO: [Opt 31-75] Optimized module 'PE_64_336'. +INFO: [Opt 31-75] Optimized module 'PE_64_339'. +INFO: [Opt 31-75] Optimized module 'PE_64_342'. +INFO: [Opt 31-75] Optimized module 'PE_64_345'. +INFO: [Opt 31-75] Optimized module 'PE_64_348'. +INFO: [Opt 31-75] Optimized module 'PE_64_351'. +INFO: [Opt 31-75] Optimized module 'PE_64_354'. +INFO: [Opt 31-75] Optimized module 'Queue16_ReplayInternal'. +INFO: [Opt 31-75] Optimized module 'Queue1_RegMapperInput_i23_m8'. +INFO: [Opt 31-75] Optimized module 'Queue4_TLBroadcastData'. +INFO: [Opt 31-75] Optimized module 'Queue8_SramReadResp_39'. +INFO: [Opt 31-75] Optimized module 'Repeater_TLBundleA_a17d64s3k1z3u'. +INFO: [Opt 31-75] Optimized module 'ShiftQueue'. +INFO: [Opt 31-75] Optimized module 'SubROB'. +INFO: [Opt 31-75] Optimized module 'TLB'. +INFO: [Opt 31-75] Optimized module 'TLXbar_sbus_i2_o3_a32d128s3k1z4c'. +INFO: [Opt 31-75] Optimized module 'TagQueue'. +INFO: [Opt 31-75] Optimized module 'WritebackUnit'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_axi_mc_wr_cmd_fsm'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_bank_state__parameterized2'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_if_post_fifo'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_rdlvl'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_ddr_phy_wrcal'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_rank_common'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_round_robin_arb'. +INFO: [Opt 31-75] Optimized module 'arty_ddr3mig_7series_v4_2_tempmon'. +INFO: [Opt 31-75] Optimized module 'axi_fullwidth'. +INFO: [Opt 31-75] Optimized module 'ram_2x58'. +INFO: [Opt 31-75] Optimized module 'ram_2x58_376'. +INFO: [Common 17-14] Message 'Opt 31-75' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Opt 31-1566] Pulled 2280 inverters resulting in an inversion of 7908 pins +INFO: [Opt 31-138] Pushed 4 inverter(s) to 19 load pin(s). +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 8 Resynthesis | Checksum: 23ff3679c + +Time (s): cpu = 00:02:41 ; elapsed = 00:00:53 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472072 ; free virtual = 612675 +Resynthesis | Checksum: 23ff3679c +INFO: [Opt 31-389] Phase Resynthesis created 19062 cells and removed 19811 cells +INFO: [Opt 31-1021] In phase Resynthesis, 151 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 9 Post Processing Netlist +Phase 9 Post Processing Netlist | Checksum: 23ff3679c + +Time (s): cpu = 00:02:41 ; elapsed = 00:00:53 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472074 ; free virtual = 612678 +Post Processing Netlist | Checksum: 23ff3679c +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +INFO: [Opt 31-1021] In phase Post Processing Netlist, 45 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. + +Phase 10 Finalization + +Phase 10.1 Finalizing Design Cores and Updating Shapes +Phase 10.1 Finalizing Design Cores and Updating Shapes | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 472083 ; free virtual = 612686 + +Phase 10.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471942 ; free virtual = 612545 +Phase 10.2 Verifying Netlist Connectivity | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471934 ; free virtual = 612537 +Phase 10 Finalization | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471926 ; free virtual = 612529 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 97 | 603 | 52 | +| Constant propagation | 12 | 19 | 30 | +| Sweep | 0 | 333 | 150 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Resynthesis | 19062 | 19811 | 151 | +| Post Processing Netlist | 0 | 0 | 45 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 1a072e151 + +Time (s): cpu = 00:02:42 ; elapsed = 00:00:54 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471926 ; free virtual = 612529 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471723 ; free virtual = 612326 +Ending Netlist Obfuscation Task | Checksum: 1a072e151 + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 471715 ; free virtual = 612318 +INFO: [Common 17-83] Releasing license: Implementation +131 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:02:46 ; elapsed = 00:00:56 . Memory (MB): peak = 6570.145 ; gain = 32.016 ; free physical = 471661 ; free virtual = 612265 +# write_checkpoint -force $out/optimized.dcp +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470083 ; free virtual = 610686 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470083 ; free virtual = 610686 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610686 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610686 +Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470082 ; free virtual = 610687 +Write Physdb Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.03 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470081 ; free virtual = 610686 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.11 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470074 ; free virtual = 610689 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/optimized.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470006 ; free virtual = 610681 +# report_utilization -file $out/opt-utilization.rpt +# phase PLACE +BOARD_PHASE PLACE +# place_design -directive Explore +Command: place_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Vivado_Tcl 4-2302] The placer was invoked with the 'Explore' directive. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470014 ; free virtual = 610691 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14f5d1a2b + +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470014 ; free virtual = 610691 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470013 ; free virtual = 610690 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17dfc4ae4 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 6570.145 ; gain = 0.000 ; free physical = 470042 ; free virtual = 610722 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610790 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610790 +Phase 1 Placer Initialization | Checksum: 189c2ca53 + +Time (s): cpu = 00:00:25 ; elapsed = 00:00:12 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470095 ; free virtual = 610791 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 20bb1dab5 + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470120 ; free virtual = 610816 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2286fe973 + +Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470140 ; free virtual = 610839 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 2286fe973 + +Time (s): cpu = 00:00:41 ; elapsed = 00:00:17 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470127 ; free virtual = 610826 + +Phase 2.4 Global Placement Core + +Phase 2.4.1 UpdateTiming Before Physical Synthesis +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1a630b68c + +Time (s): cpu = 00:02:11 ; elapsed = 00:00:50 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 470167 ; free virtual = 610887 + +Phase 2.4.2 Physical Synthesis In Placer +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 5152 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2204 nets or LUTs. Breaked 0 LUT, combined 2204 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. +INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. +INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 470052 ; free virtual = 610865 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------------------------------------- +| LUT Combining | 0 | 2204 | 2204 | 0 | 1 | 00:00:02 | +| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | +| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 2204 | 2204 | 0 | 4 | 00:00:02 | +----------------------------------------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2a3298b58 + +Time (s): cpu = 00:02:21 ; elapsed = 00:00:55 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469384 ; free virtual = 610551 +Phase 2.4 Global Placement Core | Checksum: 28e960a12 + +Time (s): cpu = 00:02:34 ; elapsed = 00:01:00 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469678 ; free virtual = 610874 +Phase 2 Global Placement | Checksum: 28e960a12 + +Time (s): cpu = 00:02:34 ; elapsed = 00:01:01 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469678 ; free virtual = 610874 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 2ba6ea6d8 + +Time (s): cpu = 00:02:41 ; elapsed = 00:01:03 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469681 ; free virtual = 610876 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2733bb972 + +Time (s): cpu = 00:02:53 ; elapsed = 00:01:07 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469671 ; free virtual = 610867 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 27d09f09c + +Time (s): cpu = 00:02:54 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469668 ; free virtual = 610864 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 280076c81 + +Time (s): cpu = 00:02:54 ; elapsed = 00:01:08 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 469675 ; free virtual = 610871 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 274e2b06e + +Time (s): cpu = 00:03:15 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465571 ; free virtual = 607195 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 2462932d4 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465456 ; free virtual = 607080 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 3265b2010 + +Time (s): cpu = 00:03:17 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465404 ; free virtual = 607046 +Phase 3 Detail Placement | Checksum: 3265b2010 + +Time (s): cpu = 00:03:18 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 465246 ; free virtual = 606904 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 260892d3c + +Phase 4.1.1.1 BUFG Insertion + +Starting Physical Synthesis Task + +Phase 1 Physical Synthesis Initialization +INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.277 | TNS=0.000 | +Phase 1 Physical Synthesis Initialization | Checksum: 1113813e2 + +Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 459558 ; free virtual = 602864 +INFO: [Place 46-33] Processed net platform/loader/SR[0], BUFG insertion was skipped due to placement/routing conflicts. +INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. +Ending Physical Synthesis Task | Checksum: 1f7ac6828 + +Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 455937 ; free virtual = 600446 +Phase 4.1.1.1 BUFG Insertion | Checksum: 260892d3c + +Time (s): cpu = 00:03:51 ; elapsed = 00:01:43 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 454364 ; free virtual = 599397 + +Phase 4.1.1.2 Post Placement Timing Optimization +INFO: [Place 30-746] Post Placement Timing Summary WNS=1.277. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 452011 ; free virtual = 597821 + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 452010 ; free virtual = 597821 +Phase 4.1 Post Commit Optimization | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:53 ; elapsed = 00:01:44 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 450421 ; free virtual = 596761 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:54 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 448028 ; free virtual = 595156 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 8x8| +|___________|___________________|___________________| +| South| 2x2| 8x8| +|___________|___________________|___________________| +| East| 2x2| 8x8| +|___________|___________________|___________________| +| West| 1x1| 2x2| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 446097 ; free virtual = 593864 +Phase 4.3 Placer Reporting | Checksum: 29d6b1f6b + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 444507 ; free virtual = 592800 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 444337 ; free virtual = 592687 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 444336 ; free virtual = 592686 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2e4b25a14 + +Time (s): cpu = 00:03:55 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 442564 ; free virtual = 591473 +Ending Placer Task | Checksum: 1eddddbab + +Time (s): cpu = 00:03:56 ; elapsed = 00:01:46 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 441290 ; free virtual = 590627 +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:04:00 ; elapsed = 00:01:48 . Memory (MB): peak = 6577.172 ; gain = 7.027 ; free physical = 440996 ; free virtual = 590428 +# write_checkpoint -force $out/placed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 440814 ; free virtual = 590264 +Wrote PlaceDB: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 451981 ; free virtual = 601581 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 451981 ; free virtual = 601581 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452075 ; free virtual = 601675 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 452552 ; free virtual = 602161 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/placed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 453042 ; free virtual = 603197 +# phase PHYS_OPT +BOARD_PHASE PHYS_OPT +# phys_opt_design -directive Explore +Command: phys_opt_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:19 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 441326 ; free virtual = 602523 +INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 1.277 | TNS= 0.000 | +INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped. +INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +phys_opt_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:06 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 441326 ; free virtual = 602523 +# phase ROUTE +BOARD_PHASE ROUTE +# route_design -directive Explore +Command: route_design -directive Explore +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-270] Using Router directive 'Explore'. +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: ee9480ea ConstDB: 0 ShapeSum: 4d76fb2b RouteDB: b1d25f96 +Post Restoration Checksum: NetGraph: 3122703f | NumContArr: 80923bb4 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 23706a12d + +Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434318 ; free virtual = 603900 + +Phase 2 Router Initialization + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 23706a12d + +Time (s): cpu = 00:00:34 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434125 ; free virtual = 603900 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 23706a12d + +Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 434083 ; free virtual = 603902 + Number of Nodes with overlaps = 0 + +Phase 2.3 Update Timing +Phase 2.3 Update Timing | Checksum: 2919fd49e + +Time (s): cpu = 00:01:07 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 429576 ; free virtual = 603961 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-1.411 | THS=-707.945| + + +Phase 2.4 Update Timing for Bus Skew + +Phase 2.4.1 Update Timing +Phase 2.4.1 Update Timing | Checksum: 24d0d505a + +Time (s): cpu = 00:01:30 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 426124 ; free virtual = 603406 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=-2.372 | THS=-68.356| + +Phase 2.4 Update Timing for Bus Skew | Checksum: 25d8558af + +Time (s): cpu = 00:01:30 ; elapsed = 00:00:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 426009 ; free virtual = 603350 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 93600 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 93600 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 30f73531b + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 425562 ; free virtual = 603128 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 30f73531b + +Time (s): cpu = 00:01:32 ; elapsed = 00:00:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 425546 ; free virtual = 603120 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass +Phase 4.1 Initial Net Routing Pass | Checksum: 373819a83 + +Time (s): cpu = 00:01:47 ; elapsed = 00:00:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424373 ; free virtual = 603481 +Phase 4 Initial Routing | Checksum: 373819a83 + +Time (s): cpu = 00:01:48 ; elapsed = 00:00:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424370 ; free virtual = 603478 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 + Number of Nodes with overlaps = 14547 + Number of Nodes with overlaps = 1474 + Number of Nodes with overlaps = 372 + Number of Nodes with overlaps = 120 + Number of Nodes with overlaps = 28 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.1 Global Iteration 0 | Checksum: 22ddfe875 + +Time (s): cpu = 00:03:05 ; elapsed = 00:01:18 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424370 ; free virtual = 603561 + +Phase 5.2 Global Iteration 1 + Number of Nodes with overlaps = 6 + Number of Nodes with overlaps = 18 + Number of Nodes with overlaps = 35 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 4 + Number of Nodes with overlaps = 3 + Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 5.2 Global Iteration 1 | Checksum: 2caa5e21c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:25 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424320 ; free virtual = 603539 +Phase 5 Rip-up And Reroute | Checksum: 2caa5e21c + +Time (s): cpu = 00:03:21 ; elapsed = 00:01:26 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424320 ; free virtual = 603539 + +Phase 6 Delay and Skew Optimization + +Phase 6.1 Delay CleanUp + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 23ffe80c8 + +Time (s): cpu = 00:03:30 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 6.1 Delay CleanUp | Checksum: 2c7712393 + +Time (s): cpu = 00:03:30 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 + +Phase 6.2 Clock Skew Optimization +Phase 6.2 Clock Skew Optimization | Checksum: 2c7712393 + +Time (s): cpu = 00:03:31 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603499 +Phase 6 Delay and Skew Optimization | Checksum: 2c7712393 + +Time (s): cpu = 00:03:31 ; elapsed = 00:01:28 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424280 ; free virtual = 603500 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.274 | TNS=0.000 | WHS=0.010 | THS=0.000 | + +Phase 7.1 Hold Fix Iter | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:41 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424301 ; free virtual = 603520 +Phase 7 Post Hold Fix | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:41 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424301 ; free virtual = 603520 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 21.9621 % + Global Horizontal Routing Utilization = 26.5401 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 8 Route finalize | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:42 ; elapsed = 00:01:30 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424309 ; free virtual = 603528 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 3069ea4f8 + +Time (s): cpu = 00:03:42 ; elapsed = 00:01:31 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424309 ; free virtual = 603528 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 29fc7be2a + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424316 ; free virtual = 603535 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 29fc7be2a + +Time (s): cpu = 00:03:49 ; elapsed = 00:01:34 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424316 ; free virtual = 603535 + +Phase 12 Post Router Timing +INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.276 | TNS=0.000 | WHS=0.012 | THS=0.000 | + +Phase 12 Post Router Timing | Checksum: 1f006e4a8 + +Time (s): cpu = 00:04:17 ; elapsed = 00:01:40 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424343 ; free virtual = 603562 +INFO: [Route 35-61] The design met the timing requirement. +Total Elapsed time in route_design: 100.15 secs + +Phase 13 Post-Route Event Processing +Phase 13 Post-Route Event Processing | Checksum: fa658e56 + +Time (s): cpu = 00:04:17 ; elapsed = 00:01:41 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424343 ; free virtual = 603562 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: fa658e56 + +Time (s): cpu = 00:04:18 ; elapsed = 00:01:41 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424351 ; free virtual = 603571 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:04:24 ; elapsed = 00:01:45 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424352 ; free virtual = 603571 +# write_checkpoint -force $out/routed.dcp +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.16 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424337 ; free virtual = 603574 +Wrote PlaceDB: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424235 ; free virtual = 603557 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424235 ; free virtual = 603557 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.54 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424229 ; free virtual = 603567 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424222 ; free virtual = 603569 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424214 ; free virtual = 603561 +Write Physdb Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424214 ; free virtual = 603561 +INFO: [Common 17-1381] The checkpoint '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/routed.dcp' has been generated. +write_checkpoint: Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424299 ; free virtual = 603605 +# phase REPORT +BOARD_PHASE REPORT +# report_utilization -file $out/routed-utilization.rpt +# report_utilization -hierarchical -file $out/routed-hierarchy.rpt +# report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. +report_timing_summary: Time (s): cpu = 00:00:25 ; elapsed = 00:00:07 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424242 ; free virtual = 603549 +# report_route_status -file $out/route-status.rpt +# report_drc -file $out/drc.rpt +Command: report_drc -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/drc.rpt. +report_drc completed successfully +INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port. +# set cdc [report_cdc -details -return_string] +# set f [open $out/cdc.rpt w] +# puts $f $cdc +# close $f +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs +# set skew [report_bus_skew -return_string] +# set f [open $out/bus-skew.rpt w] +# puts $f $skew +# close $f +# report_methodology -file $out/methodology.rpt +Command: report_methodology -file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 8 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/methodology.rpt. +report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:30 ; elapsed = 00:00:10 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424266 ; free virtual = 603608 +# report_io -file $out/io.rpt +report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.18 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424268 ; free virtual = 603610 +# report_clocks -file $out/clocks.rpt +INFO: [Timing 38-35] Done setting XDC timing constraints. +# check_timing -verbose -file $out/check-timing.rpt +# if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +# if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +# foreach kind {max min} { +# set paths [get_timing_paths -delay_type $kind -max_paths 1] +# if {[llength $paths]==0} {error "Missing $kind timing paths"} +# if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +# } +# if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +# if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +# set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +# if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +# phase BITSTREAM +BOARD_PHASE BITSTREAM +# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +# write_bitstream -force $out/toy_a7.bit +Command: write_bitstream -force /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/toy_a7.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 8 threads +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. +WARNING: [DRC DPIP-1] Input pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result input platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance. +INFO: [Common 17-14] Message 'DRC DPIP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +WARNING: [DRC DPOP-1] PREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 output platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. +INFO: [Common 17-14] Message 'DRC DPOP-1' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_icol_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/_irow_T_7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_inputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr4__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_outputAddr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/convUnroller/addrGen/io_weightAddr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_0_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_1_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_2_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_3_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_4_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_5_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_6_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_0/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_1/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_2/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_3/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_4/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_5/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_6/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/exCtrl/mesh/mesh/mesh_7_7/tile_0_0/mac_unit/mac/result/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_362__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/_GEN_363/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_0_bits_dram_addr5__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_1_bits_dram_addr4__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/ballDomain/bbus/balls_0/matmulUnroller/io_cmd_bits_slots_2_bits_dram_addr2__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/readVaddr1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/accelerators_0/memDomain/frontend/reader/rowSkip_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__11/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/cores_0/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +WARNING: [DRC DPOP-2] MREG Output pipelining: DSP platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0 multiplier stage platform/chip/system/tile_prci_domain/element_reset_domain_bbtile/fpuOpts_0/sharedFma/fma/product_pipe_b0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. +INFO: [Common 17-14] Message 'DRC DPOP-2' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/pll_clk3_out on the ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of ddr_controller/u_arty_ddr3_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned. +WARNING: [DRC RTSTAT-10] No routable loads: 45 net(s) have no routable loads. The problem bus(es) and/or net(s) are memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grach2.axi_rach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwach2.axi_wach/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0], memory_cdc/inst/gen_clock_conv.gen_async_conv.asyncfifo_axi/inst_fifo_gen/gaxi_full_lite.gread_ch.grdch2.axi_rdch/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2:0]... and (the first 15 of 25 listed). +INFO: [Vivado 12-3199] DRC finished with 0 Errors, 360 Warnings +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 7428160 bits. +Writing bitstream /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-rob-ram-20261012-201352/toy_a7.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +12 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:45 ; elapsed = 00:00:24 . Memory (MB): peak = 6577.172 ; gain = 0.000 ; free physical = 424219 ; free virtual = 603708 +# phase COMPLETE +BOARD_PHASE COMPLETE +# puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" +PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=0; this build does not validate physical boot +INFO: [Common 17-206] Exiting Vivado at Mon Oct 12 20:37:08 2026... diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/README.md b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/README.md new file mode 100644 index 0000000..af10a48 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/README.md @@ -0,0 +1,27 @@ +# Board integration + +Build and programming commands are in [the platform guide](../README.md). +This directory targets Arty A7-100T `xc7a100tcsg324-1` with official Digilent +Rev E.0 DDR parameters. The recorded hardware run passes full payload DDR +readback and Linux checks; physical PCB revision remains unconfirmed. + +- `toy_a7_top.sv`: 100 MHz input, MMCM/BUFG clocks, per-domain reset sequencing, + physical UART/LED/DDR pins, actual MIG and AXI Clock Converter instances. +- `toy_a7_platform.sv`: validated Chisel core, loader/CPU DDR arbitration, + fullwidth memory adapter and SCU console. CPU remains reset until verified RUN. +- `axi_fullwidth.sv`: preserves lanes, strobes, IDs and backpressure while + translating narrow INCR/FIXED beats into aligned 128-bit DDR accesses. +- `ddr_uart_loader.sv` / `loader_axi.sv`: CRC-framed load, readback and release; + acknowledgements wait for DDR responses. INFO bytes preserve LUTRAM inference. +- `axi_scu.sv`: UART/exit MMIO and 256-byte RX FIFO, with accepted-response pops. +- `arty_a7.xdc`: actual pins and targeted asynchronous I/O/reset exceptions; + DDR data/address/control and internal CPU timing remain checked. +- `build_board.tcl`: complete IP generation, synthesis, placement, routing and + bitstream. Setup/hold, CDC Critical, bus skew, routing errors and DRC errors + stop the build. No warning severity downgrade or CDC waiver is applied. +- `program_arty.tcl`: explicit volatile JTAG programming; exactly one target + and one XC7A100T required. The platform's `../program.tcl` entry delegates here. + The exact script used for first bring-up is also archived with the hardware logs. + +`vendor/` contains unmodified pinned Digilent MIG/board inputs and their license. +Vivado generates proprietary vendor IP into ignored build directories locally. diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/SOURCE_MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/SOURCE_MANIFEST.json new file mode 100644 index 0000000..3ced1fd --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/SOURCE_MANIFEST.json @@ -0,0 +1,18 @@ +{ + "core_sha256": "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779", + "copied_files": { + "uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "vendor/board.xml": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df", + "vendor/MANIFEST.json": "3fbfac2499bc99a23356873a5d81e0f87d32f02ec1b7929ead51a15f33d9af85", + "vendor/mig.prj": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329", + "vendor/part0_pins.xml": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31", + "vendor/preset.xml": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + }, + "clock_hz": 25000000, + "uart_baud": 1000000, + "memory_bytes": 268435456, + "clint_actual_hz": 500000, + "vendor_revision": "E.0", + "physical_board_revision": "unknown" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/arty_a7.xdc b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/arty_a7.xdc new file mode 100644 index 0000000..51efe3b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/arty_a7.xdc @@ -0,0 +1,27 @@ +# User pins from Digilent Arty A7-100 Master XDC Rev D/E. DDR pins/timing +# are supplied by the unmodified official MIG output products. +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ] +create_clock -name board_clk -period 10.000 [get_ports CLK100MHZ] +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports btn0] +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports uart_txd_in] +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports uart_rxd_out] +set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[0]}] +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[1]}] +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {led[2]}] +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {led[3]}] +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property DRIVE 8 [get_ports {led[*] uart_rxd_out}] +set_property SLEW SLOW [get_ports {led[*] uart_rxd_out}] +# Asynchronous button and UART input: cut only the first synchronizer stage. +set_false_path -from [get_ports btn0] -to [get_pins -hier -filter {NAME =~ *btn_meta_reg/D || NAME =~ *btn_ref_meta_reg/D}] +set_false_path -from [get_ports uart_txd_in] -to [get_pins -hier -filter {NAME =~ *rx_meta_reg/D}] +# Reset assertion is asynchronous; deassertion is synchronized in each domain. +set_false_path -to [get_pins -hier -filter {NAME =~ *lock_sync_reg*/PRE || NAME =~ *ui_reset_pipe_reg*/PRE}] +# Calibration status crosses ui_clk to core_clk through a two-stage synchronizer. +set_false_path -to [get_pins -hier -regexp {.*calib_sync_reg\[0\]/D}] +# Human-visible indicators and asynchronous serial TX have no external clock. +set_false_path -to [get_ports {led[*] uart_rxd_out}] +# DDR RESET_N is an asynchronous memory reset, sequenced by the unmodified MIG +# initialization FSM. It is not a command/data signal sampled on DDR CK edges. +set_false_path -to [get_ports ddr3_reset_n] diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/axi_fullwidth.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/axi_fullwidth.sv new file mode 100644 index 0000000..a17053c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/axi_fullwidth.sv @@ -0,0 +1,115 @@ +// Serialize each INCR/FIXED AXI beat into an aligned 128-bit MIG transaction. +// Lane positions/strobes and IDs are preserved. Narrow reads may overfetch DDR +// bytes but never MMIO. One read and one write burst can progress independently. +module axi_fullwidth ( + input wire clk, reset, + input wire [3:0] s_awid, s_arid, + input wire [31:0] s_awaddr, s_araddr, + input wire [7:0] s_awlen, s_arlen, + input wire [2:0] s_awsize, s_arsize, + input wire [1:0] s_awburst, s_arburst, + input wire s_awvalid, s_arvalid, s_wvalid, s_wlast, s_bready, s_rready, + output wire s_awready, s_arready, s_wready, + input wire [127:0] s_wdata, input wire [15:0] s_wstrb, + output reg [3:0] s_bid, s_rid, + output reg [1:0] s_bresp, s_rresp, + output reg s_bvalid, s_rvalid, s_rlast, output reg [127:0] s_rdata, + output wire [3:0] m_awid, m_arid, + output wire [27:0] m_awaddr, m_araddr, + output wire [7:0] m_awlen, m_arlen, + output wire [2:0] m_awsize, m_arsize, + output wire [1:0] m_awburst, m_arburst, + output wire m_awvalid, m_arvalid, m_wvalid, m_wlast, m_bready, m_rready, + input wire m_awready, m_arready, m_wready, + output wire [127:0] m_wdata, output wire [15:0] m_wstrb, + input wire [3:0] m_bid, m_rid, + input wire [1:0] m_bresp, m_rresp, + input wire m_bvalid, m_rvalid, m_rlast, input wire [127:0] m_rdata +); + localparam W_IDLE=0, W_DATA=1, W_SEND=2, W_RESP=3; + localparam R_IDLE=0, R_SEND=1, R_RESP=2, R_RETURN=3; + reg [1:0] ws, rs; + reg [31:0] wa, ra; + reg [7:0] wl, rl; + reg [2:0] wz, rz; + reg wi, ri, wbad, rbad, aw_sent, w_sent; + reg [127:0] wd; + reg [15:0] wm; + wire [32:0] wend = {1'b0,s_awaddr} + ({25'd0,s_awlen} << s_awsize); + wire [32:0] rend = {1'b0,s_araddr} + ({25'd0,s_arlen} << s_arsize); + wire wlegal = s_awaddr[31:28]==4'h8 && s_awsize<=4 && s_awburst<=1 && + (s_awaddr & ((32'd1<3 || awburst>1 || + (awaddr & ((31'd1<3 || arburst>1 || (araddr & ((31'd1<=3) rdata[47:40]<={5'd0,framing,overflow,count!=0}; + end else rresp<=2; + end + if(push) begin fifo[wp]<=rx_data;wp<=wp+1'b1;end + if(pop) rp<=rp+1'b1; + case({push,pop}) + 2'b10:count<=count+1'b1; + 2'b01:count<=count-1'b1; + default:count<=count; + endcase + if(rx_valid && !push) overflow<=1; + if(rx_error) framing<=1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/backup_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/backup_flash.tcl new file mode 100644 index 0000000..7c44264 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/backup_flash.tcl @@ -0,0 +1,32 @@ +# Read all existing Flash before any erase. This temporarily replaces FPGA SRAM +# with Vivado's SPI bridge, but never requests a Flash write/erase. +if {$argc!=2} {error "Usage: backup_flash.tcl FLASH_PART output.bin"} +lassign $argv part backup +set backup [file normalize $backup] +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete Flash backup"} +puts "PASS FLASH_BACKUP: $part $backup bytes=16777216" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/build_board.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/build_board.tcl new file mode 100644 index 0000000..93159c2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/build_board.tcl @@ -0,0 +1,86 @@ +set root [file dirname [file dirname [file normalize [info script]]]] +cd $root +if {[llength $argv]<1 || [llength $argv]>2} {error "Usage: build_board.tcl OUTPUT_DIRECTORY ?flash?"} +set flash 0 +if {[llength $argv]==2} { + if {[lindex $argv 1] ne "flash"} {error "Second argument must be flash"} + set flash 1 +} +set out [file normalize [lindex $argv 0]] +file mkdir $out +file mkdir $out/ip +proc phase {name} { + global out + set f [open $out/phase.txt w];puts $f $name;close $f + puts "BOARD_PHASE $name" +} +set_param general.maxThreads 8 +phase CREATE_IP +create_project -in_memory -part xc7a100tcsg324-1 +set_property target_language Verilog [current_project] +create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name arty_ddr3 -dir $out/ip +set_property CONFIG.XML_INPUT_FILE $root/board/vendor/mig.prj [get_ips arty_ddr3] +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name toy_axi_cdc -dir $out/ip +set_property -dict {CONFIG.PROTOCOL AXI4 CONFIG.ADDR_WIDTH 28 CONFIG.DATA_WIDTH 128 CONFIG.ID_WIDTH 4 CONFIG.ACLK_ASYNC 1 CONFIG.SYNCHRONIZATION_STAGES 3} [get_ips toy_axi_cdc] +generate_target all [get_ips] +report_ip_status -file $out/ip-status.rpt +phase SYNTH_IP +synth_ip [get_ips] +phase SYNTH_BOARD +if {$flash} {read_verilog -sv $root/build/flash-boot/ToyLinuxChip.sv} else { + read_verilog -sv $root/build/serial-bound/ToyLinuxChip.sv +} +read_verilog -sv $root/build/serial-bound/FpgaMemories.sv +foreach f [glob $root/board/*.sv] {read_verilog -sv $f} +set_property verilog_define {SYNTHESIS BUCKYBALL_DISABLE_DPI} [current_fileset] +read_xdc $root/board/arty_a7.xdc +read_xdc $root/board/flash_boot.xdc +synth_design -top toy_a7_top -part xc7a100tcsg324-1 -flatten_hierarchy rebuilt -directive AreaOptimized_high -resource_sharing on -generic FLASH_BOOT=$flash +write_checkpoint -force $out/synthesized.dcp +report_utilization -file $out/synth-utilization.rpt +report_utilization -hierarchical -file $out/synth-hierarchy.rpt +report_timing_summary -delay_type min_max -file $out/synth-timing.rpt +set unresolved [get_cells -hier -quiet -filter {IS_BLACKBOX == 1}] +if {[llength $unresolved]} {error "Unresolved black boxes: $unresolved"} +phase OPTIMIZE +opt_design -directive ExploreArea +write_checkpoint -force $out/optimized.dcp +report_utilization -file $out/opt-utilization.rpt +phase PLACE +place_design -directive Explore +write_checkpoint -force $out/placed.dcp +phase PHYS_OPT +phys_opt_design -directive Explore +phase ROUTE +route_design -directive Explore +write_checkpoint -force $out/routed.dcp +phase REPORT +report_utilization -file $out/routed-utilization.rpt +report_utilization -hierarchical -file $out/routed-hierarchy.rpt +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -file $out/routed-timing.rpt +report_route_status -file $out/route-status.rpt +report_drc -file $out/drc.rpt +set cdc [report_cdc -details -return_string] +set f [open $out/cdc.rpt w];puts $f $cdc;close $f +set skew [report_bus_skew -return_string] +set f [open $out/bus-skew.rpt w];puts $f $skew;close $f +report_methodology -file $out/methodology.rpt +report_io -file $out/io.rpt +report_clocks -file $out/clocks.rpt +check_timing -verbose -file $out/check-timing.rpt +if {[regexp {CDC-[0-9]+\s+Critical} $cdc]} {error "Critical CDC findings; see cdc.rpt"} +if {[string match *VIOLATED* $skew]} {error "Bus skew failed; see bus-skew.rpt"} +foreach kind {max min} { + set paths [get_timing_paths -delay_type $kind -max_paths 1] + if {[llength $paths]==0} {error "Missing $kind timing paths"} + if {[get_property SLACK [lindex $paths 0]]<0} {error "$kind timing failed"} +} +if {![report_route_status -boolean_check ROUTED_FULLY]} {error "Routing incomplete"} +if {[report_route_status -boolean_check ERRORS_IN_ROUTES]} {error "Routing errors"} +set errors [get_drc_violations -quiet -filter {SEVERITY == Error || SEVERITY == {Critical Warning}}] +if {[llength $errors]} {error "DRC errors/critical warnings: $errors"} +phase BITSTREAM +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +write_bitstream -force $out/toy_a7.bit +phase COMPLETE +puts "PASS BOARD_PLACE_ROUTE_TIMING_BITSTREAM: engineering Rev E target; flash=$flash; this build does not validate physical boot" diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/ddr_uart_loader.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/ddr_uart_loader.sv new file mode 100644 index 0000000..9aa2dc9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/ddr_uart_loader.sv @@ -0,0 +1,169 @@ +// Stop-and-wait serial boot protocol. Requests: A5 5A op seq addrLE32 lenLE16 +// [WRITE payload] crcLE16. CRC-16/CCITT-FALSE covers op through payload. +// Responses: 5A A5 (op|80) seq status lenLE16 [data] crcLE16. +// CRC is checked before any DDR write; CPU starts after the RUN reply drains. +module ddr_uart_loader #( + parameter integer RAM_BYTES = 268435456, + parameter integer CLOCK_HZ = 25000000, + parameter integer RX_TIMEOUT = CLOCK_HZ/10 +) ( + input wire clk, reset, + input wire rx_valid, input wire [7:0] rx_data, input wire rx_error, + output wire tx_valid, output reg [7:0] tx_data, input wire tx_ready, + output reg cpu_run, output reg error_seen, + output wire load_en, + output wire [$clog2(RAM_BYTES)-1:0] load_addr, + output reg [127:0] load_data, + output reg [15:0] load_mask, + input wire load_valid, load_error, input wire [127:0] load_result +); + localparam [3:0] SYNC0=0,SYNC1=1,HEADER=2,PAYLOAD=3,CRC0=4,CRC1=5, + EXECUTE=6,WRITE=7,READ_REQ=8,READ_WAIT=9,REPLY=10,DRAIN=11; + reg [3:0] state; + reg [7:0] operation, sequence_id, status; + reg [31:0] address; + reg [15:0] length, reply_length, crc, received_crc; + reg [8:0] cursor, reply_index; + reg [3:0] header_index; + (* ram_style="distributed" *) reg [7:0] payload [0:255]; + reg pending_run, image_loaded; + reg [$clog2(RX_TIMEOUT+1)-1:0] timeout_count; + wire receiving = state==SYNC1 || state==HEADER || state==PAYLOAD || state==CRC0 || state==CRC1; + wire [32:0] end_address = {1'b0,address}+length; + wire valid_range = length!=0 && length<=256 && address>=32'h80000000 && + end_address<=33'h080000000+RAM_BYTES; + wire [31:0] byte_address = address + cursor; + assign load_addr = byte_address[$clog2(RAM_BYTES)-1:0]; + assign load_en = !cpu_run && (state==WRITE || state==READ_REQ); + always @* begin + load_data=0;load_mask=0; + if(state==WRITE) begin + load_data[byte_address[3:0]*8 +: 8]=payload[cursor[7:0]]; + load_mask=16'b1<> ((reply_index-11)*8); + 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + default:tx_data=0; + endcase + else tx_data=payload[(reply_index-7) & 255]; + end + else if(reply_index==7+reply_length) tx_data=crc[7:0]; + else tx_data=crc[15:8]; + end + endcase + end + always @(posedge clk) begin + if(reset) begin + state<=SYNC0;cpu_run<=0;error_seen<=0;image_loaded<=0;pending_run<=0; + operation<=0;sequence_id<=0;status<=0;address<=0;length<=0; + reply_length<=0;crc<=16'hffff;received_crc<=0;cursor<=0; + reply_index<=0;header_index<=0;timeout_count<=0; + end else if(!cpu_run) begin + if(!receiving || rx_valid) timeout_count<=0; + else timeout_count<=timeout_count+1'b1; + if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + state<=SYNC0;error_seen<=1;timeout_count<=0; + end else case(state) + SYNC0: if(rx_valid && rx_data==8'ha5) state<=SYNC1; + SYNC1: if(rx_valid) begin + if(rx_data==8'h5a) begin + state<=HEADER;header_index<=0;crc<=16'hffff;length<=0;address<=0; + pending_run<=0;reply_index<=0;reply_length<=0;status<=0; + end else if(rx_data!=8'ha5) state<=SYNC0; + end + HEADER: if(rx_valid) begin + crc<=crc_next(crc,rx_data); + case(header_index) + 0:operation<=rx_data; + 1:sequence_id<=rx_data; + 2:address[7:0]<=rx_data; + 3:address[15:8]<=rx_data; + 4:address[23:16]<=rx_data; + 5:address[31:24]<=rx_data; + 6:length[7:0]<=rx_data; + 7:begin + length[15:8]<=rx_data;cursor<=0; + if({rx_data,length[7:0]}>256) begin state<=SYNC0;error_seen<=1;end + else if(operation==1 && {rx_data,length[7:0]}!=0) state<=PAYLOAD; + else state<=CRC0; + end + endcase + header_index<=header_index+1'b1; + end + PAYLOAD: if(rx_valid) begin + payload[cursor[7:0]]<=rx_data;crc<=crc_next(crc,rx_data); + cursor<=cursor+1'b1; + if(cursor+1==length) state<=CRC0; + end + CRC0: if(rx_valid) begin received_crc[7:0]<=rx_data;state<=CRC1;end + CRC1: if(rx_valid) begin + cursor<=0; + if({rx_data,received_crc[7:0]}!=crc) begin + status<=1;error_seen<=1;crc<=16'hffff;state<=REPLY; + end else state<=EXECUTE; + end + EXECUTE: begin + crc<=16'hffff; + if(operation==1 || operation==2) begin + if(!valid_range) begin status<=2;error_seen<=1;state<=REPLY;end + else if(operation==1) state<=WRITE; + else begin reply_length<=length;state<=READ_REQ;end + end else if(operation==3 && length==0 && address==32'h80000000) begin + if(!image_loaded) begin status<=5;error_seen<=1;end + else pending_run<=1; + state<=REPLY; + end else if(operation==4 && length==0 && address==0) begin + reply_length<=12;state<=REPLY; + end else begin status<=3;error_seen<=1;state<=REPLY;end + end + WRITE: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;state<=REPLY;end + else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + else cursor<=cursor+1'b1; + end + READ_REQ: state<=READ_WAIT; + READ_WAIT: if(load_valid) begin + if(load_error) begin status<=6;error_seen<=1;reply_length<=0;state<=REPLY;end + else begin + payload[cursor[7:0]]<=load_result[byte_address[3:0]*8 +: 8]; + if(cursor+1==length) state<=REPLY; + else begin cursor<=cursor+1'b1;state<=READ_REQ;end + end + end + REPLY: if(tx_ready) begin + if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + if(reply_index==8+reply_length) state<=DRAIN; + else reply_index<=reply_index+1'b1; + end + DRAIN: if(tx_ready) begin + if(pending_run) cpu_run<=1; + state<=SYNC0; + end + default:state<=SYNC0; + endcase + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_boot.xdc b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_boot.xdc new file mode 100644 index 0000000..902d6a7 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_boot.xdc @@ -0,0 +1,19 @@ +# Digilent Arty-A7-100-Master.xdc Rev D/E; CCLK is owned by STARTUPE2. +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports sw0] +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS33} [get_ports flash_cs_n] +set_property -dict {PACKAGE_PIN K17 IOSTANDARD LVCMOS33} [get_ports flash_mosi] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports flash_miso] +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS33} [get_ports flash_wp_n] +set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports flash_hold_n] +set_property DRIVE 8 [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property SLEW SLOW [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set switch_sync [get_pins -quiet -hier -filter {NAME =~ *sw_meta_reg/D}] +if {[llength $switch_sync]} {set_false_path -from [get_ports sw0] -to $switch_sync} +# Serial input sampled after two synchronizer stages. Mode-0 half bit is 160 ns; +# the external data settles before these stages, then is sampled on the next rise. +set flash_sync [get_pins -quiet -hier -filter {NAME =~ *miso_meta_reg/D}] +if {[llength $flash_sync]} {set_false_path -from [get_ports flash_miso] -to $flash_sync} +set_false_path -to [get_ports {flash_cs_n flash_mosi flash_wp_n flash_hold_n}] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_spi_byte.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_spi_byte.sv new file mode 100644 index 0000000..1610a12 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/flash_spi_byte.sv @@ -0,0 +1,33 @@ +// Read-only boot software uses this mode-0 byte engine; no Flash writes in RTL. +// 25 MHz / (2 * 4) = 3.125 MHz. Two MISO synchronizers settle within a half bit. +module flash_spi_byte ( + input wire clk, reset, start, + input wire [7:0] tx_data, + input wire miso, + output reg busy, sck, + output wire mosi, + output reg [7:0] rx_data +); + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg miso_meta, miso_sync; + reg [7:0] shift_tx, shift_rx; + reg [2:0] bit_count; + reg [1:0] divider; + assign mosi=shift_tx[7]; + always @(posedge clk) begin + miso_meta<=miso;miso_sync<=miso_meta; + if(reset) begin + busy<=0;sck<=0;shift_tx<=0;shift_rx<=0;rx_data<=0;bit_count<=0;divider<=0; + end else if(!busy) begin + sck<=0; + if(start) begin busy<=1;shift_tx<=tx_data;shift_rx<=0;bit_count<=0;divider<=0;end + end else if(divider==3) begin + divider<=0;sck<=!sck; + if(!sck) shift_rx<={shift_rx[6:0],miso_sync}; + else begin + shift_tx<={shift_tx[6:0],1'b1}; + if(bit_count==7) begin busy<=0;rx_data<=shift_rx;end + else bit_count<=bit_count+1'b1; + end + end else divider<=divider+1'b1; + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/loader_axi.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/loader_axi.sv new file mode 100644 index 0000000..096ddb0 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/loader_axi.sv @@ -0,0 +1,53 @@ +// Convert a held loader byte request into a completed AXI transaction. +// The loader advances only after B/R. A RELEASE cycle prevents resubmission +// while its synchronous state machine consumes the acknowledgement. +module loader_axi ( + input wire clk, reset, load_en, + input wire [27:0] load_addr, + input wire [127:0] load_data, input wire [15:0] load_mask, + output reg load_valid, load_error, output reg [127:0] load_result, + output wire [27:0] awaddr, araddr, + output wire awvalid, wvalid, arvalid, bready, rready, + input wire awready, wready, arready, bvalid, rvalid, + output wire [127:0] wdata, output wire [15:0] wstrb, + input wire [1:0] bresp, rresp, input wire [127:0] rdata +); + localparam IDLE=0, SEND_W=1, WAIT_B=2, SEND_R=3, WAIT_R=4, RELEASE=5; + reg [2:0] state; + reg [27:0] addr; + reg [127:0] data; + reg [15:0] mask; + reg sent_aw, sent_w; + assign awaddr=addr;assign araddr=addr; + assign wdata=data;assign wstrb=mask; + assign awvalid=!reset && state==SEND_W && !sent_aw; + assign wvalid=!reset && state==SEND_W && !sent_w; + assign arvalid=!reset && state==SEND_R; + assign bready=!reset && state==WAIT_B; + assign rready=!reset && state==WAIT_R; + always @(posedge clk) begin + load_valid<=0; + if(reset) begin + state<=IDLE;addr<=0;data<=0;mask<=0;sent_aw<=0;sent_w<=0; + load_valid<=0;load_error<=0;load_result<=0; + end else case(state) + IDLE:if(load_en) begin + addr<={load_addr[27:4],4'd0};data<=load_data;mask<=load_mask; + sent_aw<=0;sent_w<=0;load_error<=0; + state<=|load_mask ? SEND_W : SEND_R; + end + SEND_W:begin + if(awvalid && awready) sent_aw<=1; + if(wvalid && wready) sent_w<=1; + if((sent_aw || awready) && (sent_w || wready)) state<=WAIT_B; + end + WAIT_B:if(bvalid) begin load_valid<=1;load_error<=bresp!=0;state<=RELEASE;end + SEND_R:if(arready) state<=WAIT_R; + WAIT_R:if(rvalid) begin + load_valid<=1;load_error<=rresp!=0;load_result<=rdata;state<=RELEASE; + end + RELEASE:state<=IDLE; + default:state<=IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/make_flash_image.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/make_flash_image.tcl new file mode 100644 index 0000000..ad0a6d6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/make_flash_image.tcl @@ -0,0 +1,18 @@ +# Combine configuration and packed software without crossing partitions. +if {$argc!=3} {error "Usage: make_flash_image.tcl toy_a7.bit flash_payload.bin output.mcs"} +lassign $argv bitfile payload output +set bitfile [file normalize $bitfile] +set payload [file normalize $payload] +set output [file normalize $output] +if {![file isfile $bitfile] || ![file isfile $payload]} {error "Missing input file"} +if {[file size $bitfile]>=0x400000} {error "Configuration exceeds the 4 MiB partition"} +if {[file size $payload]<=32 || [file size $payload]>0xc00000} {error "Invalid software partition size"} +set f [open $payload rb] +set magic [read $f 8] +close $f +if {$magic ne "TOYFLZ4\x00"} {error "Expected a packed TOYFLZ4 image"} +file mkdir [file dirname $output] +write_cfgmem -force -format mcs -interface SPIx1 -size 16 \ + -loadbit [list up 0x00000000 $bitfile] -loaddata [list up 0x00400000 $payload] -file $output +puts "PASS FLASH_IMAGE_LAYOUT: config=0x0 software=0x400000 capacity=16MiB" +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_arty.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_arty.tcl new file mode 100644 index 0000000..f70f054 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_arty.tcl @@ -0,0 +1,25 @@ +# Volatile JTAG programming only. Usage: +# Confirm physical Rev E DDR compatibility before using this engineering image. +# vivado -mode batch -source board/program_arty.tcl -tclargs /path/to/toy_a7.bit +if {$argc != 1} { error "Supply the Arty A7-100T .bit file" } +set bitfile [file normalize [lindex $argv 0]] +if {![file isfile $bitfile]} { error "Bitstream not found: $bitfile" } +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets] != 1} { + error "Expected one connected JTAG target. Select the Arty manually in Hardware Manager if multiple boards are attached." +} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices] != 1} { error "Expected one XC7A100T; inspect the connected board" } +set device [lindex $devices 0] +current_hw_device $device +set_property PROGRAM.FILE $bitfile $device +program_hw_devices $device +refresh_hw_device $device +puts "ARTY_JTAG_PROGRAMMED: $bitfile" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_flash.tcl b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_flash.tcl new file mode 100644 index 0000000..82a6c4f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/program_flash.tcl @@ -0,0 +1,51 @@ +# Explicit nonvolatile programming: backs up Flash, then erases/programs/verifies. +if {$argc!=3} {error "Usage: program_flash.tcl image.mcs FLASH_PART fresh-backup.bin"} +lassign $argv image part backup +set image [file normalize $image] +set backup [file normalize $backup] +if {![file isfile $image]} {error "Missing Flash image"} +if {[file exists $backup]} {error "Refusing to overwrite an existing backup"} +if {$part ni {s25fl128sxxxxxx0-spi-x1_x2_x4 s25fl128sxxxxxx1-spi-x1_x2_x4 mt25ql128-spi-x1_x2_x4}} { + error "Select the exact supported 128-Mbit Arty Flash model" +} +open_hw_manager +connect_hw_server -allow_non_jtag +set targets [get_hw_targets -quiet] +if {[llength $targets]!=1} {error "Expected one attached JTAG target"} +open_hw_target [lindex $targets 0] +set devices [get_hw_devices -quiet -filter {PART == xc7a100t}] +if {[llength $devices]!=1} {error "Expected one XC7A100T"} +set device [lindex $devices 0] +current_hw_device $device +set choices [get_cfgmem_parts -of_objects $device -filter "NAME == $part"] +if {[llength $choices]!=1} {error "Flash part is not uniquely compatible with this FPGA"} +create_hw_cfgmem -hw_device $device [lindex $choices 0] +set memory [get_property PROGRAM.HW_CFGMEM $device] +create_hw_bitstream -hw_device $device [get_property PROGRAM.HW_CFGMEM_BITFILE $device] +program_hw_devices $device +file mkdir [file dirname $backup] +readback_hw_cfgmem -all -file $backup -format bin $memory +if {[file size $backup]!=16777216} {error "Incomplete backup; programming cancelled"} +puts "PASS FLASH_BACKUP: $backup bytes=16777216" +set_property PROGRAM.ADDRESS_RANGE use_file $memory +set_property PROGRAM.FILES [list $image] $memory +set_property PROGRAM.BLANK_CHECK 0 $memory +set_property PROGRAM.ERASE 1 $memory +set_property PROGRAM.CFG_PROGRAM 1 $memory +set_property PROGRAM.VERIFY 1 $memory +set_property PROGRAM.CHECKSUM 0 $memory +program_hw_cfgmem $memory +puts "PASS FLASH_PROGRAM_VERIFY: $part $image" +# JP1 must be shorted; this reloads the FPGA from Flash without downloading .bit. +boot_hw_device -timeout 60 $device +refresh_hw_device $device +if {[get_property REGISTER.CONFIG_STATUS.BIT14_DONE_PIN $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS $device]!=1 || + [get_property REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR $device]!=0} { + error "FPGA did not successfully reconfigure from Flash" +} +puts "FLASH_BOOT_CONFIG_STATUS [get_property REGISTER.CONFIG_STATUS $device]" +close_hw_target +disconnect_hw_server +close_hw_manager +exit diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_platform.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_platform.sv new file mode 100644 index 0000000..e26d6dc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_platform.sv @@ -0,0 +1,450 @@ +// Generated wiring; source CPU/accelerator RTL is byte-identical. +module toy_a7_platform #(parameter UART_DIVISOR=25, parameter FLASH_BOOT=0) ( + input wire clk, reset, uart_rx_in, + output wire uart_tx_out, cpu_run, exited, loader_error, + output wire [31:0] exit_code, + output wire [3:0] ddr_awid, + output wire [27:0] ddr_awaddr, + output wire [7:0] ddr_awlen, + output wire [2:0] ddr_awsize, + output wire [1:0] ddr_awburst, + output wire ddr_awvalid, + input wire ddr_awready, + output wire [127:0] ddr_wdata, + output wire [15:0] ddr_wstrb, + output wire ddr_wlast, + output wire ddr_wvalid, + input wire ddr_wready, + input wire [3:0] ddr_bid, + input wire [1:0] ddr_bresp, + input wire ddr_bvalid, + output wire ddr_bready, + output wire [3:0] ddr_arid, + output wire [27:0] ddr_araddr, + output wire [7:0] ddr_arlen, + output wire [2:0] ddr_arsize, + output wire [1:0] ddr_arburst, + output wire ddr_arvalid, + input wire ddr_arready, + input wire [3:0] ddr_rid, + input wire [127:0] ddr_rdata, + input wire [1:0] ddr_rresp, + input wire ddr_rlast, + input wire ddr_rvalid, + output wire ddr_rready, + input wire flash_miso, flash_recovery, + output wire flash_mosi, flash_sck, flash_cs_n +); + wire cpu_reset=reset || !cpu_run; + wire loader_cpu_run; + assign cpu_run=loader_cpu_run || (FLASH_BOOT && !flash_recovery); + wire irq; + wire rx_valid, rx_error, tx_ready, loader_tx_valid, mmio_tx_valid; + wire [7:0] rx_data, loader_tx_data, mmio_tx_data; + wire load_en, load_valid, load_error; wire [27:0] load_addr; + wire [127:0] load_data, load_result; wire [15:0] load_mask; + uart_rx #(.DIVISOR(UART_DIVISOR)) receiver (.clk(clk),.reset(reset),.rx(uart_rx_in), + .valid(rx_valid),.data(rx_data),.frame_error(rx_error)); + uart_tx #(.DIVISOR(UART_DIVISOR)) transmitter (.clk(clk),.reset(reset), + .valid(cpu_run ? mmio_tx_valid : loader_tx_valid),.data(cpu_run ? mmio_tx_data : loader_tx_data), + .ready(tx_ready),.tx(uart_tx_out)); + ddr_uart_loader loader (.clk(clk),.reset(reset),.rx_valid(rx_valid && !cpu_run),.rx_data(rx_data), + .rx_error(rx_error),.tx_valid(loader_tx_valid),.tx_data(loader_tx_data),.tx_ready(tx_ready), + .cpu_run(loader_cpu_run),.error_seen(loader_error),.load_en(load_en),.load_addr(load_addr), + .load_data(load_data),.load_mask(load_mask),.load_valid(load_valid),.load_error(load_error),.load_result(load_result)); + wire memory_aw_ready; + wire memory_aw_valid; + wire [3:0] memory_aw_bits_id; + wire [31:0] memory_aw_bits_addr; + wire [7:0] memory_aw_bits_len; + wire [2:0] memory_aw_bits_size; + wire [1:0] memory_aw_bits_burst; + wire memory_aw_bits_lock; + wire [3:0] memory_aw_bits_cache; + wire [2:0] memory_aw_bits_prot; + wire [3:0] memory_aw_bits_qos; + wire memory_w_ready; + wire memory_w_valid; + wire [127:0] memory_w_bits_data; + wire [15:0] memory_w_bits_strb; + wire memory_w_bits_last; + wire memory_b_ready; + wire memory_b_valid; + wire [3:0] memory_b_bits_id; + wire [1:0] memory_b_bits_resp; + wire memory_ar_ready; + wire memory_ar_valid; + wire [3:0] memory_ar_bits_id; + wire [31:0] memory_ar_bits_addr; + wire [7:0] memory_ar_bits_len; + wire [2:0] memory_ar_bits_size; + wire [1:0] memory_ar_bits_burst; + wire memory_ar_bits_lock; + wire [3:0] memory_ar_bits_cache; + wire [2:0] memory_ar_bits_prot; + wire [3:0] memory_ar_bits_qos; + wire memory_r_ready; + wire memory_r_valid; + wire [3:0] memory_r_bits_id; + wire [127:0] memory_r_bits_data; + wire [1:0] memory_r_bits_resp; + wire memory_r_bits_last; + wire peripherals_aw_ready; + wire peripherals_aw_valid; + wire [1:0] peripherals_aw_bits_id; + wire [30:0] peripherals_aw_bits_addr; + wire [7:0] peripherals_aw_bits_len; + wire [2:0] peripherals_aw_bits_size; + wire [1:0] peripherals_aw_bits_burst; + wire peripherals_aw_bits_lock; + wire [3:0] peripherals_aw_bits_cache; + wire [2:0] peripherals_aw_bits_prot; + wire [3:0] peripherals_aw_bits_qos; + wire peripherals_w_ready; + wire peripherals_w_valid; + wire [63:0] peripherals_w_bits_data; + wire [7:0] peripherals_w_bits_strb; + wire peripherals_w_bits_last; + wire peripherals_b_ready; + wire peripherals_b_valid; + wire [1:0] peripherals_b_bits_id; + wire [1:0] peripherals_b_bits_resp; + wire peripherals_ar_ready; + wire peripherals_ar_valid; + wire [1:0] peripherals_ar_bits_id; + wire [30:0] peripherals_ar_bits_addr; + wire [7:0] peripherals_ar_bits_len; + wire [2:0] peripherals_ar_bits_size; + wire [1:0] peripherals_ar_bits_burst; + wire peripherals_ar_bits_lock; + wire [3:0] peripherals_ar_bits_cache; + wire [2:0] peripherals_ar_bits_prot; + wire [3:0] peripherals_ar_bits_qos; + wire peripherals_r_ready; + wire peripherals_r_valid; + wire [1:0] peripherals_r_bits_id; + wire [63:0] peripherals_r_bits_data; + wire [1:0] peripherals_r_bits_resp; + wire peripherals_r_bits_last; + ToyLinuxChip chip ( + .clock(clk), + .reset(cpu_reset), + .interrupt(irq), + .memory_aw_ready(memory_aw_ready), + .memory_aw_valid(memory_aw_valid), + .memory_aw_bits_id(memory_aw_bits_id), + .memory_aw_bits_addr(memory_aw_bits_addr), + .memory_aw_bits_len(memory_aw_bits_len), + .memory_aw_bits_size(memory_aw_bits_size), + .memory_aw_bits_burst(memory_aw_bits_burst), + .memory_aw_bits_lock(memory_aw_bits_lock), + .memory_aw_bits_cache(memory_aw_bits_cache), + .memory_aw_bits_prot(memory_aw_bits_prot), + .memory_aw_bits_qos(memory_aw_bits_qos), + .memory_w_ready(memory_w_ready), + .memory_w_valid(memory_w_valid), + .memory_w_bits_data(memory_w_bits_data), + .memory_w_bits_strb(memory_w_bits_strb), + .memory_w_bits_last(memory_w_bits_last), + .memory_b_ready(memory_b_ready), + .memory_b_valid(memory_b_valid), + .memory_b_bits_id(memory_b_bits_id), + .memory_b_bits_resp(memory_b_bits_resp), + .memory_ar_ready(memory_ar_ready), + .memory_ar_valid(memory_ar_valid), + .memory_ar_bits_id(memory_ar_bits_id), + .memory_ar_bits_addr(memory_ar_bits_addr), + .memory_ar_bits_len(memory_ar_bits_len), + .memory_ar_bits_size(memory_ar_bits_size), + .memory_ar_bits_burst(memory_ar_bits_burst), + .memory_ar_bits_lock(memory_ar_bits_lock), + .memory_ar_bits_cache(memory_ar_bits_cache), + .memory_ar_bits_prot(memory_ar_bits_prot), + .memory_ar_bits_qos(memory_ar_bits_qos), + .memory_r_ready(memory_r_ready), + .memory_r_valid(memory_r_valid), + .memory_r_bits_id(memory_r_bits_id), + .memory_r_bits_data(memory_r_bits_data), + .memory_r_bits_resp(memory_r_bits_resp), + .memory_r_bits_last(memory_r_bits_last), + .peripherals_aw_ready(peripherals_aw_ready), + .peripherals_aw_valid(peripherals_aw_valid), + .peripherals_aw_bits_id(peripherals_aw_bits_id), + .peripherals_aw_bits_addr(peripherals_aw_bits_addr), + .peripherals_aw_bits_len(peripherals_aw_bits_len), + .peripherals_aw_bits_size(peripherals_aw_bits_size), + .peripherals_aw_bits_burst(peripherals_aw_bits_burst), + .peripherals_aw_bits_lock(peripherals_aw_bits_lock), + .peripherals_aw_bits_cache(peripherals_aw_bits_cache), + .peripherals_aw_bits_prot(peripherals_aw_bits_prot), + .peripherals_aw_bits_qos(peripherals_aw_bits_qos), + .peripherals_w_ready(peripherals_w_ready), + .peripherals_w_valid(peripherals_w_valid), + .peripherals_w_bits_data(peripherals_w_bits_data), + .peripherals_w_bits_strb(peripherals_w_bits_strb), + .peripherals_w_bits_last(peripherals_w_bits_last), + .peripherals_b_ready(peripherals_b_ready), + .peripherals_b_valid(peripherals_b_valid), + .peripherals_b_bits_id(peripherals_b_bits_id), + .peripherals_b_bits_resp(peripherals_b_bits_resp), + .peripherals_ar_ready(peripherals_ar_ready), + .peripherals_ar_valid(peripherals_ar_valid), + .peripherals_ar_bits_id(peripherals_ar_bits_id), + .peripherals_ar_bits_addr(peripherals_ar_bits_addr), + .peripherals_ar_bits_len(peripherals_ar_bits_len), + .peripherals_ar_bits_size(peripherals_ar_bits_size), + .peripherals_ar_bits_burst(peripherals_ar_bits_burst), + .peripherals_ar_bits_lock(peripherals_ar_bits_lock), + .peripherals_ar_bits_cache(peripherals_ar_bits_cache), + .peripherals_ar_bits_prot(peripherals_ar_bits_prot), + .peripherals_ar_bits_qos(peripherals_ar_bits_qos), + .peripherals_r_ready(peripherals_r_ready), + .peripherals_r_valid(peripherals_r_valid), + .peripherals_r_bits_id(peripherals_r_bits_id), + .peripherals_r_bits_data(peripherals_r_bits_data), + .peripherals_r_bits_resp(peripherals_r_bits_resp), + .peripherals_r_bits_last(peripherals_r_bits_last) + ); + wire [3:0] c_awid; + wire [27:0] c_awaddr; + wire [7:0] c_awlen; + wire [2:0] c_awsize; + wire [1:0] c_awburst; + wire c_awvalid; + wire c_awready; + wire [127:0] c_wdata; + wire [15:0] c_wstrb; + wire c_wlast; + wire c_wvalid; + wire c_wready; + wire [3:0] c_bid; + wire [1:0] c_bresp; + wire c_bvalid; + wire c_bready; + wire [3:0] c_arid; + wire [27:0] c_araddr; + wire [7:0] c_arlen; + wire [2:0] c_arsize; + wire [1:0] c_arburst; + wire c_arvalid; + wire c_arready; + wire [3:0] c_rid; + wire [127:0] c_rdata; + wire [1:0] c_rresp; + wire c_rlast; + wire c_rvalid; + wire c_rready; + wire [3:0] l_awid; + wire [27:0] l_awaddr; + wire [7:0] l_awlen; + wire [2:0] l_awsize; + wire [1:0] l_awburst; + wire l_awvalid; + wire l_awready; + wire [127:0] l_wdata; + wire [15:0] l_wstrb; + wire l_wlast; + wire l_wvalid; + wire l_wready; + wire [3:0] l_bid; + wire [1:0] l_bresp; + wire l_bvalid; + wire l_bready; + wire [3:0] l_arid; + wire [27:0] l_araddr; + wire [7:0] l_arlen; + wire [2:0] l_arsize; + wire [1:0] l_arburst; + wire l_arvalid; + wire l_arready; + wire [3:0] l_rid; + wire [127:0] l_rdata; + wire [1:0] l_rresp; + wire l_rlast; + wire l_rvalid; + wire l_rready; + axi_fullwidth normalizer ( + .clk(clk), + .reset(reset), + .s_awid(memory_aw_bits_id), + .m_awid(c_awid), + .s_awaddr(memory_aw_bits_addr), + .m_awaddr(c_awaddr), + .s_awlen(memory_aw_bits_len), + .m_awlen(c_awlen), + .s_awsize(memory_aw_bits_size), + .m_awsize(c_awsize), + .s_awburst(memory_aw_bits_burst), + .m_awburst(c_awburst), + .s_awvalid(memory_aw_valid), + .m_awvalid(c_awvalid), + .s_awready(memory_aw_ready), + .m_awready(c_awready), + .s_wdata(memory_w_bits_data), + .m_wdata(c_wdata), + .s_wstrb(memory_w_bits_strb), + .m_wstrb(c_wstrb), + .s_wlast(memory_w_bits_last), + .m_wlast(c_wlast), + .s_wvalid(memory_w_valid), + .m_wvalid(c_wvalid), + .s_wready(memory_w_ready), + .m_wready(c_wready), + .s_bid(memory_b_bits_id), + .m_bid(c_bid), + .s_bresp(memory_b_bits_resp), + .m_bresp(c_bresp), + .s_bvalid(memory_b_valid), + .m_bvalid(c_bvalid), + .s_bready(memory_b_ready), + .m_bready(c_bready), + .s_arid(memory_ar_bits_id), + .m_arid(c_arid), + .s_araddr(memory_ar_bits_addr), + .m_araddr(c_araddr), + .s_arlen(memory_ar_bits_len), + .m_arlen(c_arlen), + .s_arsize(memory_ar_bits_size), + .m_arsize(c_arsize), + .s_arburst(memory_ar_bits_burst), + .m_arburst(c_arburst), + .s_arvalid(memory_ar_valid), + .m_arvalid(c_arvalid), + .s_arready(memory_ar_ready), + .m_arready(c_arready), + .s_rid(memory_r_bits_id), + .m_rid(c_rid), + .s_rdata(memory_r_bits_data), + .m_rdata(c_rdata), + .s_rresp(memory_r_bits_resp), + .m_rresp(c_rresp), + .s_rlast(memory_r_bits_last), + .m_rlast(c_rlast), + .s_rvalid(memory_r_valid), + .m_rvalid(c_rvalid), + .s_rready(memory_r_ready), + .m_rready(c_rready) + ); + loader_axi load_bridge ( + .clk(clk), + .reset(reset), + .load_en(load_en), + .load_addr(load_addr), + .load_data(load_data), + .load_mask(load_mask), + .load_valid(load_valid), + .load_error(load_error), + .load_result(load_result), + .awaddr(l_awaddr), + .araddr(l_araddr), + .awvalid(l_awvalid), + .wvalid(l_wvalid), + .arvalid(l_arvalid), + .bready(l_bready), + .rready(l_rready), + .awready(l_awready), + .wready(l_wready), + .arready(l_arready), + .bvalid(l_bvalid), + .rvalid(l_rvalid), + .wdata(l_wdata), + .wstrb(l_wstrb), + .bresp(l_bresp), + .rresp(l_rresp), + .rdata(l_rdata) + ); + assign l_awid=0; + assign l_arid=0; + assign l_awlen=0; + assign l_arlen=0; + assign l_awsize=4; + assign l_arsize=4; + assign l_awburst=1; + assign l_arburst=1; + assign l_wlast=1; + assign ddr_awid=cpu_run ? c_awid : l_awid; + assign ddr_awaddr=cpu_run ? c_awaddr : l_awaddr; + assign ddr_awlen=cpu_run ? c_awlen : l_awlen; + assign ddr_awsize=cpu_run ? c_awsize : l_awsize; + assign ddr_awburst=cpu_run ? c_awburst : l_awburst; + assign ddr_awvalid=cpu_run ? c_awvalid : l_awvalid; + assign c_awready=ddr_awready && cpu_run; + assign l_awready=ddr_awready && !cpu_run; + assign ddr_wdata=cpu_run ? c_wdata : l_wdata; + assign ddr_wstrb=cpu_run ? c_wstrb : l_wstrb; + assign ddr_wlast=cpu_run ? c_wlast : l_wlast; + assign ddr_wvalid=cpu_run ? c_wvalid : l_wvalid; + assign c_wready=ddr_wready && cpu_run; + assign l_wready=ddr_wready && !cpu_run; + assign c_bid=ddr_bid; + assign l_bid=ddr_bid; + assign c_bresp=ddr_bresp; + assign l_bresp=ddr_bresp; + assign c_bvalid=ddr_bvalid && cpu_run; + assign l_bvalid=ddr_bvalid && !cpu_run; + assign ddr_bready=cpu_run ? c_bready : l_bready; + assign ddr_arid=cpu_run ? c_arid : l_arid; + assign ddr_araddr=cpu_run ? c_araddr : l_araddr; + assign ddr_arlen=cpu_run ? c_arlen : l_arlen; + assign ddr_arsize=cpu_run ? c_arsize : l_arsize; + assign ddr_arburst=cpu_run ? c_arburst : l_arburst; + assign ddr_arvalid=cpu_run ? c_arvalid : l_arvalid; + assign c_arready=ddr_arready && cpu_run; + assign l_arready=ddr_arready && !cpu_run; + assign c_rid=ddr_rid; + assign l_rid=ddr_rid; + assign c_rdata=ddr_rdata; + assign l_rdata=ddr_rdata; + assign c_rresp=ddr_rresp; + assign l_rresp=ddr_rresp; + assign c_rlast=ddr_rlast; + assign l_rlast=ddr_rlast; + assign c_rvalid=ddr_rvalid && cpu_run; + assign l_rvalid=ddr_rvalid && !cpu_run; + assign ddr_rready=cpu_run ? c_rready : l_rready; + wire [1:0] scu_bresp; + assign peripherals_b_bits_resp=|scu_bresp; + axi_scu #(.FLASH_BOOT(FLASH_BOOT)) peripherals ( + .clk(clk), + .reset(cpu_reset), + .awid(peripherals_aw_bits_id), + .awaddr(peripherals_aw_bits_addr), + .awlen(peripherals_aw_bits_len), + .awsize(peripherals_aw_bits_size), + .awburst(peripherals_aw_bits_burst), + .awvalid(peripherals_aw_valid), + .awready(peripherals_aw_ready), + .wdata(peripherals_w_bits_data), + .wstrb(peripherals_w_bits_strb), + .wlast(peripherals_w_bits_last), + .wvalid(peripherals_w_valid), + .wready(peripherals_w_ready), + .bid(peripherals_b_bits_id), + .bresp(scu_bresp), + .bvalid(peripherals_b_valid), + .bready(peripherals_b_ready), + .arid(peripherals_ar_bits_id), + .araddr(peripherals_ar_bits_addr), + .arlen(peripherals_ar_bits_len), + .arsize(peripherals_ar_bits_size), + .arburst(peripherals_ar_bits_burst), + .arvalid(peripherals_ar_valid), + .arready(peripherals_ar_ready), + .rid(peripherals_r_bits_id), + .rdata(peripherals_r_bits_data), + .rresp(peripherals_r_bits_resp), + .rlast(peripherals_r_bits_last), + .rvalid(peripherals_r_valid), + .rready(peripherals_r_ready), + .rx_valid(rx_valid && cpu_run), + .rx_data(rx_data), + .rx_error(rx_error), + .tx_valid(mmio_tx_valid), + .tx_data(mmio_tx_data), + .tx_ready(tx_ready), + .exited(exited), + .exit_code(exit_code), + .interrupt(irq),.flash_miso(flash_miso),.flash_recovery(flash_recovery), + .flash_mosi(flash_mosi),.flash_sck(flash_sck),.flash_cs_n(flash_cs_n) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_top.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_top.sv new file mode 100644 index 0000000..397a262 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/toy_a7_top.sv @@ -0,0 +1,305 @@ +module toy_a7_top #(parameter FLASH_BOOT=0) ( + input wire CLK100MHZ, btn0, uart_txd_in, output wire uart_rxd_out, output wire [3:0] led, + inout wire [15:0] ddr3_dq, inout wire [1:0] ddr3_dqs_n, ddr3_dqs_p, + output wire [13:0] ddr3_addr, output wire [2:0] ddr3_ba, + output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, + output wire [0:0] ddr3_ck_p, ddr3_ck_n, ddr3_cke, ddr3_cs_n, ddr3_odt, output wire [1:0] ddr3_dm, + input wire sw0, flash_miso, + output wire flash_mosi, flash_cs_n, flash_wp_n, flash_hold_n +); + wire clk_in,fb,fb_buf,core_raw,sys_raw,ref_raw,clk,sys_clk,ref_clk,locked; + IBUF input_clock (.I(CLK100MHZ),.O(clk_in)); + MMCME2_BASE #(.CLKIN1_PERIOD(10.0),.DIVCLK_DIVIDE(1),.CLKFBOUT_MULT_F(10.0), + .CLKOUT0_DIVIDE_F(40.0),.CLKOUT1_DIVIDE(6),.CLKOUT2_DIVIDE(5)) clock_mmcm ( + .CLKIN1(clk_in),.CLKFBIN(fb_buf),.CLKFBOUT(fb),.CLKOUT0(core_raw), + .CLKOUT1(sys_raw),.CLKOUT2(ref_raw),.LOCKED(locked),.RST(1'b0),.PWRDWN(1'b0)); + BUFG fb_buffer (.I(fb),.O(fb_buf)); BUFG core_buffer (.I(core_raw),.O(clk)); + BUFG sys_buffer (.I(sys_raw),.O(sys_clk)); BUFG ref_buffer (.I(ref_raw),.O(ref_clk)); + wire ui_clk,ui_rst,mig_locked,calibrated; + wire flash_sck; + assign flash_wp_n=1;assign flash_hold_n=1; + generate if(FLASH_BOOT) begin : flash_clock + STARTUPE2 startup (.CLK(1'b0),.GSR(1'b0),.GTS(1'b0),.KEYCLEARB(1'b1),.PACK(1'b0), + .USRCCLKO(flash_sck),.USRCCLKTS(1'b0),.USRDONEO(1'b1),.USRDONETS(1'b1), + .CFGCLK(),.CFGMCLK(),.EOS(),.PREQ()); + end endgenerate + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg sw_meta=0,sw_sync=0; + reg flash_recovery=0; + always @(posedge clk) begin + sw_meta<=sw0;sw_sync<=sw_meta; + if(reset) flash_recovery<=sw_sync; + end + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] lock_sync=7; + always @(posedge clk or negedge locked) if(!locked) lock_sync<=7;else lock_sync<={lock_sync[1:0],1'b0}; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_meta=0,btn_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg btn_ref_meta=0,btn_ref_sync=0; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] mig_resetn_pipe=0; + always @(posedge ref_clk) begin btn_ref_meta<=btn0;btn_ref_sync<=btn_ref_meta;end + always @(posedge ref_clk or negedge locked) if(!locked) mig_resetn_pipe<=0; + else mig_resetn_pipe<={mig_resetn_pipe[1:0],!btn_ref_sync}; + wire mig_resetn=mig_resetn_pipe[2]; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [1:0] calib_sync=0; + always @(posedge clk) begin btn_meta<=btn0;btn_sync<=btn_meta;calib_sync<={calib_sync[0],calibrated};end + reg [17:0] reset_count=0;wire reset=lock_sync[2] || btn_sync || !calib_sync[1] || !(&reset_count); + always @(posedge clk) if(lock_sync[2] || btn_sync || !calib_sync[1]) reset_count<=0; + else if(!(&reset_count)) reset_count<=reset_count+1'b1; + (* ASYNC_REG="TRUE", SHREG_EXTRACT="NO" *) reg [2:0] ui_reset_pipe=7; + always @(posedge ui_clk or posedge ui_rst) if(ui_rst) ui_reset_pipe<=7; + else ui_reset_pipe<={ui_reset_pipe[1:0],1'b0}; + wire ui_aresetn=~ui_reset_pipe[2]; + wire cpu_run,exited,loader_error;wire [31:0] exit_code;reg [24:0] heartbeat=0; + always @(posedge clk) if(reset) heartbeat<=0;else heartbeat<=heartbeat+1'b1; + assign led={heartbeat[24],cpu_run && !reset,loader_error || (exited && exit_code!=0),calib_sync[1]}; + wire [3:0] ddr_awid; + wire [27:0] ddr_awaddr; + wire [7:0] ddr_awlen; + wire [2:0] ddr_awsize; + wire [1:0] ddr_awburst; + wire ddr_awvalid; + wire ddr_awready; + wire [127:0] ddr_wdata; + wire [15:0] ddr_wstrb; + wire ddr_wlast; + wire ddr_wvalid; + wire ddr_wready; + wire [3:0] ddr_bid; + wire [1:0] ddr_bresp; + wire ddr_bvalid; + wire ddr_bready; + wire [3:0] ddr_arid; + wire [27:0] ddr_araddr; + wire [7:0] ddr_arlen; + wire [2:0] ddr_arsize; + wire [1:0] ddr_arburst; + wire ddr_arvalid; + wire ddr_arready; + wire [3:0] ddr_rid; + wire [127:0] ddr_rdata; + wire [1:0] ddr_rresp; + wire ddr_rlast; + wire ddr_rvalid; + wire ddr_rready; + wire [3:0] ui_awid; + wire [27:0] ui_awaddr; + wire [7:0] ui_awlen; + wire [2:0] ui_awsize; + wire [1:0] ui_awburst; + wire ui_awvalid; + wire ui_awready; + wire [127:0] ui_wdata; + wire [15:0] ui_wstrb; + wire ui_wlast; + wire ui_wvalid; + wire ui_wready; + wire [3:0] ui_bid; + wire [1:0] ui_bresp; + wire ui_bvalid; + wire ui_bready; + wire [3:0] ui_arid; + wire [27:0] ui_araddr; + wire [7:0] ui_arlen; + wire [2:0] ui_arsize; + wire [1:0] ui_arburst; + wire ui_arvalid; + wire ui_arready; + wire [3:0] ui_rid; + wire [127:0] ui_rdata; + wire [1:0] ui_rresp; + wire ui_rlast; + wire ui_rvalid; + wire ui_rready; + toy_a7_platform #(.FLASH_BOOT(FLASH_BOOT)) platform ( + .clk(clk), + .reset(reset), + .uart_rx_in(uart_txd_in), + .uart_tx_out(uart_rxd_out), + .cpu_run(cpu_run), + .exited(exited), + .loader_error(loader_error), + .exit_code(exit_code), + .flash_miso(flash_miso),.flash_mosi(flash_mosi),.flash_sck(flash_sck), + .flash_cs_n(flash_cs_n),.flash_recovery(flash_recovery), + .ddr_awid(ddr_awid), + .ddr_awaddr(ddr_awaddr), + .ddr_awlen(ddr_awlen), + .ddr_awsize(ddr_awsize), + .ddr_awburst(ddr_awburst), + .ddr_awvalid(ddr_awvalid), + .ddr_awready(ddr_awready), + .ddr_wdata(ddr_wdata), + .ddr_wstrb(ddr_wstrb), + .ddr_wlast(ddr_wlast), + .ddr_wvalid(ddr_wvalid), + .ddr_wready(ddr_wready), + .ddr_bid(ddr_bid), + .ddr_bresp(ddr_bresp), + .ddr_bvalid(ddr_bvalid), + .ddr_bready(ddr_bready), + .ddr_arid(ddr_arid), + .ddr_araddr(ddr_araddr), + .ddr_arlen(ddr_arlen), + .ddr_arsize(ddr_arsize), + .ddr_arburst(ddr_arburst), + .ddr_arvalid(ddr_arvalid), + .ddr_arready(ddr_arready), + .ddr_rid(ddr_rid), + .ddr_rdata(ddr_rdata), + .ddr_rresp(ddr_rresp), + .ddr_rlast(ddr_rlast), + .ddr_rvalid(ddr_rvalid), + .ddr_rready(ddr_rready) + ); + toy_axi_cdc memory_cdc ( + .s_axi_aclk(clk), + .s_axi_aresetn(!reset), + .m_axi_aclk(ui_clk), + .m_axi_aresetn(ui_aresetn), + .s_axi_awid(ddr_awid), + .s_axi_awaddr(ddr_awaddr), + .s_axi_awlen(ddr_awlen), + .s_axi_awsize(ddr_awsize), + .s_axi_awburst(ddr_awburst), + .s_axi_awvalid(ddr_awvalid), + .s_axi_awready(ddr_awready), + .s_axi_wdata(ddr_wdata), + .s_axi_wstrb(ddr_wstrb), + .s_axi_wlast(ddr_wlast), + .s_axi_wvalid(ddr_wvalid), + .s_axi_wready(ddr_wready), + .s_axi_bid(ddr_bid), + .s_axi_bresp(ddr_bresp), + .s_axi_bvalid(ddr_bvalid), + .s_axi_bready(ddr_bready), + .s_axi_arid(ddr_arid), + .s_axi_araddr(ddr_araddr), + .s_axi_arlen(ddr_arlen), + .s_axi_arsize(ddr_arsize), + .s_axi_arburst(ddr_arburst), + .s_axi_arvalid(ddr_arvalid), + .s_axi_arready(ddr_arready), + .s_axi_rid(ddr_rid), + .s_axi_rdata(ddr_rdata), + .s_axi_rresp(ddr_rresp), + .s_axi_rlast(ddr_rlast), + .s_axi_rvalid(ddr_rvalid), + .s_axi_rready(ddr_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0), + .s_axi_awregion(4'd0), + .s_axi_arregion(4'd0), + .m_axi_awid(ui_awid), + .m_axi_awaddr(ui_awaddr), + .m_axi_awlen(ui_awlen), + .m_axi_awsize(ui_awsize), + .m_axi_awburst(ui_awburst), + .m_axi_awvalid(ui_awvalid), + .m_axi_awready(ui_awready), + .m_axi_wdata(ui_wdata), + .m_axi_wstrb(ui_wstrb), + .m_axi_wlast(ui_wlast), + .m_axi_wvalid(ui_wvalid), + .m_axi_wready(ui_wready), + .m_axi_bid(ui_bid), + .m_axi_bresp(ui_bresp), + .m_axi_bvalid(ui_bvalid), + .m_axi_bready(ui_bready), + .m_axi_arid(ui_arid), + .m_axi_araddr(ui_araddr), + .m_axi_arlen(ui_arlen), + .m_axi_arsize(ui_arsize), + .m_axi_arburst(ui_arburst), + .m_axi_arvalid(ui_arvalid), + .m_axi_arready(ui_arready), + .m_axi_rid(ui_rid), + .m_axi_rdata(ui_rdata), + .m_axi_rresp(ui_rresp), + .m_axi_rlast(ui_rlast), + .m_axi_rvalid(ui_rvalid), + .m_axi_rready(ui_rready), + .m_axi_awlock(), + .m_axi_arlock(), + .m_axi_awcache(), + .m_axi_arcache(), + .m_axi_awprot(), + .m_axi_arprot(), + .m_axi_awqos(), + .m_axi_arqos(), + .m_axi_awregion(), + .m_axi_arregion() + ); + arty_ddr3 ddr_controller ( + .ddr3_dq(ddr3_dq), + .ddr3_dqs_n(ddr3_dqs_n), + .ddr3_dqs_p(ddr3_dqs_p), + .ddr3_addr(ddr3_addr), + .ddr3_ba(ddr3_ba), + .ddr3_ras_n(ddr3_ras_n), + .ddr3_cas_n(ddr3_cas_n), + .ddr3_we_n(ddr3_we_n), + .ddr3_reset_n(ddr3_reset_n), + .ddr3_ck_p(ddr3_ck_p), + .ddr3_ck_n(ddr3_ck_n), + .ddr3_cke(ddr3_cke), + .ddr3_cs_n(ddr3_cs_n), + .ddr3_dm(ddr3_dm), + .ddr3_odt(ddr3_odt), + .sys_clk_i(sys_clk), + .clk_ref_i(ref_clk), + .sys_rst(mig_resetn), + .ui_clk(ui_clk), + .ui_clk_sync_rst(ui_rst), + .mmcm_locked(mig_locked), + .aresetn(ui_aresetn), + .init_calib_complete(calibrated), + .device_temp(), + .app_sr_req(1'b0), + .app_ref_req(1'b0), + .app_zq_req(1'b0), + .app_sr_active(), + .app_ref_ack(), + .app_zq_ack(), + .s_axi_awid(ui_awid), + .s_axi_awaddr(ui_awaddr), + .s_axi_awlen(ui_awlen), + .s_axi_awsize(ui_awsize), + .s_axi_awburst(ui_awburst), + .s_axi_awvalid(ui_awvalid), + .s_axi_awready(ui_awready), + .s_axi_wdata(ui_wdata), + .s_axi_wstrb(ui_wstrb), + .s_axi_wlast(ui_wlast), + .s_axi_wvalid(ui_wvalid), + .s_axi_wready(ui_wready), + .s_axi_bid(ui_bid), + .s_axi_bresp(ui_bresp), + .s_axi_bvalid(ui_bvalid), + .s_axi_bready(ui_bready), + .s_axi_arid(ui_arid), + .s_axi_araddr(ui_araddr), + .s_axi_arlen(ui_arlen), + .s_axi_arsize(ui_arsize), + .s_axi_arburst(ui_arburst), + .s_axi_arvalid(ui_arvalid), + .s_axi_arready(ui_arready), + .s_axi_rid(ui_rid), + .s_axi_rdata(ui_rdata), + .s_axi_rresp(ui_rresp), + .s_axi_rlast(ui_rlast), + .s_axi_rvalid(ui_rvalid), + .s_axi_rready(ui_rready), + .s_axi_awlock(1'b0), + .s_axi_arlock(1'b0), + .s_axi_awcache(4'b0011), + .s_axi_arcache(4'b0011), + .s_axi_awprot(3'd0), + .s_axi_arprot(3'd0), + .s_axi_awqos(4'd0), + .s_axi_arqos(4'd0) + ); +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_rx.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_rx.sv new file mode 100644 index 0000000..567b8b4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_rx.sv @@ -0,0 +1,40 @@ +// 8-N-1 receiver. Data is sampled in the middle of each bit after a verified +// start bit. A held-low/broken line reports one framing error, then waits high. +module uart_rx #( + parameter integer DIVISOR = 434 +) ( + input wire clk, reset, rx, + output reg valid, + output reg [7:0] data, + output reg frame_error +); + (* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *) reg rx_meta = 1, rx_sync = 1; + always @(posedge clk) begin rx_meta <= rx; rx_sync <= rx_meta; end + localparam integer WIDTH = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + localparam [2:0] IDLE=0, START=1, DATA=2, STOP=3, WAIT_HIGH=4; + reg [2:0] state, bit_index; + reg [WIDTH-1:0] count; + reg [7:0] shift; + always @(posedge clk) begin + valid <= 0; frame_error <= 0; + if (reset) begin + state <= IDLE; bit_index <= 0; count <= 0; shift <= 0; data <= 0; + end else case (state) + IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + START: if (count != 0) count <= count - 1'b1; + else if (rx_sync) state <= IDLE; + else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + DATA: if (count != 0) count <= count - 1'b1; + else begin + shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + if (bit_index == 7) state <= STOP; + else bit_index <= bit_index + 1'b1; + end + STOP: if (count != 0) count <= count - 1'b1; + else if (rx_sync) begin data <= shift; valid <= 1; state <= IDLE; end + else begin frame_error <= 1; state <= WAIT_HIGH; end + WAIT_HIGH: if (rx_sync) state <= IDLE; + default: state <= IDLE; + endcase + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_tx.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_tx.sv new file mode 100644 index 0000000..11f6e4a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/uart_tx.sv @@ -0,0 +1,37 @@ +module uart_tx #( + parameter integer DIVISOR = 434 // 50 MHz / 115200, error < 0.01%. +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [7:0] data, + output wire ready, + output wire tx +); + localparam integer COUNT_BITS = $clog2(DIVISOR) < 1 ? 1 : $clog2(DIVISOR); + reg [COUNT_BITS-1:0] count; + reg [9:0] shift; + reg [3:0] bits_left; + assign ready = bits_left == 0; + assign tx = shift[0]; + + always @(posedge clk) begin + if (reset) begin + count <= 0; + shift <= 10'h3ff; + bits_left <= 0; + end else if (ready) begin + if (valid) begin + shift <= {1'b1, data, 1'b0}; + bits_left <= 10; + count <= DIVISOR - 1; + end + end else if (count == 0) begin + shift <= {1'b1, shift[9:1]}; + bits_left <= bits_left - 1'b1; + count <= DIVISOR - 1; + end else begin + count <= count - 1'b1; + end + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/License.txt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/License.txt new file mode 100644 index 0000000..b76cf0c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/License.txt @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2021 Digilent, Inc. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. \ No newline at end of file diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/MANIFEST.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/MANIFEST.json new file mode 100644 index 0000000..ae5699f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/MANIFEST.json @@ -0,0 +1,24 @@ +{ + "repository": "Digilent/vivado-boards", + "commit": "36f34ab687b7fa9c778b779d027f3bce63b3ace9", + "vendor_revision": "E.0", + "physical_board_revision": "unknown", + "files": { + "board.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/board.xml", + "sha256": "5bd9a7ca97ccb2fef617515a14401166464b45a06684d663c0be1a06b02a86df" + }, + "part0_pins.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/part0_pins.xml", + "sha256": "50aa844aa9c78af6342de68ae3c980f7618716447b28282878d5a106f86fed31" + }, + "mig.prj": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/mig.prj", + "sha256": "914a9e4bb1b3002837592944cdf49f8dfbaf4d112552dd8b5be48602ff1ac329" + }, + "preset.xml": { + "url": "https://raw.githubusercontent.com/Digilent/vivado-boards/36f34ab687b7fa9c778b779d027f3bce63b3ace9/new/board_files/arty-a7-100/E.0/1.0/preset.xml", + "sha256": "ff95b9b976323fefa588873588dfa2bdce1673759c0a9e91c12ee9f2a2955bce" + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/board.xml b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/board.xml new file mode 100644 index 0000000..50f4535 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/board.xml @@ -0,0 +1,1247 @@ + + + + + E.0 + +1.0 +Arty A7-100 + + + + + DDR3 board interface, it can use MIG IP for connection. + + + + + + 4-position user DIP Switches + + + + + + + + + + + + + + + + Secondary interface to communicate with ethernet phy. + + + + + + + + + + + + + + + + + + + + + + + + + Primary interface to communicate with ethernet phy in MII mode. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Shield I2C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + I2C Pullups to enable shield I2C + + + + + + + + + + + + + + 4 LEDs + + + + + + + + + + + + + + + + 4 Push Buttons + + + + + + + + + + + + + + + + Quad SPI Flash + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Onboard Reset Button + + + + + + + + + + + + + + + + 4 RGB LEDs + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 256 MB DDR3L memory SODIMM + + + + + + + DIP Switches 3 to 0 + + + PHY Ethernet on the board + + + + + + + + + + + Shield i2c + + + Shield i2c pullups, must pull high if using the shield I2C on J3 + + + LEDs 3 to 0 + + + Push buttons 3 to 0 + + + 16 MB of nonvolatile storage that can be used for configuration or data storage + + + CPU Reset Push Button, active low + + + RGB leds 12 to 0 (3 per LED) + + + Shield pins 0 through 19 + + + Shield pins 26 through 41 + + + Shield SPI + + + 3.3V Single-Ended 100MHz oscillator used as system clock on the board + + + USB-to-UART Bridge, which allows a connection to a host computer with a USB port + + + Pmod Connector JA + + + Pmod Connector JB + + + Pmod Connector JC + + + Pmod Connector JD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/mig.prj b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/mig.prj new file mode 100644 index 0000000..1bff709 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/mig.prj @@ -0,0 +1,134 @@ + + + + design_1_mig_7series_0_0 + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a100t-csg324/-1 + 2.3 + No Buffer + No Buffer + ACTIVE LOW + FALSE + 1 + 50 Ohms + 0 + + DDR3_SDRAM/Components/MT41K128M16XX-15E + 3000 + 1.8V + 4:1 + 166.666 + 0 + 666 + 1.000 + 1 + 1 + 1 + 1 + 16 + 1 + 1 + Disabled + Normal + FALSE + + 14 + 10 + 3 + 1.35V + 268435456 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 5 + Normal + No + Slow Exit + Enable + RZQ/6 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 28 + 128 + 4 + 0 + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/part0_pins.xml b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/part0_pins.xml new file mode 100644 index 0000000..dc32e54 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/part0_pins.xml @@ -0,0 +1,156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/preset.xml b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/preset.xml new file mode 100644 index 0000000..ec20fb4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/board/vendor/preset.xml @@ -0,0 +1,418 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/build.sbt b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/build.sbt new file mode 100644 index 0000000..79eb11f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/build.sbt @@ -0,0 +1,70 @@ +ThisBuild / scalaVersion := "2.13.16" +ThisBuild / organization := "srtp.fpga" +ThisBuild / version := "0.1.0" +ThisBuild / scalacOptions ++= Seq("-language:reflectiveCalls", "-Ymacro-annotations", "-deprecation", "-feature") + +lazy val chiselSettings = Seq( + scalaVersion := "2.13.16", + libraryDependencies += "org.chipsalliance" %% "chisel" % "6.7.0", + addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.7.0" cross CrossVersion.full) +) +lazy val cde = project.in(file("thirdparty/cde")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "cde/src/chipsalliance" +) +lazy val diplomacy = project.in(file("thirdparty/diplomacy/diplomacy")).dependsOn(cde).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "src/diplomacy", + libraryDependencies += "com.lihaoyi" %% "sourcecode" % "0.3.0" +) +lazy val hardfloat = project.in(file("thirdparty/hardfloat/hardfloat")).dependsOn(cde).settings(chiselSettings) +lazy val macros = project.in(file("thirdparty/rocket-chip/macros")).settings( + libraryDependencies += "org.scala-lang" % "scala-reflect" % "2.13.16" +) +lazy val rocket = project.in(file("thirdparty/rocket-chip")).dependsOn(cde, diplomacy, hardfloat, macros).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "src/main/scala") ** "*.scala").get + original.filterNot(f => f.getName == "FPU.scala") ++ + ((baseDirectory.value / "../../patches/rocket") ** "*.scala").get + }, + libraryDependencies ++= Seq( + "com.lihaoyi" %% "mainargs" % "0.5.0", + "org.json4s" %% "json4s-jackson" % "4.0.5", + "org.scala-graph" %% "graph-core" % "1.13.5" + ) +) +lazy val inclusive = project.in(file("thirdparty/inclusive-cache")).dependsOn(rocket).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "design/craft" +) +lazy val midas = project.in(file("thirdparty/firesim-compile")).settings(chiselSettings).settings( + Compile / unmanagedSourceDirectories += baseDirectory.value / "../firesim/sim/midas/targetutils/src/main/scala" +) +lazy val gemmini = project.in(file("thirdparty/gemmini-compile")).dependsOn(rocket, midas).settings(chiselSettings).settings( + Compile / unmanagedSources := { + val original = ((baseDirectory.value / "../gemmini/src/main/scala") ** "*.scala").get + original.filterNot(f => Set("PE.scala", "Tile.scala", "Mesh.scala")(f.getName)) ++ + ((baseDirectory.value / "../../patches/gemmini") ** "*.scala").get + }, + Compile / unmanagedResourceDirectories += baseDirectory.value / "../gemmini/src/main/resources" +) +lazy val root = project.in(file(".")).dependsOn(inclusive, gemmini).settings(chiselSettings).settings( + name := "toy-arty-a7-linux", + libraryDependencies ++= Seq( + "com.lihaoyi" %% "upickle" % "3.3.1", + "tech.sparse" %% "toml-scala" % "0.2.2" + ), + Compile / unmanagedSources ++= { + val upstream = baseDirectory.value / "upstream" + val framework = upstream / "arch/src/main/scala/framework" + val directories = Seq("balldomain", "builtin", "dpi", "frontend", "gpdomain", "memdomain", "top", + "system/core/rocket", "system/core/accelerator", "system/tile") + val shared = directories.flatMap(d => ((framework / d) ** "*.scala").get) + .filterNot(f => Set("WithBuckyballTiles.scala", "WithBoomTile.scala", "MemMidend.scala", "MemStorer.scala", "PrivateMemBackend.scala", "SubROB.scala", "GlobalROB.scala", "MemFrontend.scala", "MemLoader.scala")(f.getName)) + shared ++ ((baseDirectory.value / "patches/framework") ** "*.scala").get ++ + ((baseDirectory.value / "patches/buckyball") ** "*.scala").get ++ ((upstream / "arch/src/main/scala/sims/hash") ** "*.scala").get ++ Seq("gemmini", "trace", "mxfp2int", "relu").flatMap { name => + val ball = upstream / "examples/balls" / name + ((ball / "arch/src/main/scala") ** "*.scala").get.filterNot(f => + Set("GemminiExCtrl.scala", "GemminiExCtrlDefs.scala", + "GemminiExCtrlComputeFeedState.scala", "GemminiExCtrlStoreOps.scala", + "GemminiExCtrlPreloadStates.scala", "GemminiExCtrlCmdStates.scala", "GemminiBall.scala", "LoopMatmulUnroller.scala")(f.getName)) ++ ((ball / "configs") ** "*.scala").get + } + } +) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/patches/framework/GlobalROB.scala b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/patches/framework/GlobalROB.scala new file mode 100644 index 0000000..750c2a3 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/patches/framework/GlobalROB.scala @@ -0,0 +1,599 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.frontend.scoreboard.{BankAccessInfo, BankAliasTable, BankScoreboard} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT +import framework.memdomain.backend.shared.SharedMemLayout +import framework.memdomain.backend.banks.btrace.{BTraceDPI, PhysicalBankHash} + +@instantiable +class GlobalROB(val b: GlobalConfig, useOperandRam: Boolean = true) extends Module { + + val robDepth = b.frontend.rob_entries + val idWidth = log2Up(robDepth) + val scoreBankNum = b.memDomain.virtualBankCount + robDepth + val sharedHashCount = if (b.memDomain.sharedEnable) SharedMemLayout.totalBank(b) else 0 + val physicalBankCount = b.memDomain.bankNum + sharedHashCount + + require( + b.frontend.vbank_id_upper_bound < b.memDomain.virtualBankCount, + s"vbank_id_upper_bound(${b.frontend.vbank_id_upper_bound}) must be < virtualBankCount(${b.memDomain.virtualBankCount})" + ) + + @public + val io = IO(new Bundle { + val hart_id = Input(UInt(b.tile.xLen.W)) + val alloc = Flipped(new DecoupledIO(new PostGDCmd(b))) + val issue = new DecoupledIO(new GlobalRobEntry(b)) + val complete = Flipped(new DecoupledIO(UInt(idWidth.W))) + + val empty = Output(Bool()) + val full = Output(Bool()) + val head_ptr = Output(UInt(idWidth.W)) + val issued_count = Output(UInt(log2Up(robDepth + 1).W)) + val entry_valid = Output(Vec(robDepth, Bool())) + val entry_complete = Output(Vec(robDepth, Bool())) + + val subRobActive = Input(Bool()) + val inst_ids = Output(Vec(robDepth, UInt(64.W))) + + val bank_hashes = + if (b.sim.diffTest) { + Some(Input(Vec(physicalBankCount, new PhysicalBankHash(b)))) + } else { + None + } + + }) + + // --------------------------------------------------------------------------- + // BAT + Bank Scoreboard + // --------------------------------------------------------------------------- + val bat: Instance[BankAliasTable] = Instantiate( + new BankAliasTable( + bankIdLen = b.frontend.bank_id_len, + vbankUpper = b.memDomain.virtualBankCount - 1, + robEntries = robDepth + ) + ) + + val scoreboard: Instance[BankScoreboard] = + Instantiate(new BankScoreboard(b.frontend.bank_id_len, scoreBankNum, robDepth)) + + // --------------------------------------------------------------------------- + // Instruction trace (DPI-C, defined in ITraceDPI.scala) + // --------------------------------------------------------------------------- + val itraceAlloc = Module(new ITraceDPI) + val itraceIssue = Module(new ITraceDPI) + val itraceComp = Module(new ITraceDPI) + + for (t <- Seq(itraceAlloc, itraceIssue, itraceComp)) { + t.io.clock := clock + t.io.reset := reset.asBool + t.io.is_issue := 0.U + t.io.hart_id := io.hart_id + t.io.rob_id := 0.U + t.io.inst_id := 0.U + t.io.domain_id := 0.U + t.io.funct := 0.U + t.io.pc := 0.U + t.io.rs1_data := 0.U + t.io.rs2_data := 0.U + t.io.enable := false.B + } + + // --------------------------------------------------------------------------- + // Storage + // --------------------------------------------------------------------------- + val robEntries = RegInit(VecInit(Seq.fill(robDepth)(0.U.asTypeOf(new GlobalRobEntry(b))))) + // Only the issued payload needs the full operands. Keep existing copies for + // trace/commit observation; Vivado removes trace-only bits with DPI disabled. + // MSET's low rs2 bits stay in registers for the parallel commit scan. + private val operandWidth = b.tile.xLen + private val operandRam = if (useOperandRam) { + Some(SyncReadMem(robDepth, UInt((2 * operandWidth).W)).suggestName("robOperands")) + } else None + val robValid = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val instIds = RegInit(VecInit(Seq.fill(robDepth)(0.U(64.W)))) + val nextInstId = RegInit(1.U(64.W)) + + val statusHashes = + if (b.sim.diffTest) { + Some(RegInit(VecInit(Seq.fill(robDepth)(VecInit(Seq.fill(3)(0.U(32.W))))))) + } else { + None + } + + io.inst_ids := instIds + + val headPtr = RegInit(0.U(idWidth.W)) + val tailPtr = RegInit(0.U(idWidth.W)) + val issuedCount = RegInit(0.U(log2Up(robDepth + 1).W)) + private val bankColWidth = b.memDomain.groupCountWidth + val bankCols = RegInit(VecInit(Seq.fill(b.memDomain.virtualBankCount)(0.U(bankColWidth.W)))) + // In-flight ownership is tracked in the architectural vbank namespace. + private val vbankMaskWidth = b.memDomain.virtualBankCount + val vbankBusy = RegInit(0.U(vbankMaskWidth.W)) + + // Dependency state is maintained incrementally instead of rebuilding all + // older-entry comparisons every cycle. A bit in slot k names the ROB slot + // that currently blocks k. Ordinary RAW dependencies disappear at complete; + // dependencies involving a mapping/config instruction disappear at commit. + // Keeping one union mask is sufficient because a config dependency is never + // allowed to clear earlier than commit, even when it also looks like a RAW. + val dependencyMask = RegInit(VecInit(Seq.fill(robDepth)(0.U(robDepth.W)))) + + val isEmpty = headPtr === tailPtr && !robValid(headPtr) + val isFull = headPtr === tailPtr && robValid(headPtr) + + def nextPtr(p: UInt): UInt = Mux(p === (robDepth - 1).U, 0.U, p + 1.U) + def wrapPtr(v: UInt): UInt = Mux(v >= robDepth.U, v - robDepth.U, v) + def robIdx(v: UInt): UInt = v(idWidth - 1, 0) + + def isMappingConfig(entry: GlobalRobEntry): Bool = + entry.cmd.domain_id === DomainId.MEM && + (entry.cmd.cmd.funct === MSET_BITPAT) + + def accessUsesBank(access: BankAccessInfo, bank: UInt): Bool = + (access.rd_bank_0_valid && access.rd_bank_0_id === bank) || + (access.rd_bank_1_valid && access.rd_bank_1_id === bank) || + (access.wr_bank_valid && access.wr_bank_id === bank) + + // Build one architectural-vbank mask per ROB slot once, then hazard checks + // become mask intersections instead of repeating ID comparisons. + private val hazardBankCount = b.memDomain.virtualBankCount + + def rawReadMask(access: BankAccessInfo): UInt = { + val rd0 = Mux( + access.rd_bank_0_valid && access.rd_bank_0_id < hazardBankCount.U, + UIntToOH(access.rd_bank_0_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + val rd1 = Mux( + access.rd_bank_1_valid && access.rd_bank_1_id < hazardBankCount.U, + UIntToOH(access.rd_bank_1_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + rd0 | rd1 + } + + def rawWriteMask(access: BankAccessInfo): UInt = Mux( + access.wr_bank_valid && access.wr_bank_id < hazardBankCount.U, + UIntToOH(access.wr_bank_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + + def rawUseMask(access: BankAccessInfo): UInt = + rawReadMask(access) | rawWriteMask(access) + + // --------------------------------------------------------------------------- + // Allocate: enqueue decoded instruction into ROB + // rob_id == tailPtr at allocation time (no separate counter needed) + // --------------------------------------------------------------------------- + val commitMask = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { + commitMask(i) := false.B + } + bat.io.free.valid := commitMask.asUInt.orR + bat.io.free.mask := commitMask + + val commitScan = Wire(Vec(robDepth, Bool())) + val commitKeep = Wire(Vec(robDepth + 1, Bool())) + commitKeep(0) := true.B + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + commitScan(i) := commitKeep(i) && robValid(ptr) && robComplete(ptr) + commitKeep(i + 1) := (if (b.sim.diffTest) false.B else commitScan(i)) + } + val hasCommit = commitScan.asUInt.orR + val tailAlias = Wire(UInt(b.frontend.bank_id_len.W)) + tailAlias := + b.memDomain.virtualBankCount.U(b.frontend.bank_id_len.W) + tailPtr + + val tailAliasLive = WireDefault(false.B) + for (i <- 0 until robDepth) { + when(robValid(i) && !robComplete(i) && accessUsesBank(robEntries(i).renamedBankAccess, tailAlias)) { + tailAliasLive := true.B + } + } + + io.alloc.ready := !isFull && !hasCommit && !tailAliasLive + bat.io.alloc.valid := io.alloc.fire + bat.io.alloc.rob_id := tailPtr + bat.io.alloc.raw := io.alloc.bits.bankAccess + + // Mark write alias as busy in scoreboard at alloc time (not issue time). + scoreboard.alloc.valid := io.alloc.fire && io.alloc.bits.bankAccess.wr_bank_valid + scoreboard.alloc.bits := bat.io.alloc_renamed + + // Bank masks are shared by allocation and issue. This avoids rebuilding the + // UIntToOH decoders once for every older-entry comparison at allocation. + val entryRawReads = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryRawWrites = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryIsConfig = Wire(Vec(robDepth, Bool())) + for (slot <- 0 until robDepth) { + entryRawReads(slot) := rawReadMask(robEntries(slot).cmd.bankAccess) + entryRawWrites(slot) := rawWriteMask(robEntries(slot).cmd.bankAccess) + entryIsConfig(slot) := isMappingConfig(robEntries(slot)) + } + + // A newly allocated entry is always younger than all currently valid ROB + // entries (tailPtr points at the first free slot). Capture its older-entry + // dependencies once here; issue no longer repeats pairwise comparisons. + val allocReadMask = rawReadMask(io.alloc.bits.bankAccess) + val allocWriteMask = rawWriteMask(io.alloc.bits.bankAccess) + val allocIsConfig = io.alloc.bits.domain_id === DomainId.MEM && + (io.alloc.bits.cmd.funct === MSET_BITPAT) + val allocIsBall = io.alloc.bits.domain_id === DomainId.BALL + val allocDependencyBits = Wire(Vec(robDepth, Bool())) + for (older <- 0 until robDepth) { + val olderUseMask = entryRawReads(older) | entryRawWrites(older) + val rawConflict = ((allocReadMask & entryRawWrites(older)) | + (allocWriteMask & olderUseMask)).orR + val configConflict = (allocIsConfig && entryIsConfig(older)) || + ((allocIsConfig || entryIsConfig(older)) && ((allocReadMask | allocWriteMask) & olderUseMask).orR) + val sameBall = allocIsBall && + robEntries(older).cmd.domain_id === DomainId.BALL && + robEntries(older).cmd.ball_bid === io.alloc.bits.ball_bid + // Config conflicts include entries that have completed but are waiting to + // commit. RAW conflicts and same-Ball commands release at completion. + allocDependencyBits(older) := + (robValid(older) && !robComplete(older) && (rawConflict || sameBall)) || + (robValid(older) && configConflict) + } + val allocDependencies = allocDependencyBits.asUInt + val allocUsesInstId = io.alloc.bits.cmd.pc =/= 0.U + + when(io.alloc.fire) { + operandRam.foreach(_.write(tailPtr, Cat(io.alloc.bits.cmd.rs1Data, io.alloc.bits.cmd.rs2Data))) + itraceAlloc.io.is_issue := 2.U + itraceAlloc.io.rob_id := tailPtr + itraceAlloc.io.inst_id := Mux(allocUsesInstId, nextInstId, 0.U) + itraceAlloc.io.domain_id := io.alloc.bits.domain_id + itraceAlloc.io.funct := io.alloc.bits.cmd.funct + itraceAlloc.io.pc := io.alloc.bits.cmd.pc + itraceAlloc.io.rs1_data := io.alloc.bits.cmd.rs1Data + itraceAlloc.io.rs2_data := io.alloc.bits.cmd.rs2Data + itraceAlloc.io.enable := true.B + + robEntries(tailPtr).cmd := io.alloc.bits + robEntries(tailPtr).renamedBankAccess := bat.io.alloc_renamed + robEntries(tailPtr).rob_id := tailPtr + instIds(tailPtr) := Mux(allocUsesInstId, nextInstId, 0.U) + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B + statusHashes.foreach { hashes => + for (slot <- 0 until 3) { + hashes(tailPtr)(slot) := 0.U + } + } + tailPtr := nextPtr(tailPtr) + when(allocUsesInstId) { + nextInstId := nextInstId + 1.U + } + } + + // --------------------------------------------------------------------------- + // Complete: mark entry as completed, release scoreboard resources + // --------------------------------------------------------------------------- + if (b.sim.diffTest) { + val collecting = RegInit(false.B) + val collectCid = Reg(UInt(idWidth.W)) + val collectSlot = Reg(UInt(2.W)) + val collectGroup = Reg(UInt(32.W)) + val currentHash = Reg(UInt(32.W)) + val hashReady = RegInit(false.B) + val hashCid = Reg(UInt(idWidth.W)) + + val incomingAccess = robEntries(io.complete.bits).cmd.bankAccess + val incomingNeedsHash = instIds(io.complete.bits) =/= 0.U && !isMappingConfig(robEntries(io.complete.bits)) && + (incomingAccess.rd_bank_0_valid || incomingAccess.rd_bank_1_valid || incomingAccess.wr_bank_valid) + io.complete.ready := !incomingNeedsHash || (hashReady && hashCid === io.complete.bits) + + when(!collecting && !hashReady && io.complete.valid && incomingNeedsHash) { + collecting := true.B + collectCid := io.complete.bits + collectSlot := Mux(incomingAccess.rd_bank_0_valid, 0.U, Mux(incomingAccess.rd_bank_1_valid, 1.U, 2.U)) + collectGroup := 0.U + currentHash := 0.U + } + + val access = robEntries(collectCid).cmd.bankAccess + val vbank = MuxLookup(collectSlot, access.wr_bank_id)(Seq( + 0.U -> access.rd_bank_0_id, + 1.U -> access.rd_bank_1_id, + 2.U -> access.wr_bank_id + )) + val hasNextSlot = MuxLookup(collectSlot, false.B)(Seq( + 0.U -> (access.rd_bank_1_valid || access.wr_bank_valid), + 1.U -> access.wr_bank_valid + )) + val nextSlot = Mux(collectSlot === 0.U && access.rd_bank_1_valid, 1.U, 2.U) + val matches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + }) + val nextMatches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + 1.U + }) + val physical = Mux1H(matches, io.bank_hashes.get) + def rotateLeft(value: UInt, amount: Int): UInt = Cat(value(31 - amount, 0), value(31, 32 - amount)) + + val mixed = physical.statusHash ^ rotateLeft(physical.groupId, 7) ^ "h9e3779b9".U + val nextHash = rotateLeft(currentHash, 5) ^ mixed ^ rotateLeft(mixed, 13) + + when(collecting) { + assert(PopCount(matches) === 1.U, "BTrace requires exactly one physical bank per vbank group") + when(nextMatches.asUInt.orR) { + currentHash := nextHash + collectGroup := collectGroup + 1.U + }.otherwise { + statusHashes.get(collectCid)(collectSlot) := nextHash + when(hasNextSlot) { + collectSlot := nextSlot + collectGroup := 0.U + currentHash := 0.U + }.otherwise { + collecting := false.B + hashReady := true.B + hashCid := collectCid + } + } + } + + when(io.complete.fire) { + hashReady := false.B + } + } else { + io.complete.ready := true.B + } + + scoreboard.complete.valid := false.B + scoreboard.complete.bits := 0.U.asTypeOf(scoreboard.complete.bits) + + val issueFired = WireDefault(false.B) + val completeIssuedEntry = io.complete.fire && robIssued(io.complete.bits) + + when(io.complete.fire) { + val cid = io.complete.bits + robComplete(cid) := true.B + scoreboard.complete.valid := true.B + scoreboard.complete.bits := robEntries(cid).renamedBankAccess + + itraceComp.io.is_issue := 0.U + itraceComp.io.rob_id := cid + itraceComp.io.inst_id := instIds(cid) + itraceComp.io.domain_id := robEntries(cid).cmd.domain_id + itraceComp.io.funct := robEntries(cid).cmd.cmd.funct + itraceComp.io.pc := robEntries(cid).cmd.cmd.pc + itraceComp.io.rs1_data := robEntries(cid).cmd.cmd.rs1Data + itraceComp.io.rs2_data := robEntries(cid).cmd.cmd.rs2Data + itraceComp.io.enable := true.B + } + + val completedBitMask = Mux( + io.complete.fire, + UIntToOH(io.complete.bits, robDepth), + 0.U(robDepth.W) + ) + + // --------------------------------------------------------------------------- + // Issue: scan from head for first issuable entry (valid && !issued && !complete) + // --------------------------------------------------------------------------- + val scanValid = Wire(Vec(robDepth, Bool())) + val scanReady = Wire(Vec(robDepth, Bool())) + val vbankMasks = Wire(Vec(robDepth, UInt(vbankMaskWidth.W))) + for (slot <- 0 until robDepth) { + // Reuse the raw hazard mask for active-command ownership. + vbankMasks(slot) := entryRawReads(slot) | entryRawWrites(slot) + } + + // Check each candidate against older ROB entries using mask intersections. + // The masks are precomputed once per slot, so this retains the original + // age-sensitive RAW/WAR/WAW semantics without replicating three equality + // comparators for every bank access pair. + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + scoreboard.queryVec(i) := robEntries(ptr).renamedBankAccess + scanReady(i) := scanValid(i) && !scoreboard.hazardVec(i) && + !dependencyMask(ptr).orR && + !(vbankMasks(ptr) & vbankBusy).orR + } + + val hasReady = scanReady.asUInt.orR + val firstReady = PriorityEncoder(scanReady.asUInt) + val actualIssuePtr = robIdx(wrapPtr(headPtr + firstReady)) + + scoreboard.query := robEntries(actualIssuePtr).renamedBankAccess + val canIssue = hasReady + + val issueStageValid = RegInit(false.B) + val issueStageEntry = Reg(new GlobalRobEntry(b)) + val issueStageFire = issueStageValid && !io.subRobActive && io.issue.ready + val issueStageReady = !issueStageValid || issueStageFire + + // Keep the wide ROB entry and bank-column mux one register boundary away + // from the age/scoreboard scan. The pointer stage can accept one candidate + // per cycle; the payload stage drains at one per cycle, so steady-state II + // remains one while the extra latency is hidden by in-flight commands. + val issuePtrValid = RegInit(false.B) + val issuePtr = Reg(UInt(idWidth.W)) + val issuePtrFire = issuePtrValid && issueStageReady + val issuePtrReady = !issuePtrValid || issuePtrFire + val issueLoad = canIssue && !io.subRobActive && issuePtrReady + val issuePayload = Wire(new GlobalRobEntry(b)) + issuePayload := robEntries(issuePtr) + operandRam.foreach { memory => + // Read at pointer selection, then re-read while that pointer is stalled. + // Replacement selects the new pointer; the current response is consumed + // before the next edge. This preserves the existing two-stage issue timing. + val readAddress = Mux(issueLoad, actualIssuePtr, issuePtr) + val readEnable = issueLoad || issuePtrValid + val operands = memory.read(readAddress, readEnable) + issuePayload.cmd.cmd.rs1Data := operands(2 * operandWidth - 1, operandWidth) + issuePayload.cmd.cmd.rs2Data := operands(operandWidth - 1, 0) + when(io.alloc.fire && readEnable) { + assert(tailPtr =/= readAddress, "ROB operand RAM read/write collision") + } + } + issuePayload.cmd.op1_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_0_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_0_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.op2_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_1_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_1_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.wr_col := Mux( + issuePayload.cmd.bankAccess.wr_bank_valid, + bankCols(issuePayload.cmd.bankAccess.wr_bank_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + + io.issue.valid := issueStageValid && !io.subRobActive + io.issue.bits := issueStageEntry + + when(issuePtrReady) { + issuePtrValid := issueLoad + when(issueLoad) { + issuePtr := actualIssuePtr + } + } + when(issueStageReady) { + issueStageValid := issuePtrValid + when(issuePtrFire) { + issueStageEntry := issuePayload + } + } + + scoreboard.issue.valid := false.B + scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) + + when(issueLoad) { + robIssued(actualIssuePtr) := true.B + issueFired := true.B + scoreboard.issue.valid := true.B + scoreboard.issue.bits := robEntries(actualIssuePtr).renamedBankAccess + + itraceIssue.io.is_issue := 1.U + itraceIssue.io.rob_id := robEntries(actualIssuePtr).rob_id + itraceIssue.io.inst_id := instIds(actualIssuePtr) + itraceIssue.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itraceIssue.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itraceIssue.io.pc := robEntries(actualIssuePtr).cmd.cmd.pc + itraceIssue.io.rs1_data := robEntries(actualIssuePtr).cmd.cmd.rs1Data + itraceIssue.io.rs2_data := robEntries(actualIssuePtr).cmd.cmd.rs2Data + itraceIssue.io.enable := true.B + } + + // Preserve the original update ordering when issue and complete coincide: + // a completion clears ownership after the newly issued transaction marks + // its banks busy. + val issuedVbankMask = Mux(issueLoad, vbankMasks(actualIssuePtr), 0.U) + val completedVbankMask = Mux(io.complete.fire, vbankMasks(io.complete.bits), 0.U) + when(issueLoad || io.complete.fire) { + vbankBusy := + (vbankBusy & ~completedVbankMask) | issuedVbankMask + } + + issuedCount := issuedCount + issueFired.asUInt - completeIssuedEntry.asUInt + + // --------------------------------------------------------------------------- + // Commit: clear completed entries. + // Explicitly skip entries being allocated or completed this cycle. + // --------------------------------------------------------------------------- + for (i <- 0 until robDepth) { + val hits = (0 until robDepth).map { off => + val ptr = robIdx(wrapPtr(headPtr + off.U)) + commitScan(off) && ptr === i.U + } + commitMask(i) := hits.reduce(_ || _) + when(commitMask(i)) { + when(robEntries(i).cmd.domain_id === DomainId.MEM && robEntries(i).cmd.cmd.funct === MSET_BITPAT) { + val bankId = robEntries(i).cmd.bankAccess.wr_bank_id + val bank = bankId(b.memDomain.vbankIdWidth - 1, 0) + val col = robEntries(i).cmd.cmd.rs2Data(9, 5) + when(robEntries(i).cmd.cmd.rs2Data(10)) { + val fullCol = + if (b.memDomain.sharedEnable) { + Mux( + bankId >= b.frontend.shared_bank_id_base.U && bankId < b.memDomain.virtualBankCount.U, + SharedMemLayout.totalBank(b).U(bankColWidth.W), + b.memDomain.bankNum.U(bankColWidth.W) + ) + } else { + b.memDomain.bankNum.U(bankColWidth.W) + } + bankCols(bank) := Mux(col === 0.U, fullCol, col) + }.otherwise { + bankCols(bank) := 0.U + } + } + robValid(i) := false.B + robIssued(i) := false.B + robComplete(i) := false.B + } + } + + if (b.sim.diffTest) { + val commitIndex = PriorityEncoder(commitMask.asUInt) + val commitAccess = robEntries(commitIndex).cmd.bankAccess + val invalidVbank = "hffffffff".U(32.W) + val btrace = Module(new BTraceDPI) + btrace.io.clock := clock + btrace.io.reset := reset.asBool + btrace.io.instId := instIds(commitIndex) + btrace.io.hartId := io.hart_id + btrace.io.r0Vbank := Mux(commitAccess.rd_bank_0_valid, commitAccess.rd_bank_0_id, invalidVbank) + btrace.io.r0Hash := Mux(commitAccess.rd_bank_0_valid, statusHashes.get(commitIndex)(0), 0.U) + btrace.io.r1Vbank := Mux(commitAccess.rd_bank_1_valid, commitAccess.rd_bank_1_id, invalidVbank) + btrace.io.r1Hash := Mux(commitAccess.rd_bank_1_valid, statusHashes.get(commitIndex)(1), 0.U) + btrace.io.w0Vbank := Mux(commitAccess.wr_bank_valid, commitAccess.wr_bank_id, invalidVbank) + btrace.io.w0Hash := Mux(commitAccess.wr_bank_valid, statusHashes.get(commitIndex)(2), 0.U) + btrace.io.fire := hasCommit && instIds(commitIndex) =/= 0.U && !isMappingConfig(robEntries(commitIndex)) && + (commitAccess.rd_bank_0_valid || commitAccess.rd_bank_1_valid || commitAccess.wr_bank_valid) + } + + // Maintain dependency masks at the same architectural events that gate the + // issue scan. A dependency involving a config entry (on either side) clears + // only at commit; all other dependencies clear at complete. This is the + // union-mask form of the former separate RAW/config masks. + val configEntryMask = entryIsConfig.asUInt + for (slot <- 0 until robDepth) { + val isAllocatedSlot = io.alloc.fire && tailPtr === slot.U + val slotIsConfig = Mux(isAllocatedSlot, allocIsConfig, entryIsConfig(slot)) + // Each dependency bit names the older entry that blocks this slot. Keep a + // config-related edge through completion when either endpoint is config. + val configRelated = configEntryMask | Fill(robDepth, slotIsConfig) + val clearMask = commitMask.asUInt | (completedBitMask & ~configRelated) + when(isAllocatedSlot) { + dependencyMask(slot) := allocDependencies & ~clearMask + }.otherwise { + dependencyMask(slot) := dependencyMask(slot) & ~clearMask + } + } + + val commitCount = PopCount(commitScan) + headPtr := wrapPtr(headPtr + commitCount) + + // --------------------------------------------------------------------------- + // Status outputs + // --------------------------------------------------------------------------- + io.empty := isEmpty + io.full := isFull + io.head_ptr := headPtr + io.issued_count := issuedCount + io.entry_valid := robValid + io.entry_complete := robComplete + +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/bind_fpu_rf.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/bind_fpu_rf.py new file mode 100644 index 0000000..4646b37 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/bind_fpu_rf.py @@ -0,0 +1,33 @@ +"""Bind the already validated zero-latency FPU RF adapter after SRAM binding.""" + +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +output = ROOT / "build/serial-bound" +core = output / "ToyLinuxChip.sv" +original = core.read_text(encoding="utf-8") +matches = list(re.finditer(r"^module regfile_32x65\(.*?^endmodule", original, re.M | re.S)) +assert len(matches) == 1 +match = matches[0] +reference = (ROOT / "rtl/FpuRfOriginal.sv").read_text(encoding="utf-8").strip() +assert match.group() == reference.replace("module FpuRfOriginal(", "module regfile_32x65(") +replacement = (ROOT / "rtl/FpuRfLvt.sv").read_text(encoding="utf-8").strip() +replacement = replacement.replace("module FpuRfLvt(", "module regfile_32x65(") +adapted = original[:match.start()] + replacement + original[match.end():] +core.write_text(adapted, encoding="utf-8", newline="\n") +assert adapted.replace(replacement, match.group(), 1) == original +manifest = json.loads((output / "MEMORY_MANIFEST.json").read_text()) +manifest["baseline_core_rtl_sha256"] = manifest["core_rtl_sha256"] +manifest["core_rtl_sha256"] = hashlib.sha256(core.read_bytes()).hexdigest() +manifest["additional_memory_adapters"] = [{ + "module": "regfile_32x65", "implementation": "two single-write LUTRAM banks and LVT", + "read_ports": 3, "write_ports": 2, "read_latency": 0, + "same_address_write_priority": "W1", "added_cycles": 0, + "adapter_sha256": hashlib.sha256((ROOT / "rtl/FpuRfLvt.sv").read_bytes()).hexdigest(), +}] +(output / "MEMORY_MANIFEST.json").write_text(json.dumps(manifest, indent=2) + "\n") +print("PASS RF adapter matches original port contract; only RF module body replaced") +print("Final core SHA256:", manifest["core_rtl_sha256"]) diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_board_linux.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_board_linux.py new file mode 100644 index 0000000..9007ba9 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_board_linux.py @@ -0,0 +1,91 @@ +"""Boot OpenSBI/Linux/BusyBox on the actual core and board AXI/SCU RTL. + +The external DDR PHY/CDC is a stalled AXI memory model. Loader start is forced +only in this bench; commands enter through the real 1 Mbps UART receiver. +""" +import hashlib +import json +from pathlib import Path +import subprocess + +ROOT=Path(__file__).resolve().parents[1] +OUT=ROOT/"build/board-linux-final" + + +def main(): + OUT.mkdir(parents=True,exist_ok=True) + payload=ROOT/"build/board-software/fw_payload.bin" + # Chunked writes avoid creating a giant intermediate Python string. + with payload.open("rb") as src,(OUT/"payload.hex").open("w") as dst: + while data:=src.read(65536):dst.write("\n".join(f"{b:02x}" for b in data)+"\n") + bench=(ROOT/"build/board-cpu/tb_board_cpu.sv").read_text() + bench=bench.replace("tb_board_cpu","tb_board_linux") + bench=bench.replace("always #5 clk=~clk;", "always #20 clk=~clk;") + first=bench.index(" if(exited &&") + last=bench.index(" end\n axi_smoke_memory",first) + bench=bench[:first]+" if(cycles>500000000) $fatal(1,\"Linux cycle watchdog\");\n"+bench[last:] + bench=bench.replace(".CAPACITY(262144)",".CAPACITY(268435456)") + bench=bench.replace('"smoke.hex"','"payload.hex"') + console=''' + reg [255:0] tail=0; + reg init_seen=0,prompt_seen=0; + integer characters=0; + always @(posedge clk) if(!reset && platform.mmio_tx_valid && platform.tx_ready && cpu_run) begin + tail={tail[247:0],platform.mmio_tx_data};characters=characters+1; + $write("%c",platform.mmio_tx_data);$fflush(); + if(tail[95:0]=="init process") init_seen=1; + if(init_seen && tail[15:0]==16'h2320) prompt_seen=1; + if(tail[183:0]=="PASS LINUX_SYSTEM_CHECK") begin + $display("\\nPASS BOARD_LINUX_USERSPACE cycles=%0d characters=%0d",cycles,characters);$finish; + end + if(tail[95:0]=="Kernel panic") $fatal(1,"Kernel panic"); + end + task automatic send_byte(input [7:0] value); + @(negedge clk);uart_rx_in=0;repeat(25) @(negedge clk); + for(integer n=0;n<8;n=n+1) begin uart_rx_in=value[n];repeat(25) @(negedge clk);end + uart_rx_in=1;repeat(25) @(negedge clk); + // Allow the polled SBI/HVC console to drain its RAM-backed RX FIFO. + repeat(250000) @(negedge clk); + endtask + initial begin + wait(prompt_seen); + $display("\\nSIM_SHELL_PROMPT cycles=%0d",cycles);$fflush(); + send_byte("/");send_byte("r");send_byte("o");send_byte("o");send_byte("t");send_byte("/"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte("_"); + send_byte("s");send_byte("y");send_byte("s");send_byte("t");send_byte("e");send_byte("m");send_byte("_"); + send_byte("c");send_byte("h");send_byte("e");send_byte("c");send_byte("k");send_byte("-"); + send_byte("l");send_byte("i");send_byte("n");send_byte("u");send_byte("x");send_byte(10); + $display("\\nSIM_COMMAND_SENT cycles=%0d overflow=%0d framing=%0d pending_rx=%0d",cycles, + platform.peripherals.overflow,platform.peripherals.framing,platform.peripherals.count);$fflush(); + if(platform.peripherals.overflow || platform.peripherals.framing) $fatal(1,"UART input loss"); + end +''' + bench=bench.replace("endmodule",console+"\nendmodule") + path=OUT/"tb_board_linux.sv" + path.write_text(bench) + files=[ROOT/"build/serial-bound/ToyLinuxChip.sv",ROOT/"build/serial-bound/FpgaMemories.sv", + ROOT/"tests/axi_smoke_memory.sv",path]+[p for p in (ROOT/"board").glob("*.sv") if p.name!="toy_a7_top.sv"] + with (OUT/"compile.log").open("w") as log: + subprocess.run(["verilator","--binary","--timing","-j","8","-Wno-fatal","-DSYNTHESIS", + "-DBUCKYBALL_DISABLE_DPI","--top-module","tb_board_linux","--Mdir",str(OUT/"obj")]+[str(p) for p in files], + stdout=log,stderr=log,check=True,timeout=900) + with (OUT/"simulation.log").open("w") as log: + result=subprocess.run([str(OUT/"obj/Vtb_board_linux")],cwd=OUT,stdout=log,stderr=log,timeout=3000) + transcript=(OUT/"simulation.log").read_text() + result.check_returncode() + required=["OpenSBI","Linux version","PASS VM_COPY_ON_WRITE","PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT","PASS LINUX_TIMER","PASS LINUX_SYSTEM_CHECK","PASS BOARD_LINUX_USERSPACE"] + for marker in required:assert marker in transcript,marker + record=dict(result="PASS_RTL_LINUX_USERSPACE",payload_sha256=hashlib.sha256(payload.read_bytes()).hexdigest(), + checks=required,physical_mig_simulated=False,physical_board_tested=False,uart_rx_command_tested=True) + (OUT/"RESULT.json").write_text(json.dumps(record,indent=2)+"\n") + print(transcript[-2000:]) + + +if __name__=="__main__": + try: + main() + except Exception as error: + OUT.mkdir(parents=True,exist_ok=True) + (OUT/"RESULT.json").write_text(json.dumps(dict(result="FAIL",error=str(error),physical_board_tested=False),indent=2)+"\n") + raise diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_globalrob.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_globalrob.py new file mode 100644 index 0000000..d563932 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/check_globalrob.py @@ -0,0 +1,64 @@ +"""核验同步 RAM 与原寄存器路径逐周期等价，包括背压、绕回和中途复位。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--skip-elaboration", action="store_true") + args = parser.parse_args() + out = ROOT / "build/globalrob-check" + out.mkdir(parents=True, exist_ok=True) + commands = [] + if not args.skip_elaboration: + commands.append((["sbt", "-batch", "runMain fpga.arty.linux.EmitGlobalRobCheck"], + "elaboration.log", 900)) + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + # CIRCT appends named inline resources and the .f index to one emission. + # Keep the untouched emission, compile only Verilog sections. + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', + (out / "GlobalRobCheck.sv").read_text()) + modules = [parts[0]] + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + modules.append(body) + elif name == "firrtl_black_box_resource_files.f": + if not all(line.strip().endswith(".v") for line in body.splitlines() if line.strip()): + raise ValueError("Unexpected inline resource index") + else: + raise ValueError("Unexpected emitted resource: " + name) + rtl = out / "GlobalRobCheck.sim.sv" + rtl.write_text("\n".join(modules)) + commands = [(["verilator", "--binary", "--timing", "--assert", "-j", "4", "-Wno-fatal", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb", "--Mdir", str(out / "obj"), + str(rtl), str(ROOT / "tests/tb_globalrob.sv")], + "compile.log", 600), + ([str(out / "obj/Vtb")], "simulation.log", 60)] + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + transcript = (out / "simulation.log").read_text() + if "PASS GLOBALROB RAM/register cycle comparison" not in transcript: + raise ValueError("GlobalROB passing marker missing") + record = {"result": "PASS", "cycle_equivalence": True, + "coverage": ["accepted operand integrity", "ROB full", "pointer wrap", + "issue backpressure", "SubROB ownership stall", "mid-flight resets", + "concurrent allocation/issue/completion", "complete drain"], + "rtl_sha256": hashlib.sha256((out / "GlobalRobCheck.sv").read_bytes()).hexdigest()} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_fpga_memories.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_fpga_memories.py new file mode 100644 index 0000000..049f434 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_fpga_memories.py @@ -0,0 +1,197 @@ +"""Bind CIRCT 1RW and 1R1W SRAM macros to synchronous FPGA RAM templates. + +The emitted CPU/operator RTL is not rewritten. Only compiler-declared external +memory modules receive implementations. Undefined read results during a write +or disabled cycle hold their previous value. No memory contents are reset. +""" + +import argparse +import hashlib +import json +import re +from pathlib import Path + + +def unpack_emission(raw): + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', raw) + rtl = [parts[0]] + metadata = None + config = None + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + rtl.append(body) + elif name == "metadata/seq_mems.json": + assert metadata is None + metadata = json.loads(body) + elif name.endswith("/memories.conf"): + assert config is None + config = body.strip() + "\n" + elif name == "firrtl_black_box_resource_files.f": + assert all(x.strip().endswith(".v") for x in body.splitlines() if x.strip()) + else: + raise ValueError(f"Unrecognized emitted section: {name}") + assert metadata and config, "Elaborate with --fpga-memories first" + return "\n".join(rtl), metadata, config + + +def validate(metadata, config): + entries = {} + for line in config.splitlines(): + words = line.split() + assert len(words) % 2 == 0 + row = dict(zip(words[::2], words[1::2])) + assert set(row) <= {"name", "depth", "width", "ports", "mask_gran"} + assert row["ports"] in ("rw", "mrw", "write,read", "mwrite,read"), row + assert row["name"] not in entries + entries[row["name"]] = row + assert len(entries) == len(metadata) + for mem in metadata: + name = mem["module_name"] + assert re.fullmatch(r"[A-Za-z_][A-Za-z0-9_]*", name) + topology = (mem["read"], mem["write"], mem["readwrite"]) + assert topology in ((0, 0, 1), (1, 1, 0)) + assert not mem["extra_ports"] + row = entries[name] + assert int(row["depth"]) == mem["depth"] > 1 + assert int(row["width"]) == mem["width"] > 0 + assert (row["ports"] in ("mrw", "mwrite,read")) == mem["masked"] + assert ("," in row["ports"]) == (topology == (1, 1, 0)) + if mem["masked"]: + gran = mem["mask_granularity"] + assert int(row["mask_gran"]) == gran and mem["width"] % gran == 0 + + +def emit_dual_memory(mem, style): + name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) + gran = mem.get("mask_granularity", width) + lanes = width // gran + addr = (depth - 1).bit_length() + mask = f",\n input [{lanes-1}:0] W0_mask" if mem["masked"] else "" + lines = [ + f"""module {name}( + input [{addr-1}:0] R0_addr, + input R0_en, R0_clk, + output reg [{width-1}:0] R0_data, + input [{addr-1}:0] W0_addr, + input W0_en, W0_clk, + input [{width-1}:0] W0_data{mask} +);""" + ] + # Split non-native masks into independent RAM lanes; keep both clocks. + write_enable = "W0_en && W0_mask[lane]" if mem["masked"] else "W0_en" + lines += [ + f" for (genvar lane = 0; lane < {lanes}; lane = lane + 1) begin : lanes", + f' (* ram_style = "{style}" *) reg [{gran-1}:0] ram [0:{depth-1}];', + " always @(posedge W0_clk)", + f" if ({write_enable}) ram[W0_addr] <= W0_data[lane*{gran} +: {gran}];", + " always @(posedge R0_clk)", + f" if (R0_en) R0_data[lane*{gran} +: {gran}] <= ram[R0_addr];", + " end", + "endmodule", + "", + ] + return "\n".join(lines), style + + +def emit_memory(mem, force_block=False): + name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) + gran = mem.get("mask_granularity", width) + lanes = width // gran + addr = (depth - 1).bit_length() + # A 64-row bank fits one LUT RAM per bit. Avoid wasting deep BRAM blocks + # on shallow tags, MMIO banks and SubROB; keep 1024-row data banks in BRAM. + style = "block" if force_block else "distributed" if depth <= 64 else "block" + if mem["read"] == 1: + return emit_dual_memory(mem, style) + ports = [ + f" input [{addr-1}:0] RW0_addr", + " input RW0_en, RW0_clk, RW0_wmode", + f" input [{width-1}:0] RW0_wdata", + f" output reg [{width-1}:0] RW0_rdata", + ] + if mem["masked"]: + ports.append(f" input [{lanes-1}:0] RW0_wmask") + lines = [f"module {name}(" + ",\n".join(ports) + "\n);"] + # Native byte masks share a wide array. Other mask widths get independent + # arrays so e.g. 17-bit L2 tags never require unsupported byte enables. + if not mem["masked"] or gran in (8, 9): + lines += [ + f' (* ram_style = "{style}" *) reg [{width-1}:0] ram [0:{depth-1}];', + " always @(posedge RW0_clk) begin", + " if (RW0_en) begin", + " if (RW0_wmode) begin", + ] + if mem["masked"]: + lines += [ + f" for (integer lane = 0; lane < {lanes}; lane = lane + 1)", + " if (RW0_wmask[lane])", + f" ram[RW0_addr][lane*{gran} +: {gran}] <= " + f"RW0_wdata[lane*{gran} +: {gran}];", + ] + else: + lines.append(" ram[RW0_addr] <= RW0_wdata;") + lines += [ + " end else RW0_rdata <= ram[RW0_addr];", + " end", + " end", + ] + else: + lines += [ + f" for (genvar lane = 0; lane < {lanes}; lane = lane + 1) begin : lanes", + f' (* ram_style = "{style}" *) reg [{gran-1}:0] ram [0:{depth-1}];', + " always @(posedge RW0_clk) begin", + " if (RW0_en) begin", + " if (RW0_wmode) begin", + " if (RW0_wmask[lane]) ram[RW0_addr] <= " + f"RW0_wdata[lane*{gran} +: {gran}];", + f" end else RW0_rdata[lane*{gran} +: {gran}] <= ram[RW0_addr];", + " end", + " end", + " end", + ] + return "\n".join(lines + ["endmodule", ""]), style + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("emission", type=Path) + parser.add_argument("--output-dir", type=Path, required=True) + parser.add_argument("--block-memory", action="append", default=[], + help="明确将指定宏映射到 BRAM，包括 ROB 的浅层宽操作数 RAM") + args = parser.parse_args() + raw = args.emission.read_bytes() + rtl, metadata, config = unpack_emission(raw.decode()) + validate(metadata, config) + requested = set(args.block_memory) + available = {mem["module_name"] for mem in metadata} + if not requested <= available: + raise ValueError("Unknown block memory: " + ", ".join(sorted(requested - available))) + modules, mappings = [], [] + for mem in metadata: + module, style = emit_memory(mem, mem["module_name"] in requested) + modules.append(module) + mappings.append({**mem, "ram_style": style}) + macros = "\n".join(modules) + args.output_dir.mkdir(parents=True, exist_ok=True) + (args.output_dir / "ToyLinuxChip.sv").write_bytes(rtl.encode()) + (args.output_dir / "FpgaMemories.sv").write_bytes(macros.encode()) + (args.output_dir / "memories.conf").write_bytes(config.encode()) + record = { + "emitted_sha256": hashlib.sha256(raw).hexdigest(), + "core_rtl_sha256": hashlib.sha256(rtl.encode()).hexdigest(), + "memory_rtl_sha256": hashlib.sha256(macros.encode()).hexdigest(), + "read_latency": 1, + "write_latency": 1, + "undefined_output_policy": "hold on disabled/write cycle", + "dual_port_collision_policy": "read/write same address is undefined", + "memories": mappings, + } + (args.output_dir / "MEMORY_MANIFEST.json").write_text( + json.dumps(record, indent=2) + "\n" + ) + instances = sum(len(m["hierarchy"]) for m in metadata) + print(f"Bound {len(metadata)} memory types, {instances} instances") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_rob_candidate.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_rob_candidate.py new file mode 100644 index 0000000..615b19d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/prepare_rob_candidate.py @@ -0,0 +1,60 @@ +"""为 ROB 操作数候选显式绑定 BRAM，核对 profile 与已有存储器几何参数。""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess +import sys + +from prepare_fpga_memories import unpack_emission, validate + +ROOT = Path(__file__).resolve().parents[1] + + +def digest(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--baseline-memory-manifest", type=Path, required=True) + args = parser.parse_args() + raw = ROOT / "build/serial-raw/ToyLinuxChip.sv" + profile = json.loads((ROOT / "build/serial-raw/ToyLinuxChip.profile.json").read_text()) + expected = json.loads((ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json").read_text()) + if profile != expected: + raise ValueError("Optimization changed the architectural hardware profile") + _, memories, config = unpack_emission(raw.read_text()) + validate(memories, config) + operands = [m for m in memories if any("robOperands" in h for h in m["hierarchy"])] + if len(operands) != 1: + raise ValueError("Expected one ROB operand memory type") + operand = operands[0] + if (operand["depth"], operand["width"], operand["read"], operand["write"], + operand["readwrite"], operand["masked"], len(operand["hierarchy"])) != (16, 128, 1, 1, 0, False, 1): + raise ValueError("Unexpected ROB memory geometry or topology") + baseline = json.loads(args.baseline_memory_manifest.read_text()) + if baseline["core_rtl_sha256"] != "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779": + raise ValueError("Wrong baseline memory manifest") + def signature(memory): + return tuple(memory.get(k) for k in + ("depth", "width", "read", "write", "readwrite", "masked", "mask_granularity")) + before = sorted((signature(m), len(m["hierarchy"])) for m in baseline["memories"]) + after = sorted((signature(m), len(m["hierarchy"])) for m in memories if m != operand) + if before != after: + raise ValueError("An existing memory geometry/topology changed") + subprocess.run([sys.executable, str(ROOT / "scripts/prepare_fpga_memories.py"), str(raw), + "--output-dir", str(ROOT / "build/serial-bound"), + "--block-memory", operand["module_name"]], check=True, timeout=60) + subprocess.run([sys.executable, str(ROOT / "scripts/bind_fpu_rf.py")], check=True, timeout=60) + record = {"result": "PREPARED_NOT_VALIDATED", "architectural_profile_unchanged": True, + "existing_memory_geometry_unchanged": True, "rob_operand_memory": operand, + "rob_operand_ram_style": "block", "core_rtl_sha256": digest(ROOT / "build/serial-bound/ToyLinuxChip.sv"), + "memory_rtl_sha256": digest(ROOT / "build/serial-bound/FpgaMemories.sv")} + (ROOT / "build/ROB_RAM_PREPARED.json").write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/run_board_regression.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/run_board_regression.py new file mode 100644 index 0000000..6d17780 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/run_board_regression.py @@ -0,0 +1,14 @@ +"""Repeat the unchanged CPU/Gemmini/loop/DMA oracles through board RTL.""" +import json +from pathlib import Path +import subprocess +import sys + +ROOT=Path(__file__).resolve().parents[1] +subprocess.run([sys.executable,str(ROOT/"scripts/check_board.py")],check=True,timeout=180) +records={} +for name in ("cpu","gemmini","loop","dma"): + subprocess.run([sys.executable,str(ROOT/"scripts/check_board_cpu.py"),"--test",name],check=True,timeout=1000) + records[name]=json.loads((ROOT/("build/board-"+name)/"RESULT.json").read_text()) +(ROOT/"build/BOARD_REGRESSION.json").write_text(json.dumps(dict(result="PASS",tests=records),indent=2)+"\n") +print("PASS BOARD_REGRESSION CPU/Gemmini/loop/DMA") diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_board_build.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_board_build.py new file mode 100644 index 0000000..a8c7b7a --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_board_build.py @@ -0,0 +1,92 @@ +"""Run the complete board flow in isolation with a one-hour hard timeout.""" +from datetime import datetime, timedelta, timezone +import argparse +import hashlib +import json +import os +from pathlib import Path +import subprocess +import sys +import time + +ROOT=Path(__file__).resolve().parents[1] +TZ=timezone(timedelta(hours=8)) +EXPECTED="4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779" + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def save(path, record): + temp=path.with_suffix(".tmp") + temp.write_text(json.dumps(record,indent=2)+"\n",encoding="utf-8") + temp.replace(path) + + +def worker(out): + manifest=out/"RUN.json" + record=json.loads(manifest.read_text()) + now=datetime.now(TZ) + script=Path(record.get("execution_script",str(ROOT/"board/build_board.tcl"))) + if "execution_script_sha256" in record: + assert sha(script)==record["execution_script_sha256"] + command=["timeout","--signal=TERM","--kill-after=15s","3600s",os.environ.get("VIVADO", "vivado"), + "-mode","batch","-source",str(script), + "-log",str(out/"vivado.log"),"-journal",str(out/"vivado.jou"),"-tclargs",str(out)] + if record.get("flash_boot"): + command.append("flash") + record.update(status="RUNNING",started_at=now.isoformat(),deadline=(now+timedelta(hours=1)).isoformat(), + command=command,worker_pid=os.getpid()) + started=time.monotonic() + try: + with (out/"console.log").open("w") as log: + p=subprocess.Popen(command,cwd=ROOT,stdin=subprocess.DEVNULL,stdout=log, + stderr=subprocess.STDOUT,start_new_session=True) + record["timeout_process_pid"]=p.pid + save(manifest,record) + code=p.wait() + record.update(exit_code=code,status="TIMED_OUT" if code in (124,137) else "COMPLETED" if code==0 else "FAILED") + except Exception as e: + record.update(status="LAUNCH_FAILED",error=str(e)) + record.update(elapsed_seconds=time.monotonic()-started,finished_at=datetime.now(TZ).isoformat(), + core_unchanged=sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED, + bitstream_generated=(out/"toy_a7.bit").is_file()) + save(manifest,record) + + +def main(): + p=argparse.ArgumentParser(description=__doc__) + p.add_argument("--worker",type=Path) + p.add_argument("--flash",action="store_true",help="Use the validated Flash boot ROM and SPI port") + args=p.parse_args() + if args.worker: + worker(args.worker.resolve());return + assert sha(ROOT/"build/serial-bound/ToyLinuxChip.sv")==EXPECTED + if args.flash: + flash_manifest=json.loads((ROOT/"build/flash-boot/MANIFEST.json").read_text()) + assert flash_manifest["original_core_sha256"]==EXPECTED + assert sha(ROOT/"build/flash-boot/ToyLinuxChip.sv")==flash_manifest["adapted_core_sha256"] + for path in (ROOT/"build").glob("board-*/RUN.json"): + assert json.loads(path.read_text())["status"] not in ("CREATED","RUNNING"),f"Active build: {path}" + out=ROOT/"build"/("board-"+datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + # Snapshot the exact board sources used by this attempt, including failures. + import shutil + shutil.copytree(ROOT/"board",out/"inputs/board") + files={str(p.relative_to(ROOT)):sha(p) for p in (ROOT/"board").rglob("*") if p.is_file()} + record=dict(status="CREATED",timeout_seconds=3600,termination_grace_seconds=15, + output_directory=str(out),part="xc7a100tcsg324-1",core_sha256=EXPECTED, + board_sources=files,core_clock_hz=25000000,uart_baud=1000000, + vendor_revision="E.0",physical_board_revision="unknown",physical_boot_tested=False, + flash_boot=args.flash) + save(out/"RUN.json",record) + with (out/"launcher.log").open("w") as log: + p=subprocess.Popen([sys.executable,str(Path(__file__).resolve()),"--worker",str(out)], + cwd=ROOT,stdout=log,stderr=subprocess.STDOUT,stdin=subprocess.DEVNULL, + start_new_session=True,close_fds=True) + print(json.dumps({"output_directory":str(out),"worker_pid":p.pid,"timeout_seconds":3600})) + + +if __name__=="__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_rob_board_build.py b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_rob_board_build.py new file mode 100644 index 0000000..de57b6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/scripts/start_rob_board_build.py @@ -0,0 +1,63 @@ +"""以独立候选记录执行同一整板流程；不继承旧位流的资格结论。""" + +import argparse +from datetime import datetime +import json +import os +from pathlib import Path +import shutil +import subprocess +import sys + +from start_board_build import ROOT, TZ, save, sha, worker + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--worker", type=Path) + args = parser.parse_args() + if args.worker: + out = args.worker.resolve() + worker(out) + record = json.loads((out / "RUN.json").read_text()) + record["candidate_core_unchanged"] = sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == record["core_sha256"] + record["candidate_memory_unchanged"] = sha(ROOT / "build/serial-bound/FpgaMemories.sv") == record["memory_sha256"] + if not record["candidate_core_unchanged"] or not record["candidate_memory_unchanged"]: + record["status"] = "INPUT_CHANGED_REJECTED" + save(out / "RUN.json", record) + return + prepared = json.loads((ROOT / "build/ROB_RAM_PREPARED.json").read_text()) + for path in ["build/globalrob-check/RESULT.json", "build/BOARD_REGRESSION.json"]: + if json.loads((ROOT / path).read_text())["result"] != "PASS": + raise ValueError("Candidate regression has not passed: " + path) + core = ROOT / "build/serial-bound/ToyLinuxChip.sv" + memories = ROOT / "build/serial-bound/FpgaMemories.sv" + if sha(core) != prepared["core_rtl_sha256"] or sha(memories) != prepared["memory_rtl_sha256"]: + raise ValueError("Candidate inputs changed after preparation") + for path in (ROOT / "build").glob("board-*/RUN.json"): + if json.loads(path.read_text())["status"] in ("CREATED", "RUNNING"): + raise ValueError("An isolated board build is already active") + out = ROOT / "build" / ("board-rob-ram-" + datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + shutil.copytree(ROOT / "board", out / "inputs/board") + files = {str(p.relative_to(ROOT)): sha(p) for p in (ROOT / "board").rglob("*") if p.is_file()} + script = out / "inputs/board/build_board.tcl" + # Keep the input snapshot for audit, execute the identical script at its + # normal root so relative HDL/IP paths resolve without rewriting Tcl. + record = {"status": "CREATED", "optimization": "ROB_OPERAND_BRAM", "timeout_seconds": 3600, + "termination_grace_seconds": 15, "part": "xc7a100tcsg324-1", + "core_sha256": sha(core), "memory_sha256": sha(memories), "board_sources": files, + "execution_script": str(ROOT / "board/build_board.tcl"), "execution_script_sha256": sha(script), + "core_clock_hz": 25000000, "uart_baud": 1000000, + "architectural_profile_unchanged": True, "flash_boot": False, + "physical_boot_tested": False, "inherits_baseline_hardware_qualification": False} + save(out / "RUN.json", record) + with (out / "launcher.log").open("w") as log: + process = subprocess.Popen([sys.executable, str(Path(__file__).resolve()), "--worker", str(out)], + cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, stdin=subprocess.DEVNULL, + start_new_session=True, close_fds=True) + print(json.dumps({"output_directory": str(out), "worker_pid": process.pid, "timeout_seconds": 3600})) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/src/main/scala/EmitGlobalRobCheck.scala b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/src/main/scala/EmitGlobalRobCheck.scala new file mode 100644 index 0000000..859e462 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/src/main/scala/EmitGlobalRobCheck.scala @@ -0,0 +1,110 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.frontend.globalrs.GlobalROB +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT + +/** Cycle comparison of register and synchronous-RAM operand storage. */ +class GlobalRobCheck extends Module { + val seed = IO(Input(UInt(32.W))) + val passed = IO(Output(Bool())) + private val b = OriginalToy.serial + val dut = Module(new GlobalROB(b, useOperandRam = true)) + val reference = Module(new GlobalROB(b, useOperandRam = false)) + val cycle = RegInit(0.U(16.W)) + val random = RegInit(seed) + cycle := cycle + 1.U + random := Cat(random(30, 0), random(31) ^ random(21) ^ random(1) ^ random(0)) + assert(cycle < 9000.U, "GlobalROB drain timeout") + + val source = Module(new Queue(new PostGDCmd(b), 2)) + val generated = Wire(new PostGDCmd(b)) + generated := 0.U.asTypeOf(generated) + val config = random(5, 2) === 0.U + generated.domain_id := Mux(config || random(2), DomainId.MEM, DomainId.BALL) + generated.ball_bid := 0.U + generated.cmd.funct := Mux(config, MSET_BITPAT.value.U(7.W), Mux(random(3), 53.U, 66.U)) + generated.cmd.raw_inst := random + generated.cmd.pc := Cat(random, ~random) + generated.cmd.rs1Data := Cat(random, random ^ "h597bdf03".U) + generated.cmd.rs2Data := Mux(config, + Cat(random, 0.U(21.W), 1.U(1.W), 0.U(3.W), random(1, 0), 0.U(5.W)), + Cat(~random, random ^ "h26ac048e".U)) + generated.bankAccess.rd_bank_0_valid := !config && random(8) + generated.bankAccess.rd_bank_1_valid := !config && random(9) + generated.bankAccess.wr_bank_valid := config || random(10) + generated.bankAccess.rd_bank_0_id := random(14, 11) + generated.bankAccess.rd_bank_1_id := random(18, 15) + generated.bankAccess.wr_bank_id := random(22, 19) + source.io.enq.valid := cycle < 5000.U && random(0) + source.io.enq.bits := generated + dut.io.alloc <> source.io.deq + reference.io.alloc.valid := dut.io.alloc.valid + reference.io.alloc.bits := dut.io.alloc.bits + + val completions = Module(new Queue(UInt(log2Ceil(b.frontend.rob_entries).W), 16)) + val active = cycle(9, 6) === 13.U + val ready = completions.io.enq.ready && random(7) && cycle(8, 5) =/= 7.U + dut.io.issue.ready := ready + reference.io.issue.ready := ready + completions.io.enq.valid := dut.io.issue.fire + completions.io.enq.bits := dut.io.issue.bits.rob_id + dut.io.complete.valid := completions.io.deq.valid && random(4) + dut.io.complete.bits := completions.io.deq.bits + reference.io.complete.valid := dut.io.complete.valid + reference.io.complete.bits := dut.io.complete.bits + completions.io.deq.ready := dut.io.complete.ready && random(4) + dut.io.hart_id := 0.U + reference.io.hart_id := 0.U + dut.io.subRobActive := active + reference.io.subRobActive := active + + assert(dut.io.alloc.ready === reference.io.alloc.ready, "ROB allocation timing mismatch") + assert(dut.io.complete.ready === reference.io.complete.ready, "ROB completion timing mismatch") + assert(dut.io.issue.valid === reference.io.issue.valid, "ROB issue timing mismatch") + when(dut.io.issue.valid) { + assert(dut.io.issue.bits.asUInt === reference.io.issue.bits.asUInt, "ROB issue payload mismatch") + } + assert(dut.io.empty === reference.io.empty && dut.io.full === reference.io.full) + assert(dut.io.head_ptr === reference.io.head_ptr) + assert(dut.io.issued_count === reference.io.issued_count) + assert(dut.io.entry_valid.asUInt === reference.io.entry_valid.asUInt) + assert(dut.io.entry_complete.asUInt === reference.io.entry_complete.asUInt) + assert(dut.io.inst_ids.asUInt === reference.io.inst_ids.asUInt) + + val allocated = RegInit(0.U(16.W)) + val issued = RegInit(0.U(16.W)) + val completed = RegInit(0.U(16.W)) + val sawFull = RegInit(false.B) + val sawStall = RegInit(false.B) + val expected = Reg(Vec(b.frontend.rob_entries, chiselTypeOf(generated.cmd))) + val allocationSlot = RegInit(0.U(log2Ceil(b.frontend.rob_entries).W)) + when(dut.io.alloc.fire) { + allocated := allocated + 1.U + expected(allocationSlot) := dut.io.alloc.bits.cmd + allocationSlot := Mux(allocationSlot === (b.frontend.rob_entries - 1).U, + 0.U, allocationSlot + 1.U) + } + when(dut.io.issue.fire) { + issued := issued + 1.U + assert(dut.io.issue.bits.cmd.cmd.asUInt === expected(dut.io.issue.bits.rob_id).asUInt, + "ROB changed accepted command operands") + } + when(dut.io.complete.fire) { completed := completed + 1.U } + when(dut.io.full) { sawFull := true.B } + when(dut.io.issue.valid && !ready) { sawStall := true.B } + passed := cycle > 5005.U && !source.io.deq.valid && dut.io.empty && !completions.io.deq.valid + when(passed) { + assert(allocated === issued && issued === completed && allocated > 64.U) + assert(sawFull && sawStall, "Missing ROB full/stall coverage") + } +} + +object EmitGlobalRobCheck extends App { + ChiselStage.emitSystemVerilogFile(new GlobalRobCheck, + Array("--target-dir", args.headOption.getOrElse("build/globalrob-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/tests/tb_globalrob.sv b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/tests/tb_globalrob.sv new file mode 100644 index 0000000..8213b7d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/sources/tests/tb_globalrob.sv @@ -0,0 +1,29 @@ +`timescale 1ns/1ps +module tb; + reg clock = 0, reset = 1; + reg [31:0] seed = 32'h12345678; + wire passed; + integer cycles = 0; + GlobalRobCheck dut(.*); + always #5 clock = ~clock; + initial begin + repeat (5) @(negedge clock); + reset = 0; + repeat (1200) @(negedge clock); + reset = 1; seed = 32'hda7a0319; + repeat (5) @(negedge clock); + reset = 0; + repeat (1800) @(negedge clock); + reset = 1; seed = 32'habcdef01; + repeat (5) @(negedge clock); + reset = 0; + end + always @(posedge clock) begin + cycles <= cycles + 1; + if (!reset && passed) begin + $display("PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=%0d", cycles); + $finish; + end + if (cycles > 15000) $fatal(1, "GlobalROB test timeout"); + end +endmodule diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/BOARD_REGRESSION.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/BOARD_REGRESSION.json new file mode 100644 index 0000000..79e2fd2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/BOARD_REGRESSION.json @@ -0,0 +1,41 @@ +{ + "result": "PASS", + "tests": { + "cpu": { + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 + }, + "gemmini": { + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 + }, + "loop": { + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 + }, + "dma": { + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 + } + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/board-unit/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/board-unit/RESULT.json new file mode 100644 index 0000000..62b7f31 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/board-unit/RESULT.json @@ -0,0 +1,18 @@ +{ + "result": "PASS", + "tests": 3, + "physical_mig_simulated": false, + "sources": { + "board/loader_axi.sv": "05609b0870054ea675aedb406f6215cd456f18db6d6428b461cbae03d9a662f4", + "board/flash_spi_byte.sv": "4d1fac5238f31fb3a69a58d1aca9ccec722e833d788113b94d86c6a1b861045a", + "board/uart_rx.sv": "0b35263884577324f146ff7fd516e5b561dcc8787e0d8ad599669bac1958406d", + "board/toy_a7_top.sv": "c8af97f543b8ae5d6dc21a85ba13b16a28fe3ba5bf93f8051c9e38c99f3350bd", + "board/ddr_uart_loader.sv": "980f4cd2e3fa2a00b66143f879bc749ed952c2c1e54331460821bac0300c43d6", + "board/axi_scu.sv": "ee77bf641d61811b4c1faea845752850c22461a63b4cdfd3d6f9cd223e6c2fc2", + "board/toy_a7_platform.sv": "01fe1f8e2621a1a023ac3b8d91758868b190760f6e706ae1d34a67857b96d846", + "board/axi_fullwidth.sv": "bf07ae27724dbd0a361d732dfb57109f06beef207c47a066d400cb06d7f07d5a", + "board/uart_tx.sv": "c20d420fc20be4f6313bdde5abc45ef0b9f8e93bf75350dd9951bc8868b3b65c", + "tests/tb_axi_fullwidth.sv": "1d3964fab0eaa76a6f864f07a7dedf01639ba12a9400a15d0839e707ab73c4ed", + "tests/tb_axi_scu.sv": "5dfd1d6cac3201f0e5188e9b73e60ade27c4551570d4b00d387301713d9fbe97" + } +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/RESULT.json new file mode 100644 index 0000000..8849267 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "cpu", + "binary_sha256": "3bbf33f7bf2b6bb0f3888ab4a649a11272de3f74458f6ea36b266f9670df75f5", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 709434 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/compile.log new file mode 100644 index 0000000..bb2cd6d --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_cpu.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.457 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 13.059 s (elab=0.532, cvt=3.209, bld=8.739); cpu 4.565 s on 8 threads; allocated 565.285 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/simulation.log new file mode 100644 index 0000000..a0088f8 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/cpu/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=709434 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.829 s; speed 1.217 ms/s +- Verilator: cpu 5.826 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/RESULT.json new file mode 100644 index 0000000..7f02844 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "dma", + "binary_sha256": "082965476d4dcc98cc556b8f79fa2fdf659cea501665e207d04349d40469e9d2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 1914839 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/compile.log new file mode 100644 index 0000000..f2a9394 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_cpu.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.457 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 12.005 s (elab=0.530, cvt=3.142, bld=7.760); cpu 4.491 s on 8 threads; allocated 565.293 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/simulation.log new file mode 100644 index 0000000..283d53c --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/dma/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=1914839 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 14.201 s; speed 1.348 ms/s +- Verilator: cpu 14.194 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/RESULT.json new file mode 100644 index 0000000..e935317 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "gemmini", + "binary_sha256": "d6307d194aadb9f23e14edf695ce98ab1ea361881237576b15c251573af2826e", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 251063 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/compile.log new file mode 100644 index 0000000..03aa70f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_cpu.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.457 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 12.918 s (elab=0.578, cvt=3.278, bld=8.383); cpu 4.816 s on 8 threads; allocated 565.293 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/simulation.log new file mode 100644 index 0000000..63777f4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/gemmini/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=251063 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 3ms; walltime 2.245 s; speed 1.118 ms/s +- Verilator: cpu 2.243 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/RESULT.json new file mode 100644 index 0000000..b5daff2 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/RESULT.json @@ -0,0 +1,15 @@ +{ + "result": "PASS", + "cycle_equivalence": true, + "coverage": [ + "accepted operand integrity", + "ROB full", + "pointer wrap", + "issue backpressure", + "SubROB ownership stall", + "mid-flight resets", + "concurrent allocation/issue/completion", + "complete drain" + ], + "rtl_sha256": "e44723e3396d7e6421b9fae96a5d7b0b12ad0b4d55cc15128f21d7e048296fd0" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/compile.log new file mode 100644 index 0000000..3e1cfff --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/compile.log @@ -0,0 +1,93 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:22:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 22 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:1346:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1346 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:1722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1722 | module robOperands_16x128( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:1747:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1747 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:6809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6809 | module GlobalROB_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:11849:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11849 | module ram_2x303( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:11868:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11868 | module Queue2_PostGDCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:11988:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11988 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:12007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12007 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:12055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12055 | module GlobalRobCheck( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/GlobalRobCheck.sim.sv:13609:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13609 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:2:8: ... Location of module with timescale + 2 | module tb; + | ^~ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb__pch.h -o Vtb__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb_BankAliasTable__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb_BankAliasTable__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.fast -c Vtb__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb_BankAliasTable__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb_BankAliasTable__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb__pch.h.slow -c Vtb__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb__ALL.a -pthread -lpthread -latomic -o Vtb +rm Vtb__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/globalrob-check/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 1.310 MB sources in 13 modules, into 4.921 MB in 13 C++ files needing 0.004 MB +- Verilator: Walltime 23.503 s (elab=0.058, cvt=0.446, bld=21.284); cpu 7.107 s on 4 threads; allocated 389.180 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/elaboration.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/elaboration.log new file mode 100644 index 0000000..9cf0f3f --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/elaboration.log @@ -0,0 +1,90 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/) +[info] compiling 213 Scala sources to /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/target/scala-2.13/classes ... +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala:38:43: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method apply, +[warn] or remove the empty argument list from its definition (Java-defined methods are exempt). +[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function. [quickfixable] +[warn] val attributes = IO(Output(Property[Seq[AnyClassType]])) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/T1DecodePattern.scala:40:42: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method apply, +[warn] or remove the empty argument list from its definition (Java-defined methods are exempt). +[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function. [quickfixable] +[warn] val attributesIn = IO(Input(Property[Seq[AnyClassType]])) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:22:16: implicit conversion method bool2str should be enabled +[warn] by making the implicit value scala.language.implicitConversions visible. +[warn] This can be achieved by adding the import clause 'import scala.language.implicitConversions' +[warn] or by setting the compiler option -language:implicitConversions. +[warn] See the Scaladoc for value scala.language.implicitConversions for a discussion +[warn] why the feature should be explicitly enabled. +[warn] implicit def bool2str(b: Boolean): String = if (b) "b1" else "b0" +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:72:24: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:73:24: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = 16, dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:74:27: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:75:25: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:76:23: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt(50000000))) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:78:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:116:5: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:135:17: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val cache = up(InclusiveCacheKey, site) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:138:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/src/main/scala/ToyLinuxConfig.scala:171:37: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site).map { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:30:49: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys).lazyZip(zs) +[warn] (stalling.init, stalling.tail, valids.init).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:41:34: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys) +[warn] (valids.init, stalling.tail).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/builtin/pipeline/Pipeline.scala:51:32: method zipped in class Ops is deprecated (since 2.13.0): Use xs.lazyZip(ys) +[warn] (valids.tail, valids.init).zipped.foreach { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:13:35: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] implicit class CrossAble[X](xs: Traversable[X]) { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:15:22: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] def cross[Y](ys: Traversable[Y]): Traversable[(X, Y)] = for { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/gpdomain/sequencer/decoder/TableGenerator.scala:15:39: type Traversable in package scala is deprecated (since 2.13.0): Use Iterable instead of Traversable +[warn] def cross[Y](ys: Traversable[Y]): Traversable[(X, Y)] = for { +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:175:85: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:183:85: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters +[warn] if (bbPerCore(i).isDefined) Some(TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters( +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/BBTile.scala:305:3: method DisableMonitors in package diplomacy is deprecated (since rocketchip 2.0.0): Diplomacy has been split to a standalone library +[warn] DisableMonitors(implicit p => tlSlaveXbar.node :*= slaveNode) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/Configs.scala:59:40: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val prev = up(TilesLocated(`location`), site) +[warn] ^ +[warn] /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/upstream/arch/src/main/scala/framework/system/tile/Configs.scala:110:40: method apply in class View is deprecated (since CDE 0.1): up(XYZ, site) is no longer necessary; remove the superfluous site argument +[warn] val prev = up(TilesLocated(`location`), site) +[warn] ^ +[warn] 24 warnings found +[info] done compiling +[info] running fpga.arty.linux.EmitGlobalRobCheck +[success] Total time: 36 s, completed Oct 12, 2026, 7:47:43 PM diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/simulation.log new file mode 100644 index 0000000..c00fe2b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/globalrob/simulation.log @@ -0,0 +1,5 @@ +PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=8029 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_globalrob.sv:25: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 80us; walltime 0.027 s; speed 2.990 ms/s +- Verilator: cpu 0.027 s on 1 threads; allocated 7 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/RESULT.json new file mode 100644 index 0000000..962fe2b --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/RESULT.json @@ -0,0 +1,17 @@ +{ + "result": "PASS_RTL_LINUX_USERSPACE", + "payload_sha256": "eb2ee34cc1a744498ac63b4e3fae425d4bb06be422ae6d41bd1ead696201134f", + "checks": [ + "OpenSBI", + "Linux version", + "PASS VM_COPY_ON_WRITE", + "PASS VM_PAGE_PROTECTION", + "PASS FP64_PROCESS_CONTEXT", + "PASS LINUX_TIMER", + "PASS LINUX_SYSTEM_CHECK", + "PASS BOARD_LINUX_USERSPACE" + ], + "physical_mig_simulated": false, + "physical_board_tested": false, + "uart_rx_command_tested": true +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/compile.log new file mode 100644 index 0000000..4e5a7b6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:2:8: ... Location of module with timescale + 2 | module tb_board_linux; + | ^~~~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_linux.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_linux.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_linux.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_linux.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_linux.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_linux__pch.h -o Vtb_board_linux__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_linux__pch.h -o Vtb_board_linux__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.fast -c Vtb_board_linux__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_linux__pch.h.slow -c Vtb_board_linux__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_linux__ALL.a -pthread -lpthread -latomic -o Vtb_board_linux +rm Vtb_board_linux__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.473 MB sources in 354 modules, into 26.897 MB in 19 C++ files needing 0.021 MB +- Verilator: Walltime 17.141 s (elab=0.576, cvt=3.206, bld=12.637); cpu 4.819 s on 8 threads; allocated 438.188 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/simulation.log new file mode 100644 index 0000000..fdcc27e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/linux-final/simulation.log @@ -0,0 +1,172 @@ + +OpenSBI v1.9 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Buckyball +Platform Features : medeleg +Platform HART Count : 1 +Platform HART Protection : pmp +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 500000Hz +Platform Console Device : buckyball-scu +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : buckyball-scu-reset +Platform Shutdown Device : buckyball-scu-reset +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 312 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 56 KB +Firmware Heap Offset : 0x45000 +Firmware Heap Size : 36 KB (total), 0 KB (reserved), 12 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 496 B (used), 3600 B (free) +Runtime SBI Version : 3.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,srst,pmu,dbcn,fwft,legacy,sse +Experimental SBI Extensions : none + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0x0* +Domain0 Region00 : 0x0000000080040000-0x000000008004ffff M: (F,R,W) S/U: () +Domain0 Region01 : 0x0000000080000000-0x000000008003ffff M: (F,R,X) S/U: () +Domain0 Region02 : 0x0000000002008000-0x000000000200bfff M: (I,R,W) S/U: () +Domain0 Region03 : 0x0000000002000000-0x0000000002007fff M: (I,R,W) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000088000000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imafdcx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 30 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +Linux version 6.6.0 (yys@amax) (riscv64-unknown-linux-gnu-gcc (GCC) 15.3.0, GNU ld (GNU Binutils) 2.46) #1 Sat Oct 10 16:24:07 CST 2026 +Machine model: ucb-bar,buckyball +Forcing kernel command line to: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +SBI specification v3.0 detected +SBI implementation ID=0x1 Version=0x10009 +SBI TIME extension detected +SBI IPI extension detected +SBI RFENCE extension detected +SBI SRST extension detected +earlycon: sbi0 at I/O port 0x0 (options '') +printk: bootconsole [sbi0] enabled +printk: debug: ignoring loglevel setting. +Memory limited to 256MB +efi: UEFI not found. +OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +OF: reserved mem: 0x0000000080040000..0x000000008004ffff (64 KiB) nomap non-reusable mmode_resv0@80040000 +Zone ranges: + DMA32 [mem 0x0000000080000000-0x000000008fffffff] + Normal empty +Movable zone start for each node +Early memory node ranges + node 0: [mem 0x0000000080000000-0x000000008004ffff] + node 0: [mem 0x0000000080050000-0x000000008fffffff] +Initmem setup node 0 [mem 0x0000000080000000-0x000000008fffffff] +Falling back to deprecated "riscv,isa" +riscv: base ISA extensions abcdfim +riscv: ELF capabilities acdfim +pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 +pcpu-alloc: [0] 0 +Kernel command line: console=hvc0 earlycon=sbi loglevel=8 ignore_loglevel panic=1 mem=256M +Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +Built 1 zonelists, mobility grouping on. Total pages: 64640 +mem auto-init: stack:all(zero), heap alloc:off, heap free:off +Memory: 241400K/262144K available (2126K kernel code, 4423K rwdata, 2048K rodata, 4385K init, 299K bss, 20744K reserved, 0K cma-reserved) +SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +riscv-intc: 64 local interrupts mapped +plic: interrupt-controller@c000000: mapped 1 interrupts with 1 handlers for 2 contexts. +clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 7052723233920 ns +sched_clock: 64 bits at 500kHz, resolution 2000ns, wraps every 4398046511000ns +Console: colour dummy device 80x25 +printk: console [hvc0] enabled +printk: console [hvc0] enabled +printk: bootconsole [sbi0] disabled +printk: bootconsole [sbi0] disabled +Calibrating delay loop (skipped), value calculated using timer frequency.. 1.00 BogoMIPS (lpj=2000) +pid_max: default: 32768 minimum: 301 +Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +riscv: ELF compat mode unsupported +ASID allocator disabled (0 bits) +EFI services will not be available. +devtmpfs: initialized +clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +futex hash table entries: 256 (order: 0, 6144 bytes, linear) +DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +clocksource: Switched to clocksource riscv_clocksource +workingset: timestamp_bits=62 max_order=16 bucket_order=0 +io scheduler mq-deadline registered +io scheduler kyber registered +clk: Disabling unused clocks +Freeing unused kernel image (initmem) memory: 4384K +Run /init as init process + with arguments: + /init + with environment: + HOME=/ + TERM=linux + + __ __ __ ____ + / / / /___ __ _____ ____ _ / /_ ____ _/ / / + / /_/ / __ `/ | / / _ \ / __ `/ / __ \/ __ `/ / / + / __ / /_/ /| |/ / __/ / /_/ / / /_/ / /_/ / / / + /_/ /_/\__,_/ |___/\___/ \__,_/ /_.___/\__,_/_/_/ + +/bin/sh: can't access tty; job control turned off +~ # +SIM_SHELL_PROMPT cycles=241934865 +/root/linux_system_check-linux +SIM_COMMAND_SENT cycles=249692645 overflow=0 framing=0 pending_rx=1 + +BEGIN LINUX_SYSTEM_CHECK +PASS VM_COPY_ON_WRITE +linux_system_ch[25]: unhandled signal 11 code 0x2 at 0x0000003f82c1a000 in linux_system_check-linux[10000+7a000] +CPU: 0 PID: 25 Comm: linux_system_ch Not tainted 6.6.0 #1 +Hardware name: ucb-bar,buckyball (DT) +epc : 00000000000105c6 ra : 000000000001041e sp : 0000003fe9ca4b50 + gp : 0000000000090078 tp : 0000000000096760 t0 : 0000000000000000 + t1 : 0000000000000000 t2 : 0000000000000000 s0 : 0000003fe9ca4bd0 + s1 : 0000003f82c19000 a0 : 0000000000000000 a1 : 0000000000000000 + a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 + a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000000000 + s2 : 0000000000000042 s3 : 0000000000001000 s4 : 0000003f82c1a000 + s5 : 0000003fe9ca4d88 s6 : 0000000000000002 s7 : 00000000000106ba + s8 : 00000000000101e0 s9 : 000000000000003a s10: 0000000000094e28 + s11: 0000000000000000 t3 : 0000000000000000 t4 : 0000000000000000 + t5 : 0000000000000000 t6 : 0000000000000000 +status: 800000020001e020 badaddr: 0000003f82c1a000 cause: 000000000000000d +PASS VM_PAGE_PROTECTION +PASS FP64_PROCESS_CONTEXT +PASS LINUX_TIMER elapsed_ns=101252000 +PASS LINUX_SYSTEM_CHECK +PASS BOARD_LINUX_USERSPACE cycles=273506752 characters=7992 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-linux-final/tb_board_linux.sv:99: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 11s; walltime 2078.418 s; speed 5.264 ms/s +- Verilator: cpu 2077.865 s on 1 threads; allocated 264 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/RESULT.json b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/RESULT.json new file mode 100644 index 0000000..c426992 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/RESULT.json @@ -0,0 +1,9 @@ +{ + "result": "PASS", + "test": "loop", + "binary_sha256": "bbe9646dc565ac9ac1188c6b3d53d24b1b37985ee158ee2ac918df04c3267ce2", + "original_cpu_oracle": true, + "ddr_phy_simulated": false, + "physical_linux_boot_tested": false, + "cycles": 684219 +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/compile.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/compile.log new file mode 100644 index 0000000..ebbfa19 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/compile.log @@ -0,0 +1,2197 @@ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 31 | module NonSyncResetSynchronizerPrimitiveShiftReg_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=5.050 + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 48 | module SynchronizerShiftReg_w1_d3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:61:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 61 | module IntSyncAsyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:74:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 74 | module AsyncResetRegVec_w1_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 103 | module IntSyncCrossingSource_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:118:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 118 | module FixedClockBroadcast_3( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:139:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 139 | module TLMonitor( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:987:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 987 | module TLMonitor_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:2434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 2434 | module TLXbar_sbus_i2_o3_a32d128s3k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:3195:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3195 | module TLMonitor_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4151 | module Repeater_TLBundleA_a28d128s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4218 | module TLWidthWidget16( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4386 | module TLInterconnectCoupler_sbus_to_bus_named_cbus( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4478:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4478 | module ram_2x58( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4497:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4497 | module Queue2_AXI4BundleAW( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4581:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4581 | module ram_2x73( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4600:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4600 | module Queue2_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4657:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4657 | module ram_2x4( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4676:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4676 | module Queue2_AXI4BundleB( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4729:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4729 | module Queue2_AXI4BundleAR( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4813:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4813 | module ram_2x69( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4832:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4832 | module Queue2_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:4891:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 4891 | module AXI4Buffer( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5067:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5067 | module ram_2x8( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5086:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5086 | module Queue2_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5143:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5143 | module Queue1_BundleMap( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5178 | module AXI4UserYanker( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5540:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5540 | module ram_8x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5559:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5559 | module Queue8_AXI4BundleR( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:5631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 5631 | module AXI4Deinterleaver( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6073 | module AXI4IdIndexer( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:6219:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 6219 | module TLMonitor_3( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7048:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7048 | module Queue1_AXI4BundleW( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7082:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7082 | module Queue1_AXI4BundleARW( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7148:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7148 | module TLToAXI4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:7529:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 7529 | module TLMonitor_4( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8396:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8396 | module Repeater_TLBundleA_a31d128s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8463 | module TLWidthWidget16_2( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:8623:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 8623 | module TLInterconnectCoupler_sbus_to_port_named_mmio_port_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:9400:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 9400 | module SystemBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10050 | module FixedClockBroadcast_4( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10073:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10073 | module TLMonitor_5( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:10975:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +10975 | module TLXbar_cbus_out_i1_o4_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:11288:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +11288 | module TLMonitor_6( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12202:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12202 | module ram_2x114( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12221 | module Queue2_TLBundleA_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12301 | module ram_2x79( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12320:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12320 | module Queue2_TLBundleD_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12399:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12399 | module TLBuffer_a28d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:12534:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +12534 | module TLMonitor_7( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13449 | module TLAtomicAutomata_cbus( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:13973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +13973 | module TLMonitor_8( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14799 | module Queue1_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14846:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14846 | module TLError( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:14953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +14953 | module TLMonitor_9( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15857 | module ram_2x100( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15876:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15876 | module Queue2_TLBundleA_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:15955:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +15955 | module Queue2_TLBundleD_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16028 | module TLBuffer_a14d64s3k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16155 | module ErrorDeviceWrapper( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:16258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +16258 | module TLMonitor_10( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17017:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17017 | module Repeater_TLBundleA_a26d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17081:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17081 | module TLFragmenter_CLINT( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17261:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17261 | module TLInterconnectCoupler_cbus_to_clint( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:17336:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +17336 | module TLMonitor_11( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18106:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18106 | module Repeater_TLBundleA_a28d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18170:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18170 | module TLFragmenter_PLIC( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18350 | module TLInterconnectCoupler_cbus_to_plic( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:18425:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +18425 | module TLMonitor_12( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19040 | module Repeater_TLBundleA_a17d64s3k1z3u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19104:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19104 | module TLFragmenter_bootrom( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19263:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19263 | module TLInterconnectCoupler_cbus_to_bootrom( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19330:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19330 | module PeripheryBus_cbus( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:19882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +19882 | module TLMonitor_13( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20610:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20610 | module ProbePicker( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20688:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20688 | module ram_2x10( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20707:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20707 | module Queue2_BundleMap_6( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:20764:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +20764 | module AXI4UserYanker_1( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21713:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21713 | module AXI4IdIndexer_1( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:21859:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +21859 | module TLMonitor_14( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22587:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22587 | module Queue1_AXI4BundleW_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22621 | module Queue1_AXI4BundleARW_1( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:22687:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +22687 | module TLToAXI4_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:23555:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +23555 | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24031:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24031 | module MemoryBus( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:24349:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +24349 | module TLMonitor_15( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25732:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25732 | module BroadcastFilter( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25756:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25756 | module ram_4x144( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25775:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25775 | module Queue4_TLBroadcastData( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25828:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25828 | module TLBroadcastTracker( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:25964:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +25964 | module TLBroadcastTracker_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26100:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26100 | module TLBroadcast( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:26686:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +26686 | module TLMonitor_16( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27414 | module BankBinder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27491:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27491 | module CoherenceManagerWrapper( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:27669:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +27669 | module TLMonitor_17( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29229:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29229 | module TLMonitor_18( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29635:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29635 | module TLXbar_MasterXbar_BBTile_i2_o1_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29898 | module IntXbar_i4_o1( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:29918:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +29918 | module WritebackUnit( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30014:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30014 | module ProbeUnit( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30154:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30154 | module Arbiter1_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30168:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30168 | module Arbiter1_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30191 | module Arbiter1_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30214 | module Arbiter1_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30249:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30249 | module Arbiter1_Bool( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30258:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30258 | module ram_16x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30277:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30277 | module Queue16_ReplayInternal( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30360:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30360 | module Queue1_TLBundleE_a32d128s1k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30388:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30388 | module MSHR( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30835:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30835 | module Arbiter1_HellaCacheResp( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:30879:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +30879 | module IOMSHR( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31790:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31790 | module sdq_17x64( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:31809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +31809 | module MSHRFile( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32350:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32350 | module OptimizationBarrier_TLBEntryData( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32406:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32406 | module PMPChecker_s3( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32691:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32691 | module PMAChecker( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:32731:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +32731 | module DTLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35923:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35923 | module L1MetadataArray( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:35990:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +35990 | module Arbiter5_L1MetaReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36023:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36023 | module Arbiter2_L1MetaWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36055 | module DataArray( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36151:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36151 | module Arbiter4_L1DataReadReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36180:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36180 | module Arbiter2_L1DataWriteReq( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36206:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36206 | module AMOALU( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36248:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36248 | module MaxPeriodFibonacciLFSR( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36342:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36342 | module Arbiter2_WritebackReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:36377:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +36377 | module NonBlockingDCache( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37660:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37660 | module ICache( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:37914:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +37914 | module ShiftQueue( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38054:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38054 | module PMPChecker_s2( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:38215:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +38215 | module ITLB( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41129:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41129 | module Frontend( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:41494:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +41494 | module TLMonitor_19( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:42301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +42301 | module TLMonitor_20( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43108:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43108 | module TLXbar_i2_o1_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43343 | module TLMonitor_21( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43851:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43851 | module ram_2x116( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43870:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43870 | module Queue2_TLBundleA_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43947:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43947 | module ram_2x77( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:43966:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +43966 | module Queue2_TLBundleD_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44045:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44045 | module TLBuffer_a32d64s1k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44158:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44158 | module TLMonitor_22( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44783 | module TLBuffer_a32d64s1k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:44892:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +44892 | module TLMonitor_23( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45699:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45699 | module Repeater_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:45766:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +45766 | module TLWidthWidget8_4( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46074:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46074 | module TLMonitor_24( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46882:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46882 | module ram_2x117( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46901:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46901 | module Queue2_TLBundleA_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:46981:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +46981 | module ram_2x78( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47000:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47000 | module Queue2_TLBundleD_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47079:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47079 | module TLBuffer_a32d64s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47214:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47214 | module HellaCacheArbiter( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47381 | module Arbiter3_Valid_PTWReq( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47419:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47419 | module OptimizationBarrier_UInt( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47427 | module OptimizationBarrier_PTE( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:47459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +47459 | module PTW( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:48434:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +48434 | module FPUDecoder( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49794:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49794 | module CompareRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49824:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49824 | module RecFNToIN_e11_s53_i64( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49873:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49873 | module RecFNToIN_e11_s53_i32( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:49912:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +49912 | module FPToInt( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50375:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50375 | module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50410:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50410 | module PipelinedINToRecFN( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50513:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50513 | module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50539 | module PipelinedINToRecFN_1( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50614 | module RoundAnyRawFNToRecFN_ie7_is64_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50642:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50642 | module PipelinedINToRecFN_2( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:50717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +50717 | module IntToFP( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51072:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51072 | module RoundAnyRawFNToRecFN_ie11_is53_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51199:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51199 | module RecFNToRecFN( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51221:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51221 | module RoundAnyRawFNToRecFN_ie11_is53_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51321:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51321 | module RecFNToRecFN_1( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51343:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51343 | module FPToFP( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51469:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51469 | module MulAddRecFNToRaw_preMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51569 | module MulAddRecFNToRaw_postMul_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51822:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51822 | module RoundAnyRawFNToRecFN_ie11_is55_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:51953:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +51953 | module RoundAnyRawFNToRecFN_ie11_is55_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52060:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52060 | module RoundAnyRawFNToRecFN_ie11_is55_oe11_os53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52194:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52194 | module SharedMulAddRecFNPipe( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52551:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52551 | module FPUSharedFMAPipe( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52682:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52682 | module DivSqrtRawFN_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52852:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52852 | module DivSqrtRecFMToRaw_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:52907:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +52907 | module RoundAnyRawFNToRecFN_ie5_is13_oe5_os11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53039:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53039 | module RoundRawFNToRecFN_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53068:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53068 | module DivSqrtRecFM_small_e5_s11( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53128:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53128 | module DivSqrtRawFN_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53297:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53297 | module DivSqrtRecFMToRaw_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53352:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53352 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53456:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53456 | module RoundRawFNToRecFN_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53485:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53485 | module DivSqrtRecFM_small_e8_s24( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53545:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53545 | module DivSqrtRawFN_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53715:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53715 | module DivSqrtRecFMToRaw_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53770:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53770 | module RoundRawFNToRecFN_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53799:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53799 | module DivSqrtRecFM_small_e11_s53( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53860:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53860 | module regfile_32x65( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:53905:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +53905 | module FPU( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:54820:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +54820 | module RVCExpander( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55183:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55183 | module IBuf( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:55307:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +55307 | module CSRFile( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57223 | module RocketALU( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:57809:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +57809 | module MulDiv( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58107 | module Arbiter3_LLWB( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58125:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58125 | module rf_31x64( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:58149:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +58149 | module RocketBB( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62838:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62838 | module GlobalDecoder( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:62928:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +62928 | module BankAliasTable( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64252:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64252 | module BankScoreboard( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:64627:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +64627 | module GlobalROB( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68674:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68674 | module Arbiter3_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68717:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68717 | module ram_16x4( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68736:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68736 | module Queue16_UInt4( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:68782:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +68782 | module SubROB( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69357:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69357 | module Arbiter1_SubRobRow( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:69722:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +69722 | module GlobalScheduler( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:70973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +70973 | module BootRom( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71013:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71013 | module Frontend_1( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71637 | module PE( + | ^~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:71656:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +71656 | module AlwaysOutTransposer( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72411:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72411 | module MacUnit( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72426:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72426 | module PE_64( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72524:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72524 | module Tile( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:72571:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +72571 | module Mesh( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76050:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76050 | module TagQueue( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76191:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76191 | module ram_6x7( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76210:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76210 | module Queue6_TagWithIdAndTotalRows( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:76271:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +76271 | module MeshWithDelays( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77318:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77318 | module ram_data_8x64( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77337 | module Queue8_SramReadResp( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:77385:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +77385 | module GemminiExCtrl( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79354:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79354 | module LoopMatmulUnroller( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79637:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79637 | module LoopConvAddrGen( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:79690:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +79690 | module LoopConvUnroller( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80113:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80113 | module LoopCmdEncoder( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80402:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80402 | module Arbiter2_LoopCmd( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:80598:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +80598 | module GemminiBall( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81783:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81783 | module RRArbiter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81857:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81857 | module CmdRouter( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:81985:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +81985 | module BallCyclePMC( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82095:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82095 | module BBus( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:82898:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +82898 | module BallDomainDecoder( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83028:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83028 | module ram_4x281( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83047:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83047 | module Queue4_BallReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83178:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83178 | module Arbiter1_BallRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83198:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83198 | module BallReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:83328:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +83328 | module BallDomain( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84141:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84141 | module MemDomainDecoder( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84300:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84300 | module ram_4x158( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84319:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84319 | module Queue4_MemReservationStation_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84421:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84421 | module Arbiter3_MemRsComplete( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84463:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84463 | module MemReservationStation( + | ^~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84631:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84631 | module MemLoader( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:84869:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +84869 | module MemStorer( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85122:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85122 | module MemCyclePMC( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85241:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85241 | module TLB( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85621 | module RRArbiter_1( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85649:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85649 | module BBTLBCluster( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:85777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +85777 | module StreamReader( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86142:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86142 | module StreamWriter( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86223:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86223 | module ZeroLineGenerator( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86264:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86264 | module MemConfiger( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86433:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86433 | module RRArbiter_2( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86465:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86465 | module MemGroupQueryArbiter( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:86543:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +86543 | module MemFrontend( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87160 | module MemMidend( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87621:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87621 | module SramBank( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87672:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87672 | module AccPipe( + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:87781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +87781 | module PrivateMemBackend( + | ^~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:90777:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +90777 | module MemBackend( + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91055:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91055 | module MemDomain( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:91973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +91973 | module Queue1_GlobalSchedComplete( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92008:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92008 | module GpDomain( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92040:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92040 | module ram_8x21( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92059 | module Queue8_BuckyballAccelerator_Anon( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:92123:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +92123 | module BuckyballAccelerator( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93569 | module Queue3_UInt2( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93614:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93614 | module SimpleHellaCacheIFReplayQueue( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93667:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93667 | module Arbiter2_HellaCacheReq( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93678:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93678 | module SimpleHellaCacheIF( + | ^~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93768:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93768 | module BarrierUnit( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:93785:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +93785 | module BBTile( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:95579:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +95579 | module TLMonitor_25( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:96427:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +96427 | module TLMonitor_26( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98184:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98184 | module ram_2x189( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98203:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98203 | module Queue2_TLBundleA_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98283:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98283 | module ram_2x142( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98302:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98302 | module Queue2_TLBundleD_a32d128s2k1z4u( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98381:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98381 | module Queue2_TLBundleA_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98459:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98459 | module Queue2_TLBundleD_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98539:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98539 | module ram_2x60( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98558:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98558 | module Queue2_TLBundleB_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98622:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98622 | module ram_2x173( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98641:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98641 | module Queue2_TLBundleC_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98716:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98716 | module ram_sink_2x1( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98735:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98735 | module Queue2_TLBundleE_a32d128s2k1z4c( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:98781:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +98781 | module TLBuffer_a32d128s2k1z4u_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99162:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99162 | module IntSyncSyncCrossingSink_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99173:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99173 | module IntSyncSyncCrossingSink_n1x1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99181:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99181 | module TilePRCIDomain( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99589:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99589 | module BundleBridgeNexus_UInt1_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:99597:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +99597 | module TLMonitor_27( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100216:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100216 | module CLINT( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100337:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100337 | module AsyncResetRegVec_w2_i0( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100366:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100366 | module IntSyncCrossingSource_n1x2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100386:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100386 | module CLINTClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:100449:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +100449 | module TLMonitor_28( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101080:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101080 | module LevelGateway( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101099:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101099 | module PLICFanIn( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101111:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101111 | module Queue1_RegMapperInput_i23_m8( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101160:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101160 | module TLPLIC( + | ^~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101389:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101389 | module PLICClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101452:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101452 | module TLMonitor_29( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:101973:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +101973 | module TLROM( + | ^~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102530:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102530 | module bootromClockSinkDomain( + | ^~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:102569:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +102569 | module ToyLinuxSystem( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103817:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103817 | module ToyLinuxChip( + | ^~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:103984:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +103984 | module tag_array( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104007:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104007 | module array_0_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104034:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104034 | module array_0_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104059:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104059 | module array_2_0( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104084:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104084 | module array_2_1( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104109:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104109 | module bbtile_icache_tag_array( + | ^~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104132:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104132 | module bbtile_icache_data_arrays_0( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104155:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104155 | module bbtile_icache_data_arrays_1( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104176:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104176 | module bbtile_icache_data_arrays_2( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104197:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104197 | module bbtile_icache_data_arrays_3( + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104218:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104218 | module robOperands( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104243:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104243 | module sram( + | ^~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104268:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104268 | module mem( + | ^~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104301:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104301 | module plusarg_reader #( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104326:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104326 | module ITraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104404:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104404 | module FpgaDspMac(input [7:0] a, b, input [19:0] c, output [19:0] y); + | ^~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104414:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104414 | module PMCTraceDPI( + | ^~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104464:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104464 | module MemPMCTraceDPI( + | ^~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/ToyLinuxChip.sv:104514:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) +104514 | module MTraceDPI( + | ^~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 1 | module tag_array_ext( input [4:0] RW0_addr, + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:19:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 19 | module array_0_0_ext( + | ^~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:37:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 37 | module bbtile_icache_tag_array_ext( input [5:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:55:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 55 | module bbtile_icache_data_arrays_0_ext( input [7:0] RW0_addr, + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:73:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 73 | module robOperands_ext( + | ^~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:90:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 90 | module sram_ext( + | ^~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/serial-bound/FpgaMemories.sv:107:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 107 | module mem_ext( input [9:0] RW0_addr, + | ^~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-TIMESCALEMOD: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3) + 3 | module axi_smoke_memory #( + | ^~~~~~~~~~~~~~~~ + /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:2:8: ... Location of module with timescale + 2 | module tb_board_cpu; + | ^~~~~~~~~~~~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:27:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 27 | count <= DIVISOR - 1; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=5.050 + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_tx.sv:32:13: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.transmitter' + 32 | count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:23:55: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 23 | IDLE: if (!rx_sync) begin state <= START; count <= DIVISOR/2 - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:26:57: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 26 | else begin state <= DATA; bit_index <= 0; count <= DIVISOR - 1; end + | ^~ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/uart_rx.sv:29:46: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.receiver' + 29 | shift[bit_index] <= rx_sync; count <= DIVISOR - 1; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:32:43: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'length' generates 16 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 32 | wire [32:0] end_address = {1'b0,address}+length; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=5.050 + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:35:38: Operator ADD expects 32 bits on the RHS, but RHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 35 | wire [31:0] byte_address = address + cursor; + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:67:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 67 | 11,12,13,14:tx_data=RAM_BYTES >> ((reply_index-11)*8); + | ^ +%Warning-WIDTHTRUNC: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:68:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SHIFTR generates 32 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 68 | 15,16,17,18:tx_data=CLOCK_HZ >> ((reply_index-15)*8); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:73:28: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 73 | else if(reply_index==7+reply_length) tx_data=crc[7:0]; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:64:23: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 64 | if(reply_index<7+reply_length) begin + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:119:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 119 | if(cursor+1==length) state<=CRC0; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:144:25: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 144 | else if(cursor+1==length) begin image_loaded<=1;state<=REPLY;end + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:152:20: Operator ADD expects 32 or 16 bits on the LHS, but LHS's VARREF 'cursor' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 152 | if(cursor+1==length) state<=REPLY; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:157:43: Operator LT expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 157 | if(reply_index>=2 && reply_index<7+reply_length) crc<=crc_next(crc,tx_data); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:158:25: Operator EQ expects 32 or 16 bits on the LHS, but LHS's VARREF 'reply_index' generates 9 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 158 | if(reply_index==8+reply_length) state<=DRAIN; + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/ddr_uart_loader.sv:87:37: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'timeout_count' generates 22 bits. + : ... note: In instance 'tb_board_cpu.platform.loader' + 87 | if((receiving && timeout_count==RX_TIMEOUT-1) || (receiving && rx_error)) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:52:20: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 52 | offset=(addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:78:28: Operator AND expects 32 bits on the LHS, but LHS's VARREF 'write_addr' generates 28 bits. + : ... note: In instance 'tb_board_cpu.memory' + 78 | offset=(write_addr & ~(LANES-1))-BASE; + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:86:26: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'h600d600d' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 86 | if (w_bits_data==64'h600d600d) begin + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:91:66: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 91 | $fatal(1,"CPU smoke failed at stage %0d",w_bits_data & 64'hffff); + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:28: Operator AND expects 128 bits on the RHS, but RHS's CONST '64'hffff0000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/axi_smoke_memory.sv:90:43: Operator EQ expects 128 bits on the RHS, but RHS's CONST '64'hbad00000' generates 64 bits. + : ... note: In instance 'tb_board_cpu.memory' + 90 | if ((w_bits_data & 64'hffff0000)==64'hbad00000) + | ^~ +%Warning-WIDTHEXPAND: /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/board/toy_a7_platform.sv:406:33: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits. + : ... note: In instance 'tb_board_cpu.platform' + 406 | assign peripherals_b_bits_resp=|scu_bresp; + | ^ +make: Entering directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/obj' +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_timing.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_timing.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -c -o verilated_threads.o /nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/verilated_threads.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.fast.gch +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -x c++-header Vtb_board_cpu__pch.h -o Vtb_board_cpu__pch.h.slow.gch +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__0.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__1.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__2.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__3.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__4.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__5.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__6.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__7.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__8.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu___024root__9.cpp +g++ -Os -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.fast -c Vtb_board_cpu__main.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__ConstPool__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__0__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__1__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__2__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu___024root__3__Slow.cpp +g++ -I. -MMD -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include -I/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -DVM_VPI=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -DVL_TIME_CONTEXT -fcoroutines -include Vtb_board_cpu__pch.h.slow -c Vtb_board_cpu__Syms__Slow.cpp +g++ verilated.o verilated_timing.o verilated_threads.o Vtb_board_cpu__ALL.a -pthread -lpthread -latomic -o Vtb_board_cpu +rm Vtb_board_cpu__ALL.verilator_deplist.tmp +make: Leaving directory '/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/obj' +- V e r i l a t i o n R e p o r t: Verilator 5.050 2026-07-01 rev v5.050 +- Verilator: Built from 46.457 MB sources in 354 modules, into 26.450 MB in 19 C++ files needing 0.019 MB +- Verilator: Walltime 12.360 s (elab=0.529, cvt=3.158, bld=7.971); cpu 4.683 s on 8 threads; allocated 437.324 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/simulation.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/simulation.log new file mode 100644 index 0000000..d8463e4 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/loop/simulation.log @@ -0,0 +1,5 @@ +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=684219 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.322 s; speed 1.286 ms/s +- Verilator: cpu 5.319 s on 1 threads; allocated 8 MB diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-board-regression.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-board-regression.log new file mode 100644 index 0000000..fd3b723 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-board-regression.log @@ -0,0 +1,31 @@ +PASS fullwidth AXI: sizes 8..128 bits, INCR/FIXED, strobes, concurrent R/W, stalls, IDs, range/4KiB rejection; read beats=90 +/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_axi_fullwidth.sv:107: $finish called at 9270000 (1ps) +PASS SCU OpenSBI byte addresses, AXI lanes, RX pop/IRQ, TX backpressure, EXIT +/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/tests/tb_axi_scu.sv:64: $finish called at 20580000 (1ps) +PASS: DDR UART loader CRC, 256-byte unaligned RAM roundtrip, rejected writes/RUN, timeout and boot +/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-unit/tb_ddr_loader.sv:116: $finish called at 78290000 (1ps) +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=709434 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-cpu/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.829 s; speed 1.217 ms/s +- Verilator: cpu 5.826 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=251063 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-gemmini/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 3ms; walltime 2.245 s; speed 1.118 ms/s +- Verilator: cpu 2.243 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=684219 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-loop/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 7ms; walltime 5.322 s; speed 1.286 ms/s +- Verilator: cpu 5.319 s on 1 threads; allocated 8 MB + +PASS CPU Sv39/FPU/AMO/cache/interrupt through board AXI/SCU cycles=1914839 +- /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/build/board-dma/tb_board_cpu.sv:56: Verilog $finish +- S i m u l a t i o n R e p o r t: Verilator 5.050 2026-07-01 +- Verilator: $finish at 19ms; walltime 14.201 s; speed 1.348 ms/s +- Verilator: cpu 14.194 s on 1 threads; allocated 8 MB + +PASS BOARD_REGRESSION CPU/Gemmini/loop/DMA diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-binding.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-binding.log new file mode 100644 index 0000000..dab7e31 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-binding.log @@ -0,0 +1,24 @@ +Bound 7 memory types, 20 instances +PASS RF adapter matches original port contract; only RF module body replaced +Final core SHA256: 31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9 +{ + "result": "PREPARED_NOT_VALIDATED", + "architectural_profile_unchanged": true, + "existing_memory_geometry_unchanged": true, + "rob_operand_memory": { + "module_name": "robOperands_ext", + "depth": 16, + "width": 128, + "masked": false, + "read": 1, + "write": 1, + "readwrite": 0, + "extra_ports": [], + "hierarchy": [ + "ToyLinuxChip.system.tile_prci_domain.element_reset_domain_bbtile.accelerators_0.frontend.scheduler.rob.robOperands.robOperands_ext" + ] + }, + "rob_operand_ram_style": "block", + "core_rtl_sha256": "31e7e07f94d08208dbb564edf9546240df26ff834935bfb646b71b541d875fb9", + "memory_rtl_sha256": "d5a37896aee19c8d4931c87dc9683861abf32f096a1c1441f4362370d3d7b054" +} diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-elaboration.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-elaboration.log new file mode 100644 index 0000000..0641156 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-core-elaboration.log @@ -0,0 +1,390 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/) +[info] running fpga.arty.linux.EmitToyLinux build/serial-raw --fpga-memories --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/home/yys/bin +/home/yys/.nix-profile/bin +/nix/var/nix/profiles/default/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 130 s (0:02:10.0), completed Oct 12, 2026, 7:58:26 PM +[info] running fpga.arty.linux.EmitToyLinux build/serial-reference --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/home/yys/bin +/home/yys/.nix-profile/bin +/nix/var/nix/profiles/default/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 61 s (0:01:01.0), completed Oct 12, 2026, 7:59:26 PM diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-memory-regression.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-memory-regression.log new file mode 100644 index 0000000..287eefc --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-memory-regression.log @@ -0,0 +1,10 @@ +PASS sram_ext depth=8 width=1269 1R1W +PASS robOperands_ext depth=16 width=128 1R1W +PASS tag_array_ext: original RTL + scoreboard, full depth/mask/enable +PASS array_0_0_ext depth=128 width=128 1R1W +PASS bbtile_icache_tag_array_ext: original RTL + scoreboard, full depth/mask/enable +PASS bbtile_icache_data_arrays_0_ext: original RTL + scoreboard, full depth/mask/enable +PASS mem_ext: original RTL + scoreboard, full depth/mask/enable +PASS all memory bindings +build/serial-bound/tb_memories.sv:585: $finish called at 51147000 (1ps) + diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-candidate.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-candidate.log new file mode 100644 index 0000000..2f8b9c6 --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-candidate.log @@ -0,0 +1,194 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/) +[info] running fpga.arty.linux.EmitToyLinux build/rob-optin-raw --fpga-memories --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 14 s, completed Oct 12, 2026, 8:54:23 PM diff --git a/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-default.log b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-default.log new file mode 100644 index 0000000..b38bf6e --- /dev/null +++ b/platforms/arty-a7-toy/evidence/2026-10-12/rob-ram/tests/rob-optin-default.log @@ -0,0 +1,196 @@ +[info] welcome to sbt 1.12.11 (N/A Java 17.0.20) +[info] loading project definition from /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/project +[info] loading settings for project root from build.sbt... +[info] set current project to toy-arty-a7-linux (in build file:/home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/) +[info] compiling 1 Scala source to /home/yys/codex-builds/toy-a7-rob-ram-20261012-2ebcbc31/target/scala-2.13/classes ... +[info] done compiling +[info] running fpga.arty.linux.EmitToyLinux build/rob-default-raw --fpga-memories --serial-fpga +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 67:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlPreloadStates.scala 83:51: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] VecInit((0 until DIM).map(i => op2Buf(i)(transpose_col))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 16:13: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 46:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op1Buf(xpose_row_cnt) := rdQueue0.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 51:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] op2Buf(xpose_row_cnt) := rdQueue1.io.deq.bits.data +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 68:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val a_col_row = VecInit((0 until DIM).map(i => op1Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlComputeFeedState.scala 69:65: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val x_col_row = VecInit((0 until DIM).map(i => op2Buf(i)(feed_row_cnt))) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 27:15: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(total_rows - 1.U - outBufCollected) := widenMeshToAcc( +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 69:17: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] outBuf(outBufRows) := widenMeshToAcc(mesh.io.resp.bits.data) +[warn] ^ +[warn] patches/buckyball/GemminiExCtrlStoreOps.scala 100:31: [W004] Dynamic index with width 4 is too wide for Vec of size 8 (expected index width 3). +[warn] val row = outBuf(rowIdx) +[warn] ^ +[warn] There were 10 warning(s) during hardware elaboration. +espresso is not found in your PATH: +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/lib/openjdk/bin +/nix/store/2y0qz1r84ckgmmrnfvx9bbysnyn1zb61-openjdk-17.0.20+8/bin +/nix/store/ahvmb4byixykslwcxiay7c4ivhgpf8vg-sbt-1.8.2/bin +/nix/store/0zhg9pq5x1kjgmhy2zdqgj1q310wr5d4-verilator-5.050/bin +/nix/store/y8vkcyc8frd7ipcq0a6jix4xilgm93j7-riscv64-unknown-elf-gcc/bin +/nix/store/ywdz7hiyhb7hkp0vyzqfdx3fmrf1v8pa-yosys-0.67/bin +/home/yys/bin +/usr/local/sbin +/usr/local/bin +/usr/sbin +/usr/bin +/sbin +/bin +/usr/games +/usr/local/games +/snap/bin +Interrupt map (2 harts 1 interrupts): + [1, 1] => system + +:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property +:68.28-71.5: Warning (simple_bus_reg): /soc/external-interrupts: missing or empty reg/ranges property +:72.18-77.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property +:88.18-93.5: Warning (simple_bus_reg): /soc/mbus_clock: missing or empty reg/ranges property +:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property +:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-dev"; + model = "ucb-bar,buckyball"; + L10: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L12: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <32>; + d-cache-size = <8192>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + hardware-exec-breakpoint-count = <0>; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <8192>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdcbzicsr_zifencei_zihpm_zfh_zba_zbb_zbs_xrocket"; + riscv,pmpgranularity = <4>; + riscv,pmpregions = <8>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L6: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L16: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + L9: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ucb-bar,buckyball-soc", "simple-bus"; + ranges; + L3: cbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "cbus_clock"; + compatible = "fixed-clock"; + }; + L13: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L6 3 &L6 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L4: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L15: external-interrupts { + interrupt-parent = <&L14>; + interrupts = <1>; + }; + L2: fbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "fbus_clock"; + compatible = "fixed-clock"; + }; + L14: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L6 11 &L6 9>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <1>; + riscv,ndev = <1>; + }; + L5: mbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "mbus_clock"; + compatible = "fixed-clock"; + }; + L17: mmio-port-axi4@60000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x60000000 0x60000000 0x10000000>; + }; + L1: pbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "pbus_clock"; + compatible = "fixed-clock"; + }; + L18: rom@10000 { + compatible = "sifive,rom0"; + reg = <0x10000 0x10000>; + reg-names = "mem"; + }; + L0: sbus_clock { + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "sbus_clock"; + compatible = "fixed-clock"; + }; + }; +}; + +Generated Address Map + 3000 - 4000 ARWX error-device@3000 + 10000 - 20000 R X rom@10000 + 2000000 - 2010000 ARW clint@2000000 + c000000 - 10000000 ARW interrupt-controller@c000000 + 60000000 - 70000000 RWX mmio-port-axi4@60000000 + 80000000 - 90000000 RWXC memory@80000000 + +[warn] thirdparty/rocket-chip/src/main/scala/rocket/NBDcache.scala 456:25: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0). +[warn] io.refill := refillMux(io.mem_grant.bits.source) +[warn] ^ +[warn] There were 1 warning(s) during hardware elaboration. +[success] Total time: 19 s, completed Oct 12, 2026, 8:54:06 PM diff --git a/platforms/arty-a7-toy/patches/framework/GlobalROB.scala b/platforms/arty-a7-toy/patches/framework/GlobalROB.scala new file mode 100644 index 0000000..2cd7e8d --- /dev/null +++ b/platforms/arty-a7-toy/patches/framework/GlobalROB.scala @@ -0,0 +1,603 @@ +package framework.frontend.globalrs + +import chisel3._ +import chisel3.util._ +import chisel3.experimental._ +import chisel3.experimental.hierarchy.{instantiable, public, Instance, Instantiate} +import framework.top.GlobalConfig +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.frontend.scoreboard.{BankAccessInfo, BankAliasTable, BankScoreboard} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT +import framework.memdomain.backend.shared.SharedMemLayout +import framework.memdomain.backend.banks.btrace.{BTraceDPI, PhysicalBankHash} + +@instantiable +class GlobalROB(val b: GlobalConfig, useOperandRam: Boolean = GlobalROB.operandRamEnabled) extends Module { + + val robDepth = b.frontend.rob_entries + val idWidth = log2Up(robDepth) + val scoreBankNum = b.memDomain.virtualBankCount + robDepth + val sharedHashCount = if (b.memDomain.sharedEnable) SharedMemLayout.totalBank(b) else 0 + val physicalBankCount = b.memDomain.bankNum + sharedHashCount + + require( + b.frontend.vbank_id_upper_bound < b.memDomain.virtualBankCount, + s"vbank_id_upper_bound(${b.frontend.vbank_id_upper_bound}) must be < virtualBankCount(${b.memDomain.virtualBankCount})" + ) + + @public + val io = IO(new Bundle { + val hart_id = Input(UInt(b.tile.xLen.W)) + val alloc = Flipped(new DecoupledIO(new PostGDCmd(b))) + val issue = new DecoupledIO(new GlobalRobEntry(b)) + val complete = Flipped(new DecoupledIO(UInt(idWidth.W))) + + val empty = Output(Bool()) + val full = Output(Bool()) + val head_ptr = Output(UInt(idWidth.W)) + val issued_count = Output(UInt(log2Up(robDepth + 1).W)) + val entry_valid = Output(Vec(robDepth, Bool())) + val entry_complete = Output(Vec(robDepth, Bool())) + + val subRobActive = Input(Bool()) + val inst_ids = Output(Vec(robDepth, UInt(64.W))) + + val bank_hashes = + if (b.sim.diffTest) { + Some(Input(Vec(physicalBankCount, new PhysicalBankHash(b)))) + } else { + None + } + + }) + + // --------------------------------------------------------------------------- + // BAT + Bank Scoreboard + // --------------------------------------------------------------------------- + val bat: Instance[BankAliasTable] = Instantiate( + new BankAliasTable( + bankIdLen = b.frontend.bank_id_len, + vbankUpper = b.memDomain.virtualBankCount - 1, + robEntries = robDepth + ) + ) + + val scoreboard: Instance[BankScoreboard] = + Instantiate(new BankScoreboard(b.frontend.bank_id_len, scoreBankNum, robDepth)) + + // --------------------------------------------------------------------------- + // Instruction trace (DPI-C, defined in ITraceDPI.scala) + // --------------------------------------------------------------------------- + val itraceAlloc = Module(new ITraceDPI) + val itraceIssue = Module(new ITraceDPI) + val itraceComp = Module(new ITraceDPI) + + for (t <- Seq(itraceAlloc, itraceIssue, itraceComp)) { + t.io.clock := clock + t.io.reset := reset.asBool + t.io.is_issue := 0.U + t.io.hart_id := io.hart_id + t.io.rob_id := 0.U + t.io.inst_id := 0.U + t.io.domain_id := 0.U + t.io.funct := 0.U + t.io.pc := 0.U + t.io.rs1_data := 0.U + t.io.rs2_data := 0.U + t.io.enable := false.B + } + + // --------------------------------------------------------------------------- + // Storage + // --------------------------------------------------------------------------- + val robEntries = RegInit(VecInit(Seq.fill(robDepth)(0.U.asTypeOf(new GlobalRobEntry(b))))) + // Only the issued payload needs the full operands. Keep existing copies for + // trace/commit observation; Vivado removes trace-only bits with DPI disabled. + // MSET's low rs2 bits stay in registers for the parallel commit scan. + private val operandWidth = b.tile.xLen + private val operandRam = if (useOperandRam) { + Some(SyncReadMem(robDepth, UInt((2 * operandWidth).W)).suggestName("robOperands")) + } else None + val robValid = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robIssued = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val robComplete = RegInit(VecInit(Seq.fill(robDepth)(false.B))) + val instIds = RegInit(VecInit(Seq.fill(robDepth)(0.U(64.W)))) + val nextInstId = RegInit(1.U(64.W)) + + val statusHashes = + if (b.sim.diffTest) { + Some(RegInit(VecInit(Seq.fill(robDepth)(VecInit(Seq.fill(3)(0.U(32.W))))))) + } else { + None + } + + io.inst_ids := instIds + + val headPtr = RegInit(0.U(idWidth.W)) + val tailPtr = RegInit(0.U(idWidth.W)) + val issuedCount = RegInit(0.U(log2Up(robDepth + 1).W)) + private val bankColWidth = b.memDomain.groupCountWidth + val bankCols = RegInit(VecInit(Seq.fill(b.memDomain.virtualBankCount)(0.U(bankColWidth.W)))) + // In-flight ownership is tracked in the architectural vbank namespace. + private val vbankMaskWidth = b.memDomain.virtualBankCount + val vbankBusy = RegInit(0.U(vbankMaskWidth.W)) + + // Dependency state is maintained incrementally instead of rebuilding all + // older-entry comparisons every cycle. A bit in slot k names the ROB slot + // that currently blocks k. Ordinary RAW dependencies disappear at complete; + // dependencies involving a mapping/config instruction disappear at commit. + // Keeping one union mask is sufficient because a config dependency is never + // allowed to clear earlier than commit, even when it also looks like a RAW. + val dependencyMask = RegInit(VecInit(Seq.fill(robDepth)(0.U(robDepth.W)))) + + val isEmpty = headPtr === tailPtr && !robValid(headPtr) + val isFull = headPtr === tailPtr && robValid(headPtr) + + def nextPtr(p: UInt): UInt = Mux(p === (robDepth - 1).U, 0.U, p + 1.U) + def wrapPtr(v: UInt): UInt = Mux(v >= robDepth.U, v - robDepth.U, v) + def robIdx(v: UInt): UInt = v(idWidth - 1, 0) + + def isMappingConfig(entry: GlobalRobEntry): Bool = + entry.cmd.domain_id === DomainId.MEM && + (entry.cmd.cmd.funct === MSET_BITPAT) + + def accessUsesBank(access: BankAccessInfo, bank: UInt): Bool = + (access.rd_bank_0_valid && access.rd_bank_0_id === bank) || + (access.rd_bank_1_valid && access.rd_bank_1_id === bank) || + (access.wr_bank_valid && access.wr_bank_id === bank) + + // Build one architectural-vbank mask per ROB slot once, then hazard checks + // become mask intersections instead of repeating ID comparisons. + private val hazardBankCount = b.memDomain.virtualBankCount + + def rawReadMask(access: BankAccessInfo): UInt = { + val rd0 = Mux( + access.rd_bank_0_valid && access.rd_bank_0_id < hazardBankCount.U, + UIntToOH(access.rd_bank_0_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + val rd1 = Mux( + access.rd_bank_1_valid && access.rd_bank_1_id < hazardBankCount.U, + UIntToOH(access.rd_bank_1_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + rd0 | rd1 + } + + def rawWriteMask(access: BankAccessInfo): UInt = Mux( + access.wr_bank_valid && access.wr_bank_id < hazardBankCount.U, + UIntToOH(access.wr_bank_id, hazardBankCount), + 0.U(hazardBankCount.W) + ) + + def rawUseMask(access: BankAccessInfo): UInt = + rawReadMask(access) | rawWriteMask(access) + + // --------------------------------------------------------------------------- + // Allocate: enqueue decoded instruction into ROB + // rob_id == tailPtr at allocation time (no separate counter needed) + // --------------------------------------------------------------------------- + val commitMask = Wire(Vec(robDepth, Bool())) + for (i <- 0 until robDepth) { + commitMask(i) := false.B + } + bat.io.free.valid := commitMask.asUInt.orR + bat.io.free.mask := commitMask + + val commitScan = Wire(Vec(robDepth, Bool())) + val commitKeep = Wire(Vec(robDepth + 1, Bool())) + commitKeep(0) := true.B + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + commitScan(i) := commitKeep(i) && robValid(ptr) && robComplete(ptr) + commitKeep(i + 1) := (if (b.sim.diffTest) false.B else commitScan(i)) + } + val hasCommit = commitScan.asUInt.orR + val tailAlias = Wire(UInt(b.frontend.bank_id_len.W)) + tailAlias := + b.memDomain.virtualBankCount.U(b.frontend.bank_id_len.W) + tailPtr + + val tailAliasLive = WireDefault(false.B) + for (i <- 0 until robDepth) { + when(robValid(i) && !robComplete(i) && accessUsesBank(robEntries(i).renamedBankAccess, tailAlias)) { + tailAliasLive := true.B + } + } + + io.alloc.ready := !isFull && !hasCommit && !tailAliasLive + bat.io.alloc.valid := io.alloc.fire + bat.io.alloc.rob_id := tailPtr + bat.io.alloc.raw := io.alloc.bits.bankAccess + + // Mark write alias as busy in scoreboard at alloc time (not issue time). + scoreboard.alloc.valid := io.alloc.fire && io.alloc.bits.bankAccess.wr_bank_valid + scoreboard.alloc.bits := bat.io.alloc_renamed + + // Bank masks are shared by allocation and issue. This avoids rebuilding the + // UIntToOH decoders once for every older-entry comparison at allocation. + val entryRawReads = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryRawWrites = Wire(Vec(robDepth, UInt(hazardBankCount.W))) + val entryIsConfig = Wire(Vec(robDepth, Bool())) + for (slot <- 0 until robDepth) { + entryRawReads(slot) := rawReadMask(robEntries(slot).cmd.bankAccess) + entryRawWrites(slot) := rawWriteMask(robEntries(slot).cmd.bankAccess) + entryIsConfig(slot) := isMappingConfig(robEntries(slot)) + } + + // A newly allocated entry is always younger than all currently valid ROB + // entries (tailPtr points at the first free slot). Capture its older-entry + // dependencies once here; issue no longer repeats pairwise comparisons. + val allocReadMask = rawReadMask(io.alloc.bits.bankAccess) + val allocWriteMask = rawWriteMask(io.alloc.bits.bankAccess) + val allocIsConfig = io.alloc.bits.domain_id === DomainId.MEM && + (io.alloc.bits.cmd.funct === MSET_BITPAT) + val allocIsBall = io.alloc.bits.domain_id === DomainId.BALL + val allocDependencyBits = Wire(Vec(robDepth, Bool())) + for (older <- 0 until robDepth) { + val olderUseMask = entryRawReads(older) | entryRawWrites(older) + val rawConflict = ((allocReadMask & entryRawWrites(older)) | + (allocWriteMask & olderUseMask)).orR + val configConflict = (allocIsConfig && entryIsConfig(older)) || + ((allocIsConfig || entryIsConfig(older)) && ((allocReadMask | allocWriteMask) & olderUseMask).orR) + val sameBall = allocIsBall && + robEntries(older).cmd.domain_id === DomainId.BALL && + robEntries(older).cmd.ball_bid === io.alloc.bits.ball_bid + // Config conflicts include entries that have completed but are waiting to + // commit. RAW conflicts and same-Ball commands release at completion. + allocDependencyBits(older) := + (robValid(older) && !robComplete(older) && (rawConflict || sameBall)) || + (robValid(older) && configConflict) + } + val allocDependencies = allocDependencyBits.asUInt + val allocUsesInstId = io.alloc.bits.cmd.pc =/= 0.U + + when(io.alloc.fire) { + operandRam.foreach(_.write(tailPtr, Cat(io.alloc.bits.cmd.rs1Data, io.alloc.bits.cmd.rs2Data))) + itraceAlloc.io.is_issue := 2.U + itraceAlloc.io.rob_id := tailPtr + itraceAlloc.io.inst_id := Mux(allocUsesInstId, nextInstId, 0.U) + itraceAlloc.io.domain_id := io.alloc.bits.domain_id + itraceAlloc.io.funct := io.alloc.bits.cmd.funct + itraceAlloc.io.pc := io.alloc.bits.cmd.pc + itraceAlloc.io.rs1_data := io.alloc.bits.cmd.rs1Data + itraceAlloc.io.rs2_data := io.alloc.bits.cmd.rs2Data + itraceAlloc.io.enable := true.B + + robEntries(tailPtr).cmd := io.alloc.bits + robEntries(tailPtr).renamedBankAccess := bat.io.alloc_renamed + robEntries(tailPtr).rob_id := tailPtr + instIds(tailPtr) := Mux(allocUsesInstId, nextInstId, 0.U) + robValid(tailPtr) := true.B + robIssued(tailPtr) := false.B + robComplete(tailPtr) := false.B + statusHashes.foreach { hashes => + for (slot <- 0 until 3) { + hashes(tailPtr)(slot) := 0.U + } + } + tailPtr := nextPtr(tailPtr) + when(allocUsesInstId) { + nextInstId := nextInstId + 1.U + } + } + + // --------------------------------------------------------------------------- + // Complete: mark entry as completed, release scoreboard resources + // --------------------------------------------------------------------------- + if (b.sim.diffTest) { + val collecting = RegInit(false.B) + val collectCid = Reg(UInt(idWidth.W)) + val collectSlot = Reg(UInt(2.W)) + val collectGroup = Reg(UInt(32.W)) + val currentHash = Reg(UInt(32.W)) + val hashReady = RegInit(false.B) + val hashCid = Reg(UInt(idWidth.W)) + + val incomingAccess = robEntries(io.complete.bits).cmd.bankAccess + val incomingNeedsHash = instIds(io.complete.bits) =/= 0.U && !isMappingConfig(robEntries(io.complete.bits)) && + (incomingAccess.rd_bank_0_valid || incomingAccess.rd_bank_1_valid || incomingAccess.wr_bank_valid) + io.complete.ready := !incomingNeedsHash || (hashReady && hashCid === io.complete.bits) + + when(!collecting && !hashReady && io.complete.valid && incomingNeedsHash) { + collecting := true.B + collectCid := io.complete.bits + collectSlot := Mux(incomingAccess.rd_bank_0_valid, 0.U, Mux(incomingAccess.rd_bank_1_valid, 1.U, 2.U)) + collectGroup := 0.U + currentHash := 0.U + } + + val access = robEntries(collectCid).cmd.bankAccess + val vbank = MuxLookup(collectSlot, access.wr_bank_id)(Seq( + 0.U -> access.rd_bank_0_id, + 1.U -> access.rd_bank_1_id, + 2.U -> access.wr_bank_id + )) + val hasNextSlot = MuxLookup(collectSlot, false.B)(Seq( + 0.U -> (access.rd_bank_1_valid || access.wr_bank_valid), + 1.U -> access.wr_bank_valid + )) + val nextSlot = Mux(collectSlot === 0.U && access.rd_bank_1_valid, 1.U, 2.U) + val matches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + }) + val nextMatches = VecInit(io.bank_hashes.get.map { state => + state.valid && state.hartId === io.hart_id && state.vbankId === vbank && state.groupId === collectGroup + 1.U + }) + val physical = Mux1H(matches, io.bank_hashes.get) + def rotateLeft(value: UInt, amount: Int): UInt = Cat(value(31 - amount, 0), value(31, 32 - amount)) + + val mixed = physical.statusHash ^ rotateLeft(physical.groupId, 7) ^ "h9e3779b9".U + val nextHash = rotateLeft(currentHash, 5) ^ mixed ^ rotateLeft(mixed, 13) + + when(collecting) { + assert(PopCount(matches) === 1.U, "BTrace requires exactly one physical bank per vbank group") + when(nextMatches.asUInt.orR) { + currentHash := nextHash + collectGroup := collectGroup + 1.U + }.otherwise { + statusHashes.get(collectCid)(collectSlot) := nextHash + when(hasNextSlot) { + collectSlot := nextSlot + collectGroup := 0.U + currentHash := 0.U + }.otherwise { + collecting := false.B + hashReady := true.B + hashCid := collectCid + } + } + } + + when(io.complete.fire) { + hashReady := false.B + } + } else { + io.complete.ready := true.B + } + + scoreboard.complete.valid := false.B + scoreboard.complete.bits := 0.U.asTypeOf(scoreboard.complete.bits) + + val issueFired = WireDefault(false.B) + val completeIssuedEntry = io.complete.fire && robIssued(io.complete.bits) + + when(io.complete.fire) { + val cid = io.complete.bits + robComplete(cid) := true.B + scoreboard.complete.valid := true.B + scoreboard.complete.bits := robEntries(cid).renamedBankAccess + + itraceComp.io.is_issue := 0.U + itraceComp.io.rob_id := cid + itraceComp.io.inst_id := instIds(cid) + itraceComp.io.domain_id := robEntries(cid).cmd.domain_id + itraceComp.io.funct := robEntries(cid).cmd.cmd.funct + itraceComp.io.pc := robEntries(cid).cmd.cmd.pc + itraceComp.io.rs1_data := robEntries(cid).cmd.cmd.rs1Data + itraceComp.io.rs2_data := robEntries(cid).cmd.cmd.rs2Data + itraceComp.io.enable := true.B + } + + val completedBitMask = Mux( + io.complete.fire, + UIntToOH(io.complete.bits, robDepth), + 0.U(robDepth.W) + ) + + // --------------------------------------------------------------------------- + // Issue: scan from head for first issuable entry (valid && !issued && !complete) + // --------------------------------------------------------------------------- + val scanValid = Wire(Vec(robDepth, Bool())) + val scanReady = Wire(Vec(robDepth, Bool())) + val vbankMasks = Wire(Vec(robDepth, UInt(vbankMaskWidth.W))) + for (slot <- 0 until robDepth) { + // Reuse the raw hazard mask for active-command ownership. + vbankMasks(slot) := entryRawReads(slot) | entryRawWrites(slot) + } + + // Check each candidate against older ROB entries using mask intersections. + // The masks are precomputed once per slot, so this retains the original + // age-sensitive RAW/WAR/WAW semantics without replicating three equality + // comparators for every bank access pair. + for (i <- 0 until robDepth) { + val ptr = robIdx(wrapPtr(headPtr + i.U)) + scanValid(i) := robValid(ptr) && !robIssued(ptr) && !robComplete(ptr) + scoreboard.queryVec(i) := robEntries(ptr).renamedBankAccess + scanReady(i) := scanValid(i) && !scoreboard.hazardVec(i) && + !dependencyMask(ptr).orR && + !(vbankMasks(ptr) & vbankBusy).orR + } + + val hasReady = scanReady.asUInt.orR + val firstReady = PriorityEncoder(scanReady.asUInt) + val actualIssuePtr = robIdx(wrapPtr(headPtr + firstReady)) + + scoreboard.query := robEntries(actualIssuePtr).renamedBankAccess + val canIssue = hasReady + + val issueStageValid = RegInit(false.B) + val issueStageEntry = Reg(new GlobalRobEntry(b)) + val issueStageFire = issueStageValid && !io.subRobActive && io.issue.ready + val issueStageReady = !issueStageValid || issueStageFire + + // Keep the wide ROB entry and bank-column mux one register boundary away + // from the age/scoreboard scan. The pointer stage can accept one candidate + // per cycle; the payload stage drains at one per cycle, so steady-state II + // remains one while the extra latency is hidden by in-flight commands. + val issuePtrValid = RegInit(false.B) + val issuePtr = Reg(UInt(idWidth.W)) + val issuePtrFire = issuePtrValid && issueStageReady + val issuePtrReady = !issuePtrValid || issuePtrFire + val issueLoad = canIssue && !io.subRobActive && issuePtrReady + val issuePayload = Wire(new GlobalRobEntry(b)) + issuePayload := robEntries(issuePtr) + operandRam.foreach { memory => + // Read at pointer selection, then re-read while that pointer is stalled. + // Replacement selects the new pointer; the current response is consumed + // before the next edge. This preserves the existing two-stage issue timing. + val readAddress = Mux(issueLoad, actualIssuePtr, issuePtr) + val readEnable = issueLoad || issuePtrValid + val operands = memory.read(readAddress, readEnable) + issuePayload.cmd.cmd.rs1Data := operands(2 * operandWidth - 1, operandWidth) + issuePayload.cmd.cmd.rs2Data := operands(operandWidth - 1, 0) + when(io.alloc.fire && readEnable) { + assert(tailPtr =/= readAddress, "ROB operand RAM read/write collision") + } + } + issuePayload.cmd.op1_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_0_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_0_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.op2_col := Mux( + issuePayload.cmd.bankAccess.rd_bank_1_valid, + bankCols(issuePayload.cmd.bankAccess.rd_bank_1_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + issuePayload.cmd.wr_col := Mux( + issuePayload.cmd.bankAccess.wr_bank_valid, + bankCols(issuePayload.cmd.bankAccess.wr_bank_id(b.memDomain.vbankIdWidth - 1, 0)), + 0.U + ) + + io.issue.valid := issueStageValid && !io.subRobActive + io.issue.bits := issueStageEntry + + when(issuePtrReady) { + issuePtrValid := issueLoad + when(issueLoad) { + issuePtr := actualIssuePtr + } + } + when(issueStageReady) { + issueStageValid := issuePtrValid + when(issuePtrFire) { + issueStageEntry := issuePayload + } + } + + scoreboard.issue.valid := false.B + scoreboard.issue.bits := 0.U.asTypeOf(scoreboard.issue.bits) + + when(issueLoad) { + robIssued(actualIssuePtr) := true.B + issueFired := true.B + scoreboard.issue.valid := true.B + scoreboard.issue.bits := robEntries(actualIssuePtr).renamedBankAccess + + itraceIssue.io.is_issue := 1.U + itraceIssue.io.rob_id := robEntries(actualIssuePtr).rob_id + itraceIssue.io.inst_id := instIds(actualIssuePtr) + itraceIssue.io.domain_id := robEntries(actualIssuePtr).cmd.domain_id + itraceIssue.io.funct := robEntries(actualIssuePtr).cmd.cmd.funct + itraceIssue.io.pc := robEntries(actualIssuePtr).cmd.cmd.pc + itraceIssue.io.rs1_data := robEntries(actualIssuePtr).cmd.cmd.rs1Data + itraceIssue.io.rs2_data := robEntries(actualIssuePtr).cmd.cmd.rs2Data + itraceIssue.io.enable := true.B + } + + // Preserve the original update ordering when issue and complete coincide: + // a completion clears ownership after the newly issued transaction marks + // its banks busy. + val issuedVbankMask = Mux(issueLoad, vbankMasks(actualIssuePtr), 0.U) + val completedVbankMask = Mux(io.complete.fire, vbankMasks(io.complete.bits), 0.U) + when(issueLoad || io.complete.fire) { + vbankBusy := + (vbankBusy & ~completedVbankMask) | issuedVbankMask + } + + issuedCount := issuedCount + issueFired.asUInt - completeIssuedEntry.asUInt + + // --------------------------------------------------------------------------- + // Commit: clear completed entries. + // Explicitly skip entries being allocated or completed this cycle. + // --------------------------------------------------------------------------- + for (i <- 0 until robDepth) { + val hits = (0 until robDepth).map { off => + val ptr = robIdx(wrapPtr(headPtr + off.U)) + commitScan(off) && ptr === i.U + } + commitMask(i) := hits.reduce(_ || _) + when(commitMask(i)) { + when(robEntries(i).cmd.domain_id === DomainId.MEM && robEntries(i).cmd.cmd.funct === MSET_BITPAT) { + val bankId = robEntries(i).cmd.bankAccess.wr_bank_id + val bank = bankId(b.memDomain.vbankIdWidth - 1, 0) + val col = robEntries(i).cmd.cmd.rs2Data(9, 5) + when(robEntries(i).cmd.cmd.rs2Data(10)) { + val fullCol = + if (b.memDomain.sharedEnable) { + Mux( + bankId >= b.frontend.shared_bank_id_base.U && bankId < b.memDomain.virtualBankCount.U, + SharedMemLayout.totalBank(b).U(bankColWidth.W), + b.memDomain.bankNum.U(bankColWidth.W) + ) + } else { + b.memDomain.bankNum.U(bankColWidth.W) + } + bankCols(bank) := Mux(col === 0.U, fullCol, col) + }.otherwise { + bankCols(bank) := 0.U + } + } + robValid(i) := false.B + robIssued(i) := false.B + robComplete(i) := false.B + } + } + + if (b.sim.diffTest) { + val commitIndex = PriorityEncoder(commitMask.asUInt) + val commitAccess = robEntries(commitIndex).cmd.bankAccess + val invalidVbank = "hffffffff".U(32.W) + val btrace = Module(new BTraceDPI) + btrace.io.clock := clock + btrace.io.reset := reset.asBool + btrace.io.instId := instIds(commitIndex) + btrace.io.hartId := io.hart_id + btrace.io.r0Vbank := Mux(commitAccess.rd_bank_0_valid, commitAccess.rd_bank_0_id, invalidVbank) + btrace.io.r0Hash := Mux(commitAccess.rd_bank_0_valid, statusHashes.get(commitIndex)(0), 0.U) + btrace.io.r1Vbank := Mux(commitAccess.rd_bank_1_valid, commitAccess.rd_bank_1_id, invalidVbank) + btrace.io.r1Hash := Mux(commitAccess.rd_bank_1_valid, statusHashes.get(commitIndex)(1), 0.U) + btrace.io.w0Vbank := Mux(commitAccess.wr_bank_valid, commitAccess.wr_bank_id, invalidVbank) + btrace.io.w0Hash := Mux(commitAccess.wr_bank_valid, statusHashes.get(commitIndex)(2), 0.U) + btrace.io.fire := hasCommit && instIds(commitIndex) =/= 0.U && !isMappingConfig(robEntries(commitIndex)) && + (commitAccess.rd_bank_0_valid || commitAccess.rd_bank_1_valid || commitAccess.wr_bank_valid) + } + + // Maintain dependency masks at the same architectural events that gate the + // issue scan. A dependency involving a config entry (on either side) clears + // only at commit; all other dependencies clear at complete. This is the + // union-mask form of the former separate RAW/config masks. + val configEntryMask = entryIsConfig.asUInt + for (slot <- 0 until robDepth) { + val isAllocatedSlot = io.alloc.fire && tailPtr === slot.U + val slotIsConfig = Mux(isAllocatedSlot, allocIsConfig, entryIsConfig(slot)) + // Each dependency bit names the older entry that blocks this slot. Keep a + // config-related edge through completion when either endpoint is config. + val configRelated = configEntryMask | Fill(robDepth, slotIsConfig) + val clearMask = commitMask.asUInt | (completedBitMask & ~configRelated) + when(isAllocatedSlot) { + dependencyMask(slot) := allocDependencies & ~clearMask + }.otherwise { + dependencyMask(slot) := dependencyMask(slot) & ~clearMask + } + } + + val commitCount = PopCount(commitScan) + headPtr := wrapPtr(headPtr + commitCount) + + // --------------------------------------------------------------------------- + // Status outputs + // --------------------------------------------------------------------------- + io.empty := isEmpty + io.full := isFull + io.head_ptr := headPtr + io.issued_count := issuedCount + io.entry_valid := robValid + io.entry_complete := robComplete + +} + +object GlobalROB { + def operandRamEnabled: Boolean = java.lang.Boolean.getBoolean("fpga.robOperandRam") +} diff --git a/platforms/arty-a7-toy/scripts/check_globalrob.py b/platforms/arty-a7-toy/scripts/check_globalrob.py new file mode 100644 index 0000000..d563932 --- /dev/null +++ b/platforms/arty-a7-toy/scripts/check_globalrob.py @@ -0,0 +1,64 @@ +"""核验同步 RAM 与原寄存器路径逐周期等价，包括背压、绕回和中途复位。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re +import subprocess + +ROOT = Path(__file__).resolve().parents[1] + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--skip-elaboration", action="store_true") + args = parser.parse_args() + out = ROOT / "build/globalrob-check" + out.mkdir(parents=True, exist_ok=True) + commands = [] + if not args.skip_elaboration: + commands.append((["sbt", "-batch", "runMain fpga.arty.linux.EmitGlobalRobCheck"], + "elaboration.log", 900)) + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + # CIRCT appends named inline resources and the .f index to one emission. + # Keep the untouched emission, compile only Verilog sections. + parts = re.split(r'// ----- 8< ----- FILE "([^"]+)" ----- 8< -----', + (out / "GlobalRobCheck.sv").read_text()) + modules = [parts[0]] + for name, body in zip(parts[1::2], parts[2::2]): + if name.endswith((".sv", ".v")): + modules.append(body) + elif name == "firrtl_black_box_resource_files.f": + if not all(line.strip().endswith(".v") for line in body.splitlines() if line.strip()): + raise ValueError("Unexpected inline resource index") + else: + raise ValueError("Unexpected emitted resource: " + name) + rtl = out / "GlobalRobCheck.sim.sv" + rtl.write_text("\n".join(modules)) + commands = [(["verilator", "--binary", "--timing", "--assert", "-j", "4", "-Wno-fatal", + "-DBUCKYBALL_DISABLE_DPI", "--top-module", "tb", "--Mdir", str(out / "obj"), + str(rtl), str(ROOT / "tests/tb_globalrob.sv")], + "compile.log", 600), + ([str(out / "obj/Vtb")], "simulation.log", 60)] + for command, name, timeout in commands: + with (out / name).open("w") as log: + subprocess.run(command, cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, + timeout=timeout, check=True) + transcript = (out / "simulation.log").read_text() + if "PASS GLOBALROB RAM/register cycle comparison" not in transcript: + raise ValueError("GlobalROB passing marker missing") + record = {"result": "PASS", "cycle_equivalence": True, + "coverage": ["accepted operand integrity", "ROB full", "pointer wrap", + "issue backpressure", "SubROB ownership stall", "mid-flight resets", + "concurrent allocation/issue/completion", "complete drain"], + "rtl_sha256": hashlib.sha256((out / "GlobalRobCheck.sv").read_bytes()).hexdigest()} + (out / "RESULT.json").write_text(json.dumps(record, indent=2) + "\n") + print(transcript) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/elaborate_rob_candidate.sh b/platforms/arty-a7-toy/scripts/elaborate_rob_candidate.sh new file mode 100644 index 0000000..f89674c --- /dev/null +++ b/platforms/arty-a7-toy/scripts/elaborate_rob_candidate.sh @@ -0,0 +1,13 @@ +#!/usr/bin/env bash +set -euo pipefail +cd "$(dirname "$0")/.." +python3 scripts/prepare_sources.py "$@" +python3 scripts/resolve_config.py +python3 scripts/check_globalrob.py +sbt -Dfpga.robOperandRam=true -batch \ + 'runMain fpga.arty.linux.EmitToyLinux build/serial-raw --fpga-memories --serial-fpga' \ + 'runMain fpga.arty.linux.EmitToyLinux build/serial-reference --serial-fpga' \ + 'runMain fpga.arty.linux.EmitRoutingCheck build/routing-check' +python3 scripts/prepare_rob_candidate.py \ + --baseline-memory-manifest evidence/2026-10-11/MEMORY_MANIFEST.json +python3 scripts/export_capabilities.py diff --git a/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py b/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py index 6c2b253..049f434 100644 --- a/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py +++ b/platforms/arty-a7-toy/scripts/prepare_fpga_memories.py @@ -93,14 +93,14 @@ def emit_dual_memory(mem, style): return "\n".join(lines), style -def emit_memory(mem): +def emit_memory(mem, force_block=False): name, depth, width = (mem[k] for k in ("module_name", "depth", "width")) gran = mem.get("mask_granularity", width) lanes = width // gran addr = (depth - 1).bit_length() # A 64-row bank fits one LUT RAM per bit. Avoid wasting deep BRAM blocks # on shallow tags, MMIO banks and SubROB; keep 1024-row data banks in BRAM. - style = "distributed" if depth <= 64 else "block" + style = "block" if force_block else "distributed" if depth <= 64 else "block" if mem["read"] == 1: return emit_dual_memory(mem, style) ports = [ @@ -156,13 +156,19 @@ def main(): parser = argparse.ArgumentParser(description=__doc__) parser.add_argument("emission", type=Path) parser.add_argument("--output-dir", type=Path, required=True) + parser.add_argument("--block-memory", action="append", default=[], + help="明确将指定宏映射到 BRAM，包括 ROB 的浅层宽操作数 RAM") args = parser.parse_args() raw = args.emission.read_bytes() rtl, metadata, config = unpack_emission(raw.decode()) validate(metadata, config) + requested = set(args.block_memory) + available = {mem["module_name"] for mem in metadata} + if not requested <= available: + raise ValueError("Unknown block memory: " + ", ".join(sorted(requested - available))) modules, mappings = [], [] for mem in metadata: - module, style = emit_memory(mem) + module, style = emit_memory(mem, mem["module_name"] in requested) modules.append(module) mappings.append({**mem, "ram_style": style}) macros = "\n".join(modules) diff --git a/platforms/arty-a7-toy/scripts/prepare_rob_candidate.py b/platforms/arty-a7-toy/scripts/prepare_rob_candidate.py new file mode 100644 index 0000000..615b19d --- /dev/null +++ b/platforms/arty-a7-toy/scripts/prepare_rob_candidate.py @@ -0,0 +1,60 @@ +"""为 ROB 操作数候选显式绑定 BRAM，核对 profile 与已有存储器几何参数。""" + +import argparse +import hashlib +import json +from pathlib import Path +import subprocess +import sys + +from prepare_fpga_memories import unpack_emission, validate + +ROOT = Path(__file__).resolve().parents[1] + + +def digest(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--baseline-memory-manifest", type=Path, required=True) + args = parser.parse_args() + raw = ROOT / "build/serial-raw/ToyLinuxChip.sv" + profile = json.loads((ROOT / "build/serial-raw/ToyLinuxChip.profile.json").read_text()) + expected = json.loads((ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json").read_text()) + if profile != expected: + raise ValueError("Optimization changed the architectural hardware profile") + _, memories, config = unpack_emission(raw.read_text()) + validate(memories, config) + operands = [m for m in memories if any("robOperands" in h for h in m["hierarchy"])] + if len(operands) != 1: + raise ValueError("Expected one ROB operand memory type") + operand = operands[0] + if (operand["depth"], operand["width"], operand["read"], operand["write"], + operand["readwrite"], operand["masked"], len(operand["hierarchy"])) != (16, 128, 1, 1, 0, False, 1): + raise ValueError("Unexpected ROB memory geometry or topology") + baseline = json.loads(args.baseline_memory_manifest.read_text()) + if baseline["core_rtl_sha256"] != "4c6aacf64660bbbf14b1114e8d5e4439d6a4e1427aaf1f681c6a4f618f2d2779": + raise ValueError("Wrong baseline memory manifest") + def signature(memory): + return tuple(memory.get(k) for k in + ("depth", "width", "read", "write", "readwrite", "masked", "mask_granularity")) + before = sorted((signature(m), len(m["hierarchy"])) for m in baseline["memories"]) + after = sorted((signature(m), len(m["hierarchy"])) for m in memories if m != operand) + if before != after: + raise ValueError("An existing memory geometry/topology changed") + subprocess.run([sys.executable, str(ROOT / "scripts/prepare_fpga_memories.py"), str(raw), + "--output-dir", str(ROOT / "build/serial-bound"), + "--block-memory", operand["module_name"]], check=True, timeout=60) + subprocess.run([sys.executable, str(ROOT / "scripts/bind_fpu_rf.py")], check=True, timeout=60) + record = {"result": "PREPARED_NOT_VALIDATED", "architectural_profile_unchanged": True, + "existing_memory_geometry_unchanged": True, "rob_operand_memory": operand, + "rob_operand_ram_style": "block", "core_rtl_sha256": digest(ROOT / "build/serial-bound/ToyLinuxChip.sv"), + "memory_rtl_sha256": digest(ROOT / "build/serial-bound/FpgaMemories.sv")} + (ROOT / "build/ROB_RAM_PREPARED.json").write_text(json.dumps(record, indent=2) + "\n") + print(json.dumps(record, indent=2)) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/start_rob_board_build.py b/platforms/arty-a7-toy/scripts/start_rob_board_build.py new file mode 100644 index 0000000..de57b6d --- /dev/null +++ b/platforms/arty-a7-toy/scripts/start_rob_board_build.py @@ -0,0 +1,63 @@ +"""以独立候选记录执行同一整板流程；不继承旧位流的资格结论。""" + +import argparse +from datetime import datetime +import json +import os +from pathlib import Path +import shutil +import subprocess +import sys + +from start_board_build import ROOT, TZ, save, sha, worker + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--worker", type=Path) + args = parser.parse_args() + if args.worker: + out = args.worker.resolve() + worker(out) + record = json.loads((out / "RUN.json").read_text()) + record["candidate_core_unchanged"] = sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == record["core_sha256"] + record["candidate_memory_unchanged"] = sha(ROOT / "build/serial-bound/FpgaMemories.sv") == record["memory_sha256"] + if not record["candidate_core_unchanged"] or not record["candidate_memory_unchanged"]: + record["status"] = "INPUT_CHANGED_REJECTED" + save(out / "RUN.json", record) + return + prepared = json.loads((ROOT / "build/ROB_RAM_PREPARED.json").read_text()) + for path in ["build/globalrob-check/RESULT.json", "build/BOARD_REGRESSION.json"]: + if json.loads((ROOT / path).read_text())["result"] != "PASS": + raise ValueError("Candidate regression has not passed: " + path) + core = ROOT / "build/serial-bound/ToyLinuxChip.sv" + memories = ROOT / "build/serial-bound/FpgaMemories.sv" + if sha(core) != prepared["core_rtl_sha256"] or sha(memories) != prepared["memory_rtl_sha256"]: + raise ValueError("Candidate inputs changed after preparation") + for path in (ROOT / "build").glob("board-*/RUN.json"): + if json.loads(path.read_text())["status"] in ("CREATED", "RUNNING"): + raise ValueError("An isolated board build is already active") + out = ROOT / "build" / ("board-rob-ram-" + datetime.now(TZ).strftime("%Y%m%d-%H%M%S")) + out.mkdir() + shutil.copytree(ROOT / "board", out / "inputs/board") + files = {str(p.relative_to(ROOT)): sha(p) for p in (ROOT / "board").rglob("*") if p.is_file()} + script = out / "inputs/board/build_board.tcl" + # Keep the input snapshot for audit, execute the identical script at its + # normal root so relative HDL/IP paths resolve without rewriting Tcl. + record = {"status": "CREATED", "optimization": "ROB_OPERAND_BRAM", "timeout_seconds": 3600, + "termination_grace_seconds": 15, "part": "xc7a100tcsg324-1", + "core_sha256": sha(core), "memory_sha256": sha(memories), "board_sources": files, + "execution_script": str(ROOT / "board/build_board.tcl"), "execution_script_sha256": sha(script), + "core_clock_hz": 25000000, "uart_baud": 1000000, + "architectural_profile_unchanged": True, "flash_boot": False, + "physical_boot_tested": False, "inherits_baseline_hardware_qualification": False} + save(out / "RUN.json", record) + with (out / "launcher.log").open("w") as log: + process = subprocess.Popen([sys.executable, str(Path(__file__).resolve()), "--worker", str(out)], + cwd=ROOT, stdout=log, stderr=subprocess.STDOUT, stdin=subprocess.DEVNULL, + start_new_session=True, close_fds=True) + print(json.dumps({"output_directory": str(out), "worker_pid": process.pid, "timeout_seconds": 3600})) + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/scripts/verify_rob_evidence.py b/platforms/arty-a7-toy/scripts/verify_rob_evidence.py new file mode 100644 index 0000000..bbd395a --- /dev/null +++ b/platforms/arty-a7-toy/scripts/verify_rob_evidence.py @@ -0,0 +1,94 @@ +"""核验 ROB RAM 候选档案；实物资格不从旧版本继承。""" + +import argparse +import hashlib +import json +from pathlib import Path +import re + +ROOT = Path(__file__).resolve().parents[1] +ARCHIVE = ROOT / "evidence/2026-10-12/rob-ram" + + +def read(path): + return json.loads(path.read_text(encoding="utf-8")) + + +def sha(path): + return hashlib.sha256(path.read_bytes()).hexdigest() + + +def resources(path): + labels = {"Slice LUTs": "LUT", "Slice Registers": "FF", "Slice": "Slice", + "Block RAM Tile": "BRAM_tiles", "DSPs": "DSP"} + values = {} + for line in path.read_text().splitlines(): + fields = [field.strip() for field in line.split("|")] + if len(fields) > 3 and fields[1] in labels: + values[labels[fields[1]]] = float(fields[2]) + assert set(values) == set(labels.values()) + return values + + +def main(): + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("--core", action="store_true") + args = parser.parse_args() + manifest = read(ARCHIVE / "MANIFEST.json") + for name, expected in manifest["files"].items(): + assert sha(ARCHIVE / name) == expected, name + record = read(ARCHIVE / "RESULT.json") + assert record["result"] == "PASS_ROB_RAM_RTL_AND_BOARD_IMPLEMENTATION" + assert record["physical_board_tested"] is False + assert record["flash_boot_tested"] is False + run = read(ARCHIVE / "implementation/RUN.json") + assert run["status"] == "COMPLETED" and run["exit_code"] == 0 + assert run["bitstream_generated"] and run["timeout_seconds"] == 3600 + assert run["candidate_core_unchanged"] and run["candidate_memory_unchanged"] + assert resources(ARCHIVE / "implementation/routed-utilization.rpt") == record["routed_resources"] + before = read(ROOT / "evidence/2026-10-11/BOARD_RESULT.json")["routed_resources"] + for name, value in record["routed_resources"].items(): + assert value - before[name] == record["resource_delta"][name], name + assert read(ARCHIVE / "ToyLinuxChip.profile.json") == read( + ROOT / "evidence/2026-10-11/ToyLinuxChip.profile.json") + assert read(ARCHIVE / "tests/globalrob/RESULT.json")["result"] == "PASS" + assert "PASS all memory bindings" in (ARCHIVE / "tests/rob-memory-regression.log").read_text() + regressions = read(ARCHIVE / "tests/BOARD_REGRESSION.json") + baseline = read(ROOT / "evidence/2026-10-11/tests/BOARD_REGRESSION.json") + assert regressions["result"] == "PASS" + for name, case in regressions["tests"].items(): + assert case["result"] == "PASS" + assert case["cycles"] == baseline["tests"][name]["cycles"] + assert case["binary_sha256"] == baseline["tests"][name]["binary_sha256"] + linux = read(ARCHIVE / "tests/linux-final/RESULT.json") + assert linux["result"] == "PASS_RTL_LINUX_USERSPACE" and not linux["physical_board_tested"] + transcript = (ARCHIVE / "tests/linux-final/simulation.log").read_text() + for marker in linux["checks"]: + assert marker in transcript, marker + assert "PASS BOARD_LINUX_USERSPACE cycles=273506752" in transcript + timing = (ARCHIVE / "implementation/routed-timing.rpt").read_text() + assert "All user specified timing constraints are met." in timing + rows = timing.split("WNS(ns)", 1)[1].splitlines() + values = next(line.split() for line in rows if re.match(r"\s+-?\d+\.\d+", line)) + assert float(values[0]) == record["timing"]["wns_ns"] >= 0 + assert float(values[4]) == record["timing"]["whs_ns"] >= 0 + assert all(float(values[n]) == 0 for n in [1, 2, 5, 6, 9, 10]) + route = (ARCHIVE / "implementation/route-status.rpt").read_text() + assert re.search(r"nets with routing errors\.+\s*:\s*0\s*:", route) + for name in ["drc.rpt", "cdc.rpt"]: + assert not re.search(r"\b(?:Critical|Error)\b", (ARCHIVE / "implementation" / name).read_text()) + assert read(ARCHIVE / "OPTIN_RESULT.json")["result"] == "PASS_DEFAULT_AND_CANDIDATE_BYTE_IDENTITY" + memory = read(ARCHIVE / "MEMORY_MANIFEST.json") + assert memory["core_rtl_sha256"] == record["core_rtl_sha256"] == run["core_sha256"] + assert memory["memory_rtl_sha256"] == record["memory_rtl_sha256"] == run["memory_sha256"] + for name, expected in record["integration_sources"].items(): + assert sha(ROOT / name) == expected, name + if args.core: + assert sha(ROOT / "build/serial-bound/ToyLinuxChip.sv") == record["core_rtl_sha256"] + assert sha(ROOT / "build/serial-bound/FpgaMemories.sv") == record["memory_rtl_sha256"] + print(f"PASS ROB RAM archive: {len(manifest['files'])} files; unchanged regression cycles; routed candidate") + print("This initial archive predates physical tests; later hardware evidence is in PR #9") + + +if __name__ == "__main__": + main() diff --git a/platforms/arty-a7-toy/src/main/scala/EmitGlobalRobCheck.scala b/platforms/arty-a7-toy/src/main/scala/EmitGlobalRobCheck.scala new file mode 100644 index 0000000..859e462 --- /dev/null +++ b/platforms/arty-a7-toy/src/main/scala/EmitGlobalRobCheck.scala @@ -0,0 +1,110 @@ +package fpga.arty.linux + +import chisel3._ +import chisel3.util._ +import _root_.circt.stage.ChiselStage +import framework.frontend.globalrs.GlobalROB +import framework.frontend.decoder.{DomainId, PostGDCmd} +import framework.memdomain.frontend.cmd.decoder.DISA.MSET_BITPAT + +/** Cycle comparison of register and synchronous-RAM operand storage. */ +class GlobalRobCheck extends Module { + val seed = IO(Input(UInt(32.W))) + val passed = IO(Output(Bool())) + private val b = OriginalToy.serial + val dut = Module(new GlobalROB(b, useOperandRam = true)) + val reference = Module(new GlobalROB(b, useOperandRam = false)) + val cycle = RegInit(0.U(16.W)) + val random = RegInit(seed) + cycle := cycle + 1.U + random := Cat(random(30, 0), random(31) ^ random(21) ^ random(1) ^ random(0)) + assert(cycle < 9000.U, "GlobalROB drain timeout") + + val source = Module(new Queue(new PostGDCmd(b), 2)) + val generated = Wire(new PostGDCmd(b)) + generated := 0.U.asTypeOf(generated) + val config = random(5, 2) === 0.U + generated.domain_id := Mux(config || random(2), DomainId.MEM, DomainId.BALL) + generated.ball_bid := 0.U + generated.cmd.funct := Mux(config, MSET_BITPAT.value.U(7.W), Mux(random(3), 53.U, 66.U)) + generated.cmd.raw_inst := random + generated.cmd.pc := Cat(random, ~random) + generated.cmd.rs1Data := Cat(random, random ^ "h597bdf03".U) + generated.cmd.rs2Data := Mux(config, + Cat(random, 0.U(21.W), 1.U(1.W), 0.U(3.W), random(1, 0), 0.U(5.W)), + Cat(~random, random ^ "h26ac048e".U)) + generated.bankAccess.rd_bank_0_valid := !config && random(8) + generated.bankAccess.rd_bank_1_valid := !config && random(9) + generated.bankAccess.wr_bank_valid := config || random(10) + generated.bankAccess.rd_bank_0_id := random(14, 11) + generated.bankAccess.rd_bank_1_id := random(18, 15) + generated.bankAccess.wr_bank_id := random(22, 19) + source.io.enq.valid := cycle < 5000.U && random(0) + source.io.enq.bits := generated + dut.io.alloc <> source.io.deq + reference.io.alloc.valid := dut.io.alloc.valid + reference.io.alloc.bits := dut.io.alloc.bits + + val completions = Module(new Queue(UInt(log2Ceil(b.frontend.rob_entries).W), 16)) + val active = cycle(9, 6) === 13.U + val ready = completions.io.enq.ready && random(7) && cycle(8, 5) =/= 7.U + dut.io.issue.ready := ready + reference.io.issue.ready := ready + completions.io.enq.valid := dut.io.issue.fire + completions.io.enq.bits := dut.io.issue.bits.rob_id + dut.io.complete.valid := completions.io.deq.valid && random(4) + dut.io.complete.bits := completions.io.deq.bits + reference.io.complete.valid := dut.io.complete.valid + reference.io.complete.bits := dut.io.complete.bits + completions.io.deq.ready := dut.io.complete.ready && random(4) + dut.io.hart_id := 0.U + reference.io.hart_id := 0.U + dut.io.subRobActive := active + reference.io.subRobActive := active + + assert(dut.io.alloc.ready === reference.io.alloc.ready, "ROB allocation timing mismatch") + assert(dut.io.complete.ready === reference.io.complete.ready, "ROB completion timing mismatch") + assert(dut.io.issue.valid === reference.io.issue.valid, "ROB issue timing mismatch") + when(dut.io.issue.valid) { + assert(dut.io.issue.bits.asUInt === reference.io.issue.bits.asUInt, "ROB issue payload mismatch") + } + assert(dut.io.empty === reference.io.empty && dut.io.full === reference.io.full) + assert(dut.io.head_ptr === reference.io.head_ptr) + assert(dut.io.issued_count === reference.io.issued_count) + assert(dut.io.entry_valid.asUInt === reference.io.entry_valid.asUInt) + assert(dut.io.entry_complete.asUInt === reference.io.entry_complete.asUInt) + assert(dut.io.inst_ids.asUInt === reference.io.inst_ids.asUInt) + + val allocated = RegInit(0.U(16.W)) + val issued = RegInit(0.U(16.W)) + val completed = RegInit(0.U(16.W)) + val sawFull = RegInit(false.B) + val sawStall = RegInit(false.B) + val expected = Reg(Vec(b.frontend.rob_entries, chiselTypeOf(generated.cmd))) + val allocationSlot = RegInit(0.U(log2Ceil(b.frontend.rob_entries).W)) + when(dut.io.alloc.fire) { + allocated := allocated + 1.U + expected(allocationSlot) := dut.io.alloc.bits.cmd + allocationSlot := Mux(allocationSlot === (b.frontend.rob_entries - 1).U, + 0.U, allocationSlot + 1.U) + } + when(dut.io.issue.fire) { + issued := issued + 1.U + assert(dut.io.issue.bits.cmd.cmd.asUInt === expected(dut.io.issue.bits.rob_id).asUInt, + "ROB changed accepted command operands") + } + when(dut.io.complete.fire) { completed := completed + 1.U } + when(dut.io.full) { sawFull := true.B } + when(dut.io.issue.valid && !ready) { sawStall := true.B } + passed := cycle > 5005.U && !source.io.deq.valid && dut.io.empty && !completions.io.deq.valid + when(passed) { + assert(allocated === issued && issued === completed && allocated > 64.U) + assert(sawFull && sawStall, "Missing ROB full/stall coverage") + } +} + +object EmitGlobalRobCheck extends App { + ChiselStage.emitSystemVerilogFile(new GlobalRobCheck, + Array("--target-dir", args.headOption.getOrElse("build/globalrob-check")), + Array("-disable-all-randomization", "-strip-debug-info")) +} diff --git a/platforms/arty-a7-toy/tests/tb_globalrob.sv b/platforms/arty-a7-toy/tests/tb_globalrob.sv new file mode 100644 index 0000000..8213b7d --- /dev/null +++ b/platforms/arty-a7-toy/tests/tb_globalrob.sv @@ -0,0 +1,29 @@ +`timescale 1ns/1ps +module tb; + reg clock = 0, reset = 1; + reg [31:0] seed = 32'h12345678; + wire passed; + integer cycles = 0; + GlobalRobCheck dut(.*); + always #5 clock = ~clock; + initial begin + repeat (5) @(negedge clock); + reset = 0; + repeat (1200) @(negedge clock); + reset = 1; seed = 32'hda7a0319; + repeat (5) @(negedge clock); + reset = 0; + repeat (1800) @(negedge clock); + reset = 1; seed = 32'habcdef01; + repeat (5) @(negedge clock); + reset = 0; + end + always @(posedge clock) begin + cycles <= cycles + 1; + if (!reset && passed) begin + $display("PASS GLOBALROB RAM/register cycle comparison, payloads, wrap, stalls, resets cycles=%0d", cycles); + $finish; + end + if (cycles > 15000) $fatal(1, "GlobalROB test timeout"); + end +endmodule